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adding input buffering to bus arbiters to reduce backpressure delay propagation

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This commit is contained in:
Blaise Tine
2020-12-05 17:31:29 -08:00
parent 13a5370254
commit d0f2a3984d
17 changed files with 480 additions and 338 deletions
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86
hw/rtl/VX_cluster.v
View File

@@ -207,38 +207,38 @@ module VX_cluster #(
.TAG_IN_WIDTH (`DCORE_TAG_WIDTH),
.TAG_OUT_WIDTH (`L2CORE_TAG_WIDTH)
) io_arb (
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
// input requests
.io_req_valid_in (per_core_io_req_valid),
.io_req_rw_in (per_core_io_req_rw),
.io_req_byteen_in (per_core_io_req_byteen),
.io_req_addr_in (per_core_io_req_addr),
.io_req_data_in (per_core_io_req_data),
.io_req_tag_in (per_core_io_req_tag),
.io_req_ready_in (per_core_io_req_ready),
.req_valid_in (per_core_io_req_valid),
.req_rw_in (per_core_io_req_rw),
.req_byteen_in (per_core_io_req_byteen),
.req_addr_in (per_core_io_req_addr),
.req_data_in (per_core_io_req_data),
.req_tag_in (per_core_io_req_tag),
.req_ready_in (per_core_io_req_ready),
// output request
.io_req_valid_out (io_req_valid),
.io_req_rw_out (io_req_rw),
.io_req_byteen_out (io_req_byteen),
.io_req_addr_out (io_req_addr),
.io_req_data_out (io_req_data),
.io_req_tag_out (io_req_tag),
.io_req_ready_out (io_req_ready),
.req_valid_out (io_req_valid),
.req_rw_out (io_req_rw),
.req_byteen_out (io_req_byteen),
.req_addr_out (io_req_addr),
.req_data_out (io_req_data),
.req_tag_out (io_req_tag),
.req_ready_out (io_req_ready),
// input responses
.io_rsp_valid_in (per_core_io_rsp_valid),
.io_rsp_data_in (per_core_io_rsp_data),
.io_rsp_tag_in (per_core_io_rsp_tag),
.io_rsp_ready_in (per_core_io_rsp_ready),
.rsp_valid_in (per_core_io_rsp_valid),
.rsp_data_in (per_core_io_rsp_data),
.rsp_tag_in (per_core_io_rsp_tag),
.rsp_ready_in (per_core_io_rsp_ready),
// output response
.io_rsp_valid_out (io_rsp_valid),
.io_rsp_tag_out (io_rsp_tag),
.io_rsp_data_out (io_rsp_data),
.io_rsp_ready_out (io_rsp_ready)
.rsp_valid_out (io_rsp_valid),
.rsp_tag_out (io_rsp_tag),
.rsp_data_out (io_rsp_data),
.rsp_ready_out (io_rsp_ready)
);
VX_csr_io_arb #(
@@ -246,34 +246,34 @@ module VX_cluster #(
.DATA_WIDTH (32),
.ADDR_WIDTH (12)
) csr_io_arb (
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
.request_id (csr_io_req_coreid),
.request_id (csr_io_req_coreid),
// input requests
.csr_io_req_valid_in (csr_io_req_valid),
.csr_io_req_addr_in (csr_io_req_addr),
.csr_io_req_rw_in (csr_io_req_rw),
.csr_io_req_data_in (csr_io_req_data),
.csr_io_req_ready_in (csr_io_req_ready),
.req_valid_in (csr_io_req_valid),
.req_addr_in (csr_io_req_addr),
.req_rw_in (csr_io_req_rw),
.req_data_in (csr_io_req_data),
.req_ready_in (csr_io_req_ready),
// output request
.csr_io_req_valid_out (per_core_csr_io_req_valid),
.csr_io_req_addr_out (per_core_csr_io_req_addr),
.csr_io_req_rw_out (per_core_csr_io_req_rw),
.csr_io_req_data_out (per_core_csr_io_req_data),
.csr_io_req_ready_out (per_core_csr_io_req_ready),
.req_valid_out (per_core_csr_io_req_valid),
.req_addr_out (per_core_csr_io_req_addr),
.req_rw_out (per_core_csr_io_req_rw),
.req_data_out (per_core_csr_io_req_data),
.req_ready_out (per_core_csr_io_req_ready),
// input responses
.csr_io_rsp_valid_in (per_core_csr_io_rsp_valid),
.csr_io_rsp_data_in (per_core_csr_io_rsp_data),
.csr_io_rsp_ready_in (per_core_csr_io_rsp_ready),
.rsp_valid_in (per_core_csr_io_rsp_valid),
.rsp_data_in (per_core_csr_io_rsp_data),
.rsp_ready_in (per_core_csr_io_rsp_ready),
// output response
.csr_io_rsp_valid_out (csr_io_rsp_valid),
.csr_io_rsp_data_out (csr_io_rsp_data),
.csr_io_rsp_ready_out (csr_io_rsp_ready)
.rsp_valid_out (csr_io_rsp_valid),
.rsp_data_out (csr_io_rsp_data),
.rsp_ready_out (csr_io_rsp_ready)
);
assign busy = (| per_core_busy);

96
hw/rtl/VX_csr_io_arb.v
View File

@@ -14,39 +14,39 @@ module VX_csr_io_arb #(
input wire [REQS_BITS-1:0] request_id,
// input requests
input wire csr_io_req_valid_in,
input wire [ADDR_WIDTH-1:0] csr_io_req_addr_in,
input wire csr_io_req_rw_in,
input wire [DATA_WIDTH-1:0] csr_io_req_data_in,
output wire csr_io_req_ready_in,
// output request
output wire [NUM_REQS-1:0] csr_io_req_valid_out,
output wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] csr_io_req_addr_out,
output wire [NUM_REQS-1:0] csr_io_req_rw_out,
output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] csr_io_req_data_out,
input wire [NUM_REQS-1:0] csr_io_req_ready_out,
// input response
input wire [NUM_REQS-1:0] csr_io_rsp_valid_in,
input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] csr_io_rsp_data_in,
output wire [NUM_REQS-1:0] csr_io_rsp_ready_in,
input wire req_valid_in,
input wire [ADDR_WIDTH-1:0] req_addr_in,
input wire req_rw_in,
input wire [DATA_WIDTH-1:0] req_data_in,
output wire req_ready_in,
// output response
output wire csr_io_rsp_valid_out,
output wire [DATA_WIDTH-1:0] csr_io_rsp_data_out,
input wire csr_io_rsp_ready_out
output wire rsp_valid_out,
output wire [DATA_WIDTH-1:0] rsp_data_out,
input wire rsp_ready_out,
// output request
output wire [NUM_REQS-1:0] req_valid_out,
output wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr_out,
output wire [NUM_REQS-1:0] req_rw_out,
output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data_out,
input wire [NUM_REQS-1:0] req_ready_out,
// input response
input wire [NUM_REQS-1:0] rsp_valid_in,
input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_in,
output wire [NUM_REQS-1:0] rsp_ready_in
);
if (NUM_REQS > 1) begin
for (genvar i = 0; i < NUM_REQS; i++) begin
assign csr_io_req_valid_out[i] = csr_io_req_valid_in && (request_id == `REQS_BITS'(i));
assign csr_io_req_addr_out[i] = csr_io_req_addr_in;
assign csr_io_req_rw_out[i] = csr_io_req_rw_in;
assign csr_io_req_data_out[i] = csr_io_req_data_in;
assign req_valid_out[i] = req_valid_in && (request_id == `REQS_BITS'(i));
assign req_addr_out[i] = req_addr_in;
assign req_rw_out[i] = req_rw_in;
assign req_data_out[i] = req_data_in;
end
assign csr_io_req_ready_in = csr_io_req_ready_out[request_id];
assign req_ready_in = req_ready_out[request_id];
end else begin
@@ -54,29 +54,49 @@ module VX_csr_io_arb #(
`UNUSED_VAR (reset)
`UNUSED_VAR (request_id)
assign csr_io_req_valid_out = csr_io_req_valid_in;
assign csr_io_req_addr_out = csr_io_req_addr_in;
assign csr_io_req_rw_out = csr_io_req_rw_in;
assign csr_io_req_data_out = csr_io_req_data_in;
assign csr_io_req_ready_in = csr_io_req_ready_out;
assign req_valid_out = req_valid_in;
assign req_addr_out = req_addr_in;
assign req_rw_out = req_rw_in;
assign req_data_out = req_data_in;
assign req_ready_in = req_ready_out;
end
///////////////////////////////////////////////////////////////////////
// Inputs buffering
wire [NUM_REQS-1:0] rsp_valid_in_qual;
wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_in_qual;
wire [NUM_REQS-1:0] rsp_ready_in_qual;
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (DATA_WIDTH),
.PASSTHRU (NUM_REQS < 4)
) rsp_buffer (
.clk (clk),
.reset (reset),
.valid_in (rsp_valid_in[i]),
.data_in (rsp_data_in[i]),
.ready_in (rsp_ready_in[i]),
.valid_out (rsp_valid_in_qual[i]),
.data_out (rsp_data_in_qual[i]),
.ready_out (rsp_ready_in_qual[i])
);
end
VX_stream_arbiter #(
.NUM_REQS(NUM_REQS),
.DATAW(DATA_WIDTH),
.BUFFERED(NUM_REQS >= 4)
) rsp_arb (
.clk (clk),
.reset (reset),
.valid_in (csr_io_rsp_valid_in),
.valid_out (csr_io_rsp_valid_out),
.data_in (csr_io_rsp_data_in),
.data_out (csr_io_rsp_data_out),
.ready_in (csr_io_rsp_ready_in),
.ready_out (csr_io_rsp_ready_out)
.clk (clk),
.reset (reset),
.valid_in (rsp_valid_in_qual),
.data_in (rsp_data_in_qual),
.ready_in (rsp_ready_in_qual),
.valid_out (rsp_valid_out),
.data_out (rsp_data_out),
.ready_out (rsp_ready_out)
);
endmodule

128
hw/rtl/VX_io_arb.v
View File

@@ -14,96 +14,118 @@ module VX_io_arb #(
input wire reset,
// input requests
input wire [NUM_REQS-1:0][`NUM_THREADS-1:0] io_req_valid_in,
input wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] io_req_tag_in,
input wire [NUM_REQS-1:0][`NUM_THREADS-1:0][ADDR_WIDTH-1:0] io_req_addr_in,
input wire [NUM_REQS-1:0] io_req_rw_in,
input wire [NUM_REQS-1:0][`NUM_THREADS-1:0][WORD_SIZE-1:0] io_req_byteen_in,
input wire [NUM_REQS-1:0][`NUM_THREADS-1:0][WORD_WIDTH-1:0] io_req_data_in,
output wire [NUM_REQS-1:0] io_req_ready_in,
input wire [NUM_REQS-1:0][`NUM_THREADS-1:0] req_valid_in,
input wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] req_tag_in,
input wire [NUM_REQS-1:0][`NUM_THREADS-1:0][ADDR_WIDTH-1:0] req_addr_in,
input wire [NUM_REQS-1:0] req_rw_in,
input wire [NUM_REQS-1:0][`NUM_THREADS-1:0][WORD_SIZE-1:0] req_byteen_in,
input wire [NUM_REQS-1:0][`NUM_THREADS-1:0][WORD_WIDTH-1:0] req_data_in,
output wire [NUM_REQS-1:0] req_ready_in,
// output request
output wire [`NUM_THREADS-1:0] io_req_valid_out,
output wire [TAG_OUT_WIDTH-1:0] io_req_tag_out,
output wire [`NUM_THREADS-1:0][ADDR_WIDTH-1:0] io_req_addr_out,
output wire io_req_rw_out,
output wire [`NUM_THREADS-1:0][WORD_SIZE-1:0] io_req_byteen_out,
output wire [`NUM_THREADS-1:0][WORD_WIDTH-1:0] io_req_data_out,
input wire io_req_ready_out,
output wire [`NUM_THREADS-1:0] req_valid_out,
output wire [TAG_OUT_WIDTH-1:0] req_tag_out,
output wire [`NUM_THREADS-1:0][ADDR_WIDTH-1:0] req_addr_out,
output wire req_rw_out,
output wire [`NUM_THREADS-1:0][WORD_SIZE-1:0] req_byteen_out,
output wire [`NUM_THREADS-1:0][WORD_WIDTH-1:0] req_data_out,
input wire req_ready_out,
// input response
output wire [NUM_REQS-1:0] io_rsp_valid_in,
output wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] io_rsp_tag_in,
output wire [NUM_REQS-1:0][WORD_WIDTH-1:0] io_rsp_data_in,
input wire [NUM_REQS-1:0] io_rsp_ready_in,
output wire [NUM_REQS-1:0] rsp_valid_in,
output wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] rsp_tag_in,
output wire [NUM_REQS-1:0][WORD_WIDTH-1:0] rsp_data_in,
input wire [NUM_REQS-1:0] rsp_ready_in,
// output response
input wire io_rsp_valid_out,
input wire [TAG_OUT_WIDTH-1:0] io_rsp_tag_out,
input wire [WORD_WIDTH-1:0] io_rsp_data_out,
output wire io_rsp_ready_out
input wire rsp_valid_out,
input wire [TAG_OUT_WIDTH-1:0] rsp_tag_out,
input wire [WORD_WIDTH-1:0] rsp_data_out,
output wire rsp_ready_out
);
localparam DATAW = `NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH);
if (NUM_REQS > 1) begin
wire [NUM_REQS-1:0] valids;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign valids[i] = (| io_req_valid_in[i]);
assign valids[i] = (| req_valid_in[i]);
end
wire [NUM_REQS-1:0][(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH))-1:0] data_in;
wire [NUM_REQS-1:0][DATAW-1:0] data_in;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign data_in[i] = {io_req_valid_in[i], {io_req_tag_in[i], REQS_BITS'(i)}, io_req_addr_in[i], io_req_rw_in[i], io_req_byteen_in[i], io_req_data_in[i]};
assign data_in[i] = {req_valid_in[i], {req_tag_in[i], REQS_BITS'(i)}, req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]};
end
wire [`NUM_THREADS-1:0] io_req_tmask_out;
wire io_req_valid_out_unqual;
// Inputs buffering
wire [NUM_REQS-1:0] req_valid_in_qual;
wire [NUM_REQS-1:0][DATAW-1:0] req_data_in_qual;
wire [NUM_REQS-1:0] req_ready_in_qual;
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (NUM_REQS < 4)
) req_buffer (
.clk (clk),
.reset (reset),
.valid_in (valids[i]),
.data_in (data_in[i]),
.ready_in (req_ready_in[i]),
.valid_out (req_valid_in_qual[i]),
.data_out (req_data_in_qual[i]),
.ready_out (req_ready_in_qual[i])
);
end
wire [`NUM_THREADS-1:0] req_tmask_out;
wire req_valid_out_unqual;
VX_stream_arbiter #(
.NUM_REQS(NUM_REQS),
.DATAW(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH)),
.BUFFERED(NUM_REQS >= 4)
.NUM_REQS (NUM_REQS),
.DATAW (DATAW),
.BUFFERED (NUM_REQS >= 4)
) req_arb (
.clk (clk),
.reset (reset),
.valid_in (valids),
.valid_out (io_req_valid_out_unqual),
.data_in (data_in),
.data_out ({io_req_tmask_out, io_req_tag_out, io_req_addr_out, io_req_rw_out, io_req_byteen_out, io_req_data_out}),
.ready_in (io_req_ready_in),
.ready_out (io_req_ready_out)
.valid_in (req_valid_in_qual),
.data_in (req_data_in_qual),
.ready_in (req_ready_in_qual),
.valid_out (req_valid_out_unqual),
.data_out ({req_tmask_out, req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out}),
.ready_out (req_ready_out)
);
assign io_req_valid_out = {`NUM_THREADS{io_req_valid_out_unqual}} & io_req_tmask_out;
assign req_valid_out = {`NUM_THREADS{req_valid_out_unqual}} & req_tmask_out;
///////////////////////////////////////////////////////////////////////
wire [REQS_BITS-1:0] rsp_sel = io_rsp_tag_out[REQS_BITS-1:0];
wire [REQS_BITS-1:0] rsp_sel = rsp_tag_out[REQS_BITS-1:0];
for (genvar i = 0; i < NUM_REQS; i++) begin
assign io_rsp_valid_in[i] = io_rsp_valid_out && (rsp_sel == REQS_BITS'(i));
assign io_rsp_tag_in[i] = io_rsp_tag_out[REQS_BITS +: TAG_IN_WIDTH];
assign io_rsp_data_in[i] = io_rsp_data_out;
assign rsp_valid_in[i] = rsp_valid_out && (rsp_sel == REQS_BITS'(i));
assign rsp_tag_in[i] = rsp_tag_out[REQS_BITS +: TAG_IN_WIDTH];
assign rsp_data_in[i] = rsp_data_out;
end
assign io_rsp_ready_out = io_rsp_ready_in[rsp_sel];
assign rsp_ready_out = rsp_ready_in[rsp_sel];
end else begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign io_req_valid_out = io_req_valid_in;
assign io_req_tag_out = io_req_tag_in;
assign io_req_addr_out = io_req_addr_in;
assign io_req_rw_out = io_req_rw_in;
assign io_req_byteen_out = io_req_byteen_in;
assign io_req_data_out = io_req_data_in;
assign io_req_ready_in = io_req_ready_out;
assign req_valid_out = req_valid_in;
assign req_tag_out = req_tag_in;
assign req_addr_out = req_addr_in;
assign req_rw_out = req_rw_in;
assign req_byteen_out = req_byteen_in;
assign req_data_out = req_data_in;
assign req_ready_in = req_ready_out;
assign io_rsp_valid_in = io_rsp_valid_out;
assign io_rsp_tag_in = io_rsp_tag_out;
assign io_rsp_data_in = io_rsp_data_out;
assign io_rsp_ready_out = io_rsp_ready_in;
assign rsp_valid_in = rsp_valid_out;
assign rsp_tag_in = rsp_tag_out;
assign rsp_data_in = rsp_data_out;
assign rsp_ready_out = rsp_ready_in;
end

38
hw/rtl/VX_mem_arb.v
View File

@@ -43,25 +43,47 @@ module VX_mem_arb #(
input wire [DATA_WIDTH-1:0] rsp_data_in,
output wire rsp_ready_in
);
localparam DATAW = TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH;
if (NUM_REQS > 1) begin
wire [NUM_REQS-1:0][(TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH)-1:0] data_in;
wire [NUM_REQS-1:0][DATAW-1:0] data_in;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign data_in[i] = {{req_tag_in[i], REQS_BITS'(i)}, req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]};
end
// Inputs buffering
wire [NUM_REQS-1:0] req_valid_in_qual;
wire [NUM_REQS-1:0][DATAW-1:0] req_data_in_qual;
wire [NUM_REQS-1:0] req_ready_in_qual;
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (NUM_REQS < 4)
) req_buffer (
.clk (clk),
.reset (reset),
.valid_in (req_valid_in[i]),
.data_in (data_in[i]),
.ready_in (req_ready_in[i]),
.valid_out (req_valid_in_qual[i]),
.data_out (req_data_in_qual[i]),
.ready_out (req_ready_in_qual[i])
);
end
VX_stream_arbiter #(
.NUM_REQS(NUM_REQS),
.DATAW(TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH),
.BUFFERED(NUM_REQS >= 4)
.NUM_REQS (NUM_REQS),
.DATAW (DATAW),
.BUFFERED (NUM_REQS >= 4)
) req_arb (
.clk (clk),
.reset (reset),
.valid_in (req_valid_in),
.valid_in (req_valid_in_qual),
.data_in (req_data_in_qual),
.ready_in (req_ready_in_qual),
.valid_out (req_valid_out),
.data_in (data_in),
.data_out ({req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out}),
.ready_in (req_ready_in),
.data_out ({req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out}),
.ready_out (req_ready_out)
);

91
hw/rtl/VX_pipeline.v
View File

@@ -55,7 +55,10 @@ module VX_pipeline #(
output wire busy,
output wire ebreak
);
// Dcache
//
// Dcache request
//
VX_cache_core_req_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
@@ -63,6 +66,18 @@ module VX_pipeline #(
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) core_dcache_req_if();
assign dcache_req_valid = core_dcache_req_if.valid;
assign dcache_req_rw = core_dcache_req_if.rw;
assign dcache_req_byteen = core_dcache_req_if.byteen;
assign dcache_req_addr = core_dcache_req_if.addr;
assign dcache_req_data = core_dcache_req_if.data;
assign dcache_req_tag = core_dcache_req_if.tag;
assign core_dcache_req_if.ready = dcache_req_ready;
//
// Dcache response
//
VX_cache_core_rsp_if #(
.NUM_REQS(`NUM_THREADS),
.WORD_SIZE(4),
@@ -70,33 +85,69 @@ module VX_pipeline #(
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) core_dcache_rsp_if();
// Icache
assign core_dcache_rsp_if.valid = dcache_rsp_valid;
assign core_dcache_rsp_if.data = dcache_rsp_data;
assign core_dcache_rsp_if.tag = dcache_rsp_tag;
assign dcache_rsp_ready = core_dcache_rsp_if.ready;
//
// Icache request
//
VX_cache_core_req_if #(
.NUM_REQS(1),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
) core_icache_req_if();
) core_icache_req_if();
assign icache_req_valid = core_icache_req_if.valid;
assign icache_req_rw = core_icache_req_if.rw;
assign icache_req_byteen = core_icache_req_if.byteen;
assign icache_req_addr = core_icache_req_if.addr;
assign icache_req_data = core_icache_req_if.data;
assign icache_req_tag = core_icache_req_if.tag;
assign core_icache_req_if.ready = icache_req_ready;
//
// Icache response
//
VX_cache_core_rsp_if #(
.NUM_REQS(1),
.WORD_SIZE(4),
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
) core_icache_rsp_if();
) core_icache_rsp_if();
assign core_icache_rsp_if.valid = icache_rsp_valid;
assign core_icache_rsp_if.data = icache_rsp_data;
assign core_icache_rsp_if.tag = icache_rsp_tag;
assign icache_rsp_ready = core_icache_rsp_if.ready;
//
// CSR IO request
//
// CSR I/O
VX_csr_io_req_if csr_io_req_if();
assign csr_io_req_if.valid = csr_io_req_valid;
assign csr_io_req_if.rw = csr_io_req_rw;
assign csr_io_req_if.addr = csr_io_req_addr;
assign csr_io_req_if.data = csr_io_req_data;
assign csr_io_req_ready = csr_io_req_if.ready;
//
// CSR IO response
//
VX_csr_io_rsp_if csr_io_rsp_if();
assign csr_io_rsp_valid = csr_io_rsp_if.valid;
assign csr_io_rsp_data = csr_io_rsp_if.data;
assign csr_io_rsp_if.ready = csr_io_rsp_ready;
assign csr_io_rsp_if.ready = csr_io_rsp_ready;
///////////////////////////////////////////////////////////////////////////
VX_cmt_to_csr_if cmt_to_csr_if();
VX_decode_if decode_if();
@@ -219,32 +270,6 @@ module VX_pipeline #(
.writeback_if (writeback_if),
.cmt_to_csr_if (cmt_to_csr_if)
);
assign dcache_req_valid = core_dcache_req_if.valid;
assign dcache_req_rw = core_dcache_req_if.rw;
assign dcache_req_byteen = core_dcache_req_if.byteen;
assign dcache_req_addr = core_dcache_req_if.addr;
assign dcache_req_data = core_dcache_req_if.data;
assign dcache_req_tag = core_dcache_req_if.tag;
assign core_dcache_req_if.ready = dcache_req_ready;
assign core_dcache_rsp_if.valid = dcache_rsp_valid;
assign core_dcache_rsp_if.data = dcache_rsp_data;
assign core_dcache_rsp_if.tag = dcache_rsp_tag;
assign dcache_rsp_ready = core_dcache_rsp_if.ready;
assign icache_req_valid = core_icache_req_if.valid;
assign icache_req_rw = core_icache_req_if.rw;
assign icache_req_byteen = core_icache_req_if.byteen;
assign icache_req_addr = core_icache_req_if.addr;
assign icache_req_data = core_icache_req_if.data;
assign icache_req_tag = core_icache_req_if.tag;
assign core_icache_req_if.ready = icache_req_ready;
assign core_icache_rsp_if.valid = icache_rsp_valid;
assign core_icache_rsp_if.data = icache_rsp_data;
assign core_icache_rsp_if.tag = icache_rsp_tag;
assign icache_rsp_ready = core_icache_rsp_if.ready;
);
endmodule

86
hw/rtl/Vortex.v
View File

@@ -248,38 +248,38 @@ module Vortex (
.TAG_IN_WIDTH (`L2CORE_TAG_WIDTH),
.TAG_OUT_WIDTH (`L3CORE_TAG_WIDTH)
) io_arb (
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
// input requests
.io_req_valid_in (per_cluster_io_req_valid),
.io_req_rw_in (per_cluster_io_req_rw),
.io_req_byteen_in (per_cluster_io_req_byteen),
.io_req_addr_in (per_cluster_io_req_addr),
.io_req_data_in (per_cluster_io_req_data),
.io_req_tag_in (per_cluster_io_req_tag),
.io_req_ready_in (per_cluster_io_req_ready),
.req_valid_in (per_cluster_io_req_valid),
.req_rw_in (per_cluster_io_req_rw),
.req_byteen_in (per_cluster_io_req_byteen),
.req_addr_in (per_cluster_io_req_addr),
.req_data_in (per_cluster_io_req_data),
.req_tag_in (per_cluster_io_req_tag),
.req_ready_in (per_cluster_io_req_ready),
// output request
.io_req_valid_out (io_req_valid),
.io_req_rw_out (io_req_rw),
.io_req_byteen_out (io_req_byteen),
.io_req_addr_out (io_req_addr),
.io_req_data_out (io_req_data),
.io_req_tag_out (io_req_tag),
.io_req_ready_out (io_req_ready),
.req_valid_out (io_req_valid),
.req_rw_out (io_req_rw),
.req_byteen_out (io_req_byteen),
.req_addr_out (io_req_addr),
.req_data_out (io_req_data),
.req_tag_out (io_req_tag),
.req_ready_out (io_req_ready),
// input responses
.io_rsp_valid_in (per_cluster_io_rsp_valid),
.io_rsp_data_in (per_cluster_io_rsp_data),
.io_rsp_tag_in (per_cluster_io_rsp_tag),
.io_rsp_ready_in (per_cluster_io_rsp_ready),
.rsp_valid_in (per_cluster_io_rsp_valid),
.rsp_data_in (per_cluster_io_rsp_data),
.rsp_tag_in (per_cluster_io_rsp_tag),
.rsp_ready_in (per_cluster_io_rsp_ready),
// output response
.io_rsp_valid_out (io_rsp_valid),
.io_rsp_tag_out (io_rsp_tag),
.io_rsp_data_out (io_rsp_data),
.io_rsp_ready_out (io_rsp_ready)
.rsp_valid_out (io_rsp_valid),
.rsp_tag_out (io_rsp_tag),
.rsp_data_out (io_rsp_data),
.rsp_ready_out (io_rsp_ready)
);
VX_csr_io_arb #(
@@ -287,34 +287,34 @@ module Vortex (
.DATA_WIDTH (32),
.ADDR_WIDTH (12)
) csr_io_arb (
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
.request_id (csr_io_request_id),
.request_id (csr_io_request_id),
// input requests
.csr_io_req_valid_in (csr_io_req_valid),
.csr_io_req_addr_in (csr_io_req_addr),
.csr_io_req_rw_in (csr_io_req_rw),
.csr_io_req_data_in (csr_io_req_data),
.csr_io_req_ready_in (csr_io_req_ready),
.req_valid_in (csr_io_req_valid),
.req_addr_in (csr_io_req_addr),
.req_rw_in (csr_io_req_rw),
.req_data_in (csr_io_req_data),
.req_ready_in (csr_io_req_ready),
// output request
.csr_io_req_valid_out (per_cluster_csr_io_req_valid),
.csr_io_req_addr_out (per_cluster_csr_io_req_addr),
.csr_io_req_rw_out (per_cluster_csr_io_req_rw),
.csr_io_req_data_out (per_cluster_csr_io_req_data),
.csr_io_req_ready_out (per_cluster_csr_io_req_ready),
.req_valid_out (per_cluster_csr_io_req_valid),
.req_addr_out (per_cluster_csr_io_req_addr),
.req_rw_out (per_cluster_csr_io_req_rw),
.req_data_out (per_cluster_csr_io_req_data),
.req_ready_out (per_cluster_csr_io_req_ready),
// input responses
.csr_io_rsp_valid_in (per_cluster_csr_io_rsp_valid),
.csr_io_rsp_data_in (per_cluster_csr_io_rsp_data),
.csr_io_rsp_ready_in (per_cluster_csr_io_rsp_ready),
.rsp_valid_in (per_cluster_csr_io_rsp_valid),
.rsp_data_in (per_cluster_csr_io_rsp_data),
.rsp_ready_in (per_cluster_csr_io_rsp_ready),
// output response
.csr_io_rsp_valid_out (csr_io_rsp_valid),
.csr_io_rsp_data_out (csr_io_rsp_data),
.csr_io_rsp_ready_out (csr_io_rsp_ready)
.rsp_valid_out (csr_io_rsp_valid),
.rsp_data_out (csr_io_rsp_data),
.rsp_ready_out (csr_io_rsp_ready)
);
assign busy = (| per_cluster_busy);

16
hw/rtl/cache/VX_cache.v vendored
View File

@@ -361,11 +361,11 @@ module VX_cache #(
) dram_req_arb (
.clk (clk),
.reset (reset),
.valid_in (per_bank_dram_req_valid),
.valid_out (dram_req_valid),
.data_in (data_in),
.data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}),
.ready_in (per_bank_dram_req_ready),
.valid_in (per_bank_dram_req_valid),
.data_in (data_in),
.ready_in (per_bank_dram_req_ready),
.valid_out (dram_req_valid),
.data_out ({dram_req_addr, dram_req_rw, dram_req_byteen, dram_req_data}),
.ready_out (dram_req_ready)
);
end else begin
@@ -392,10 +392,10 @@ module VX_cache #(
.clk (clk),
.reset (reset),
.valid_in (per_bank_snp_rsp_valid),
.valid_out (snp_rsp_valid),
.data_in (per_bank_snp_rsp_tag),
.data_out (snp_rsp_tag),
.ready_in (per_bank_snp_rsp_ready),
.ready_in (per_bank_snp_rsp_ready),
.valid_out (snp_rsp_valid),
.data_out (snp_rsp_tag),
.ready_out (snp_rsp_ready)
);
end else begin

10
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
View File

@@ -18,6 +18,7 @@ module VX_cache_core_req_bank_sel #(
input wire [NUM_BANKS-1:0] per_bank_ready
);
if (NUM_BANKS > 1) begin
reg [NUM_BANKS-1:0][NUM_REQS-1:0] per_bank_valid_r;
reg [NUM_BANKS-1:0] per_bank_ready_ignore;
reg [NUM_BANKS-1:0] per_bank_ready_other;
@@ -29,8 +30,9 @@ module VX_cache_core_req_bank_sel #(
for (integer i = 0; i < NUM_BANKS; i++) begin
for (integer j = 0; j < NUM_BANKS; j++) begin
if (i != j)
if (i != j) begin
per_bank_ready_other[i] &= (per_bank_ready[j] | per_bank_ready_ignore[j]);
end
end
end
@@ -45,11 +47,15 @@ module VX_cache_core_req_bank_sel #(
assign per_bank_valid[i][j] = per_bank_valid_r[i][j] & per_bank_ready_other[i];
end
end
assign core_req_ready = & (per_bank_ready | per_bank_ready_ignore);
end else begin
end else begin
`UNUSED_VAR (core_req_addr)
assign per_bank_valid = core_req_valid;
assign core_req_ready = per_bank_ready;
end
endmodule

9
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
View File

@@ -42,10 +42,11 @@ module VX_cache_core_rsp_merge #(
always @(*) begin
core_rsp_valid_unqual = 0;
core_rsp_tag_unqual = 'x;
sel_tag_id = 'x;
core_rsp_data_unqual = 'x;
core_rsp_bank_select = 0;
core_rsp_data_unqual = 'x;
core_rsp_bank_select = 0;
sel_tag_id = 'x;
for (integer i = 0; i < NUM_BANKS; i++) begin
if (per_bank_core_rsp_valid[i]) begin
core_rsp_tag_unqual = per_bank_core_rsp_tag[i];
@@ -90,7 +91,7 @@ module VX_cache_core_rsp_merge #(
VX_generic_register #(
.N(NUM_REQS + (NUM_REQS *`WORD_WIDTH) + (`CORE_REQ_TAG_COUNT * CORE_TAG_WIDTH)),
.R(NUM_REQS),
.PASSTHRU(NUM_BANKS <= 2)
.PASSTHRU(NUM_BANKS < 4)
) pipe_reg (
.clk (clk),
.reset (reset),

42
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -27,16 +27,16 @@ module VX_snp_forwarder #(
input wire snp_rsp_ready,
// Snoop Forwarding out
output wire [NUM_REQS-1:0] snp_fwdout_valid,
output wire [NUM_REQS-1:0] snp_fwdout_valid,
output wire [NUM_REQS-1:0][DST_ADDR_WIDTH-1:0] snp_fwdout_addr,
output wire [NUM_REQS-1:0] snp_fwdout_inv,
output wire [NUM_REQS-1:0][LOG_SNRQ_SIZE-1:0] snp_fwdout_tag,
input wire [NUM_REQS-1:0] snp_fwdout_ready,
output wire [NUM_REQS-1:0] snp_fwdout_inv,
output wire [NUM_REQS-1:0][LOG_SNRQ_SIZE-1:0] snp_fwdout_tag,
input wire [NUM_REQS-1:0] snp_fwdout_ready,
// Snoop forwarding in
input wire [NUM_REQS-1:0] snp_fwdin_valid,
input wire [NUM_REQS-1:0] snp_fwdin_valid,
input wire [NUM_REQS-1:0][LOG_SNRQ_SIZE-1:0] snp_fwdin_tag,
output wire [NUM_REQS-1:0] snp_fwdin_ready
output wire [NUM_REQS-1:0] snp_fwdin_ready
);
localparam ADDR_DIFF = DST_ADDR_WIDTH - SRC_ADDR_WIDTH;
localparam NUM_REQUESTS_QUAL = NUM_REQS * (1 << ADDR_DIFF);
@@ -44,6 +44,26 @@ module VX_snp_forwarder #(
`STATIC_ASSERT(NUM_REQS > 1, ("invalid value"))
// Inputs buffering
wire [NUM_REQS-1:0] snp_fwdin_valid_qual;
wire [NUM_REQS-1:0][LOG_SNRQ_SIZE-1:0] snp_fwdin_tag_qual;
wire [NUM_REQS-1:0] snp_fwdin_ready_qual;
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (LOG_SNRQ_SIZE),
.PASSTHRU (NUM_REQS < 4)
) snp_fwdin_buffer (
.clk (clk),
.reset (reset),
.valid_in (snp_fwdin_valid[i]),
.data_in (snp_fwdin_tag[i]),
.ready_in (snp_fwdin_ready[i]),
.valid_out (snp_fwdin_valid_qual[i]),
.data_out (snp_fwdin_tag_qual[i]),
.ready_out (snp_fwdin_ready_qual[i])
);
end
reg [REQ_QUAL_BITS:0] pending_cntrs [SNRQ_SIZE-1:0];
wire [LOG_SNRQ_SIZE-1:0] sfq_write_addr, sfq_read_addr;
@@ -167,11 +187,11 @@ module VX_snp_forwarder #(
) snp_fwdin_arb (
.clk (clk),
.reset (reset),
.valid_in (snp_fwdin_valid),
.valid_out (fwdin_valid),
.data_in (snp_fwdin_tag),
.data_out (fwdin_tag),
.ready_in (snp_fwdin_ready),
.valid_in (snp_fwdin_valid_qual),
.data_in (snp_fwdin_tag_qual),
.ready_in (snp_fwdin_ready_qual),
.valid_out (fwdin_valid),
.data_out (fwdin_tag),
.ready_out (fwdin_ready)
);

60
hw/rtl/libs/VX_elastic_buffer.v
View File

@@ -4,7 +4,8 @@ module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter BUFFERED = 0,
parameter FASTRAM = 0
parameter FASTRAM = 0,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
@@ -16,30 +17,43 @@ module VX_elastic_buffer #(
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
wire empty, full;
);
if (PASSTHRU) begin
wire push = valid_in && ready_in;
wire pop = valid_out && ready_out;
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
VX_generic_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED),
.FASTRAM (FASTRAM)
) queue (
.clk (clk),
.reset (reset),
.push (push),
.pop (pop),
.data_in(data_in),
.data_out(data_out),
.empty (empty),
.full (full),
`UNUSED_PIN (size)
);
assign valid_out = valid_in;
assign data_out = data_in;
assign ready_in = ready_out;
assign ready_in = ~full;
assign valid_out = ~empty;
end else begin
wire empty, full;
wire push = valid_in && ready_in;
wire pop = valid_out && ready_out;
VX_generic_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED),
.FASTRAM (FASTRAM)
) queue (
.clk (clk),
.reset (reset),
.push (push),
.pop (pop),
.data_in(data_in),
.data_out(data_out),
.empty (empty),
.full (full),
`UNUSED_PIN (size)
);
assign ready_in = ~full;
assign valid_out = ~empty;
end
endmodule

44
hw/rtl/libs/VX_fair_arbiter.v
View File

@@ -7,8 +7,8 @@ module VX_fair_arbiter #(
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire enable,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid
@@ -24,12 +24,13 @@ module VX_fair_arbiter #(
end else begin
reg [NUM_REQS-1:0] remaining;
wire [NUM_REQS-1:0] remaining_next;
wire [NUM_REQS-1:0] requests_use;
reg use_buffer;
reg [NUM_REQS-1:0] remaining;
reg use_buffer;
always @(posedge clk) begin
wire [NUM_REQS-1:0] requests_use = use_buffer ? remaining : requests;
wire [NUM_REQS-1:0] remaining_next = requests_use & ~grant_onehot;
always @(posedge clk) begin
if (reset) begin
remaining <= 0;
use_buffer <= 0;
@@ -38,26 +39,19 @@ module VX_fair_arbiter #(
use_buffer <= (remaining_next != 0);
end
end
assign requests_use = use_buffer ? remaining : requests;
VX_priority_encoder #(
.N(NUM_REQS)
) priority_encoder (
.data_in (requests_use),
.data_out (grant_index),
.valid_out (grant_valid)
VX_fixed_arbiter #(
.NUM_REQS(NUM_REQS),
.LOCK_ENABLE(LOCK_ENABLE)
) fixed_arbiter (
.clk (clk),
.reset (reset),
.enable (enable),
.requests (requests_use),
.grant_index (grant_index),
.grant_onehot (grant_onehot),
.grant_valid (grant_valid)
);
reg [NUM_REQS-1:0] grant_onehot_r;
always @(*) begin
grant_onehot_r = NUM_REQS'(0);
grant_onehot_r[grant_index] = 1;
end
assign remaining_next = requests_use & ~grant_onehot_r;
assign grant_onehot = grant_onehot_r;
end
endmodule

27
hw/rtl/libs/VX_fixed_arbiter.v
View File

@@ -26,21 +26,24 @@ module VX_fixed_arbiter #(
end else begin
VX_priority_encoder # (
.N(NUM_REQS)
) priority_encoder (
.data_in (requests),
.data_out (grant_index),
.valid_out (grant_valid)
);
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [NUM_REQS-1:0] grant_onehot_r;
always @(*) begin
grant_onehot_r = NUM_REQS'(0);
grant_onehot_r[grant_index] = 1;
end
always @(*) begin
grant_index_r = 'x;
grant_onehot_r = 'x;
for (integer i = 0; i < NUM_REQS; ++i) begin
if (requests[i]) begin
grant_index_r = LOG_NUM_REQS'(i);
grant_onehot_r = NUM_REQS'(1) << i;
break;
end
end
end
assign grant_index = grant_index_r;
assign grant_onehot = grant_onehot_r;
assign grant_valid = (| requests);
end
endmodule

2
hw/rtl/libs/VX_matrix_arbiter.v
View File

@@ -7,8 +7,8 @@ module VX_matrix_arbiter #(
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire enable,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid

2
hw/rtl/libs/VX_priority_encoder.v
View File

@@ -11,7 +11,7 @@ module VX_priority_encoder #(
reg [`LOG2UP(N)-1:0] data_out_r;
always @(*) begin
data_out_r = 0;
data_out_r = 'x;
for (integer i = 0; i < N; i++) begin
if (data_in[i]) begin
data_out_r = LOGN'(i);

4
hw/rtl/libs/VX_rr_arbiter.v
View File

@@ -6,9 +6,9 @@ module VX_rr_arbiter #(
parameter LOG_NUM_REQS = $clog2(NUM_REQS)
) (
input wire clk,
input wire reset,
input wire [NUM_REQS-1:0] requests,
input wire reset,
input wire enable,
input wire [NUM_REQS-1:0] requests,
output wire [LOG_NUM_REQS-1:0] grant_index,
output wire [NUM_REQS-1:0] grant_onehot,
output wire grant_valid

77
hw/rtl/libs/VX_skid_buffer.v
View File

@@ -1,7 +1,8 @@
`include "VX_platform.vh"
module VX_skid_buffer #(
parameter DATAW = 1
parameter DATAW = 1,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
@@ -13,42 +14,56 @@ module VX_skid_buffer #(
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
reg valid_out_r;
reg use_buffer;
wire push = valid_in && ready_in;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
use_buffer <= 0;
end else begin
if (ready_out) begin
use_buffer <= 0;
);
if (PASSTHRU) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign valid_out = valid_in;
assign data_out = data_in;
assign ready_in = ready_out;
end else begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;
reg valid_out_r;
reg use_buffer;
wire push = valid_in && ready_in;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
use_buffer <= 0;
end else begin
if (ready_out) begin
use_buffer <= 0;
end
if (push && valid_out_r && !ready_out) begin
assert(!use_buffer);
use_buffer <= 1;
end
if (!valid_out_r || ready_out) begin
valid_out_r <= valid_in || use_buffer;
end
end
if (push && valid_out_r && !ready_out) begin
assert(!use_buffer);
use_buffer <= 1;
if (push) begin
buffer <= data_in;
end
if (!valid_out_r || ready_out) begin
valid_out_r <= valid_in || use_buffer;
data_out_r <= use_buffer ? buffer : data_in;
end
end
if (push) begin
buffer <= data_in;
end
if (!valid_out_r || ready_out) begin
data_out_r <= use_buffer ? buffer : data_in;
end
assign ready_in = !use_buffer;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
end
assign ready_in = !use_buffer;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
endmodule