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d4e7b28be85c37c4ff1cff5ca549f29942efcb58
vortex/hw/rtl/libs
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Blaise Tine d4e7b28be8 cache refactoring
2021-01-17 00:18:56 -08:00
..
VX_bypass_buffer.v
reset networks optimization
2020-11-16 01:12:02 -08:00
VX_divider.v
multiplier unit optimization - using fifo for metadata, shift register optimization
2020-12-26 11:23:21 -08:00
VX_dp_ram.v
cache refactoring
2021-01-17 00:18:56 -08:00
VX_elastic_buffer.v
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_fair_arbiter.v
adding input buffering to bus arbiters to reduce backpressure delay propagation
2020-12-05 17:31:29 -08:00
VX_fifo_queue.v
fixed l2/l3 caches related bugs
2021-01-09 16:32:55 -08:00
VX_fixed_arbiter.v
data/dram bus refactoring
2020-12-06 03:37:22 -08:00
VX_index_buffer.v
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_index_queue.v
reset networks optimization
2020-11-16 01:12:02 -08:00
VX_lzc.v
minor update
2021-01-10 22:03:23 -08:00
VX_matrix_arbiter.v
adding input buffering to bus arbiters to reduce backpressure delay propagation
2020-12-05 17:31:29 -08:00
VX_multiplier.v
RAM blocks inference fixes
2020-11-30 14:02:47 -08:00
VX_onehot_encooder.v
adding stream arbiter
2020-12-03 06:40:23 -08:00
VX_pending_size.v
minor updates
2021-01-12 11:24:36 -08:00
VX_pipe_register.v
fixed pipe register reset issue in synthesis
2021-01-01 14:54:18 -08:00
VX_priority_encoder.v
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_reset_relay.v
minor update
2021-01-06 19:59:04 -08:00
VX_rr_arbiter.v
adding input buffering to bus arbiters to reduce backpressure delay propagation
2020-12-05 17:31:29 -08:00
VX_scope.v
ccip write fix
2021-01-14 22:49:06 -08:00
VX_serial_div.v
reset networks optimization
2020-11-16 01:12:02 -08:00
VX_shift_register.v
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_skid_buffer.v
minor update
2021-01-07 17:25:59 -08:00
VX_sp_ram.v
cache refactoring
2021-01-17 00:18:56 -08:00
VX_stream_arbiter.v
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
VX_stream_demux.v
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00