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minor update

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This commit is contained in:
Blaise Tine
2020-12-26 14:47:41 -08:00
parent 33c431ed44
commit b2b8f190dd
9 changed files with 199 additions and 198 deletions
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5
hw/rtl/VX_config.vh
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@@ -244,11 +244,6 @@
`define LSUQ_SIZE 8
`endif
// Size of MUL Request Queue
`ifndef MULQ_SIZE
`define MULQ_SIZE 8
`endif
// Size of FPU Request Queue
`ifndef FPUQ_SIZE
`define FPUQ_SIZE 8

97
hw/rtl/VX_mul_unit.v
View File

@@ -12,7 +12,6 @@ module VX_mul_unit #(
// Outputs
VX_commit_if mul_commit_if
);
localparam MULQ_BITS = `LOG2UP(`MULQ_SIZE);
wire [`MUL_BITS-1:0] alu_op = mul_req_if.op_type;
wire is_div_op = `IS_DIV_OP(alu_op);
@@ -31,34 +30,13 @@ module VX_mul_unit #(
wire mul_wb_out;
wire mul_valid_out;
wire mul_valid_in = mul_req_if.valid && !is_div_op && ~mulq_full;
wire mul_valid_in = mul_req_if.valid && !is_div_op;
wire mul_ready_in = ready_out || ~mul_valid_out;
wire mulq_push = mul_valid_in && mul_ready_in;
wire mulq_pop = mul_valid_out && ready_out;
wire mulq_full;
wire is_mulh_in = (alu_op != `MUL_MUL);
wire is_mulh_out;
VX_generic_queue #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1),
.SIZE (`MULQ_SIZE),
.FASTRAM (1)
) mul_metadata (
.clk (clk),
.reset (reset),
.push (mulq_push),
.pop (mulq_pop),
.data_in ({mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.rd, mul_req_if.wb, is_mulh_in}),
.data_out ({mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, is_mulh_out}),
.full (mulq_full),
`UNUSED_PIN (empty),
`UNUSED_PIN (size)
);
for (genvar i = 0; i < `NUM_THREADS; i++) begin
for (genvar i = 0; i < `NUM_THREADS; i++) begin
wire [32:0] mul_in1 = {(alu_op != `MUL_MULHU) & alu_in1[i][31], alu_in1[i]};
wire [32:0] mul_in2 = {(alu_op != `MUL_MULHU && alu_op != `MUL_MULHSU) & alu_in2[i][31], alu_in2[i]};
`IGNORE_WARNINGS_BEGIN
@@ -66,31 +44,32 @@ module VX_mul_unit #(
`IGNORE_WARNINGS_END
VX_multiplier #(
.WIDTHA(33),
.WIDTHB(33),
.WIDTHP(66),
.SIGNED(1),
.LATENCY(`LATENCY_IMUL)
.WIDTHA (33),
.WIDTHB (33),
.WIDTHP (66),
.SIGNED (1),
.LATENCY (`LATENCY_IMUL)
) multiplier (
.clk(clk),
.enable(mul_ready_in),
.dataa(mul_in1),
.datab(mul_in2),
.result(mul_result_tmp)
.clk (clk),
.enable (mul_ready_in),
.dataa (mul_in1),
.datab (mul_in2),
.result (mul_result_tmp)
);
assign mul_result[i] = is_mulh_out ? mul_result_tmp[63:32] : mul_result_tmp[31:0];
end
VX_shift_register #(
.DATAW(1),
.DEPTH(`LATENCY_IMUL)
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1),
.DEPTH (`LATENCY_IMUL),
.RESETW (1)
) mul_shift_reg (
.clk(clk),
.reset(reset),
.enable(mul_ready_in),
.data_in(mul_valid_in),
.data_out(mul_valid_out)
.reset (reset),
.enable (mul_ready_in),
.data_in ({mul_valid_in, mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.rd, mul_req_if.wb, is_mulh_in}),
.data_out ({mul_valid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, is_mulh_out})
);
///////////////////////////////////////////////////////////////////////////
@@ -111,26 +90,26 @@ module VX_mul_unit #(
wire is_rem_op_out;
VX_serial_div #(
.WIDTHN(32),
.WIDTHD(32),
.WIDTHQ(32),
.WIDTHR(32),
.LANES(`NUM_THREADS),
.TAGW(`NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1)
.WIDTHN (32),
.WIDTHD (32),
.WIDTHQ (32),
.WIDTHR (32),
.LANES (`NUM_THREADS),
.TAGW (`NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + 1)
) divide (
.clk(clk),
.reset(reset),
.valid_in(div_valid_in),
.ready_in(div_ready_in),
.clk (clk),
.reset (reset),
.valid_in (div_valid_in),
.ready_in (div_ready_in),
.signed_mode(is_signed_div),
.tag_in({mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.rd, mul_req_if.wb, is_rem_op_in}),
.numer(alu_in1),
.denom(alu_in2),
.quotient(div_result_tmp),
.remainder(rem_result_tmp),
.ready_out(div_ready_out),
.valid_out(div_valid_out),
.tag_out({div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, is_rem_op_out})
.tag_in ({mul_req_if.wid, mul_req_if.tmask, mul_req_if.PC, mul_req_if.rd, mul_req_if.wb, is_rem_op_in}),
.numer (alu_in1),
.denom (alu_in2),
.quotient (div_result_tmp),
.remainder (rem_result_tmp),
.ready_out (div_ready_out),
.valid_out (div_valid_out),
.tag_out ({div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, is_rem_op_out})
);
wire [`NUM_THREADS-1:0][31:0] div_result = is_rem_op_out ? rem_result_tmp : div_result_tmp;
@@ -161,6 +140,6 @@ module VX_mul_unit #(
);
// can accept new request?
assign mul_req_if.ready = is_div_op ? div_ready_in : (mul_ready_in && ~mulq_full);
assign mul_req_if.ready = is_div_op ? div_ready_in : mul_ready_in;
endmodule

19
hw/rtl/fp_cores/VX_fp_addmul.v
View File

@@ -168,9 +168,9 @@ module VX_fp_addmul #(
fmul_h = dpi_register();
end
always @(posedge clk) begin
dpi_fadd(fadd_h, enable, dataa[i], datab[i], result_add);
dpi_fsub(fsub_h, enable, dataa[i], datab[i], result_sub);
dpi_fmul(fmul_h, enable, dataa[i], datab[i], result_mul);
dpi_fadd (fadd_h, enable, dataa[i], datab[i], result_add);
dpi_fsub (fsub_h, enable, dataa[i], datab[i], result_sub);
dpi_fmul (fmul_h, enable, dataa[i], datab[i], result_mul);
end
`endif
@@ -178,14 +178,15 @@ module VX_fp_addmul #(
end
VX_shift_register #(
.DATAW(1 + TAGW + 1 + 1),
.DEPTH(`LATENCY_FADDMUL)
.DATAW (1 + TAGW + 1 + 1),
.DEPTH (`LATENCY_FADDMUL),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in({valid_in, tag_in, do_sub, do_mul}),
.data_out({valid_out, tag_out, do_sub_r, do_mul_r})
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in, do_sub, do_mul}),
.data_out ({valid_out, tag_out, do_sub_r, do_mul_r})
);
assign ready_in = enable;

17
hw/rtl/fp_cores/VX_fp_div.v
View File

@@ -44,20 +44,21 @@ module VX_fp_div #(
fdiv_h = dpi_register();
end
always @(posedge clk) begin
dpi_fdiv(fdiv_h, enable, dataa[i], datab[i], result[i]);
dpi_fdiv (fdiv_h, enable, dataa[i], datab[i], result[i]);
end
`endif
end
VX_shift_register #(
.DATAW(1 + TAGW),
.DEPTH(`LATENCY_FDIV)
.DATAW (1 + TAGW),
.DEPTH (`LATENCY_FDIV),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in ({valid_in, tag_in}),
.data_out({valid_out, tag_out})
.clk (clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in}),
.data_out ({valid_out, tag_out})
);
assign ready_in = enable;

19
hw/rtl/fp_cores/VX_fp_ftoi.v
View File

@@ -59,8 +59,8 @@ module VX_fp_ftoi #(
ftou_h = dpi_register();
end
always @(posedge clk) begin
dpi_ftoi(ftoi_h, enable, dataa[i], result_s);
dpi_ftou(ftou_h, enable, dataa[i], result_u);
dpi_ftoi (ftoi_h, enable, dataa[i], result_s);
dpi_ftou (ftou_h, enable, dataa[i], result_u);
end
`endif
@@ -68,14 +68,15 @@ module VX_fp_ftoi #(
end
VX_shift_register #(
.DATAW(1 + TAGW + 1),
.DEPTH(`LATENCY_FTOI)
.DATAW (1 + TAGW + 1),
.DEPTH (`LATENCY_FTOI),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in ({valid_in, tag_in, is_signed}),
.data_out({valid_out, tag_out, is_signed_r})
.clk (clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in, is_signed}),
.data_out ({valid_out, tag_out, is_signed_r})
);
assign ready_in = enable;

19
hw/rtl/fp_cores/VX_fp_itof.v
View File

@@ -59,8 +59,8 @@ module VX_fp_itof #(
utof_h = dpi_register();
end
always @(posedge clk) begin
dpi_itof(itof_h, enable, dataa[i], result_s);
dpi_utof(utof_h, enable, dataa[i], result_u);
dpi_itof (itof_h, enable, dataa[i], result_s);
dpi_utof (utof_h, enable, dataa[i], result_u);
end
`endif
@@ -68,14 +68,15 @@ module VX_fp_itof #(
end
VX_shift_register #(
.DATAW(1 + TAGW + 1),
.DEPTH(`LATENCY_ITOF)
.DATAW (1 + TAGW + 1),
.DEPTH (`LATENCY_ITOF),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in ({valid_in, tag_in, is_signed}),
.data_out({valid_out, tag_out, is_signed_r})
.clk (clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in, is_signed}),
.data_out ({valid_out, tag_out, is_signed_r})
);
assign ready_in = enable;

17
hw/rtl/fp_cores/VX_fp_madd.v
View File

@@ -127,8 +127,8 @@ module VX_fp_madd #(
fmsub_h = dpi_register();
end
always @(posedge clk) begin
dpi_fmadd(fmadd_h, enable, dataa[i], datab[i], datac[i], result_madd);
dpi_fmsub(fmsub_h, enable, dataa[i], datab[i], datac[i], result_msub);
dpi_fmadd (fmadd_h, enable, dataa[i], datab[i], datac[i], result_madd);
dpi_fmsub (fmsub_h, enable, dataa[i], datab[i], datac[i], result_msub);
end
`endif
@@ -138,14 +138,15 @@ module VX_fp_madd #(
end
VX_shift_register #(
.DATAW(1 + TAGW + 1 + 1),
.DEPTH(`LATENCY_FMADD)
.DATAW (1 + TAGW + 1 + 1),
.DEPTH (`LATENCY_FMADD),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in({valid_in, tag_in, do_sub, do_neg}),
.data_out({valid_out, tag_out, do_sub_r, do_neg_r})
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in, do_sub, do_neg}),
.data_out ({valid_out, tag_out, do_sub_r, do_neg_r})
);
assign ready_in = enable;

17
hw/rtl/fp_cores/VX_fp_sqrt.v
View File

@@ -42,20 +42,21 @@ module VX_fp_sqrt #(
fsqrt_h = dpi_register();
end
always @(posedge clk) begin
dpi_fsqrt(fsqrt_h, enable, dataa[i], result[i]);
dpi_fsqrt (fsqrt_h, enable, dataa[i], result[i]);
end
`endif
end
VX_shift_register #(
.DATAW(1 + TAGW),
.DEPTH(`LATENCY_FSQRT)
.DATAW (1 + TAGW),
.DEPTH (`LATENCY_FSQRT),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset(reset),
.enable(enable),
.data_in ({valid_in, tag_in}),
.data_out({valid_out, tag_out})
.clk (clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in}),
.data_out ({valid_out, tag_out})
);
assign ready_in = enable;

187
hw/rtl/libs/VX_shift_register.v
View File

@@ -1,81 +1,16 @@
`include "VX_platform.vh"
module VX_shift_register #(
parameter DATAW = 1,
parameter RESETW = DATAW,
parameter DEPTH = 1
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
);
if (RESETW != 0) begin
if (RESETW == DATAW) begin
VX_shift_register_wr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in),
.data_out (data_out)
);
end else begin
VX_shift_register_wr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr_wr (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in[DATAW-1:DATAW-RESETW]),
.data_out (data_out[DATAW-1:DATAW-RESETW])
);
VX_shift_register_nr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr_nr (
.clk (clk),
.enable (enable),
.data_in (data_in[DATAW-RESETW-1:0]),
.data_out (data_out[DATAW-RESETW-1:0])
);
end
end else begin
`UNUSED_VAR (reset)
VX_shift_register_nr #(
.DATAW (DATAW),
.DEPTH (DEPTH)
) sr (
.clk (clk),
.enable (enable),
.data_in (data_in),
.data_out (data_out)
);
end
endmodule
module VX_shift_register_nr #(
parameter DATAW = 1,
parameter DEPTH = 1
parameter DEPTH = 1,
parameter NTAPS = 1,
parameter DEPTHW = $clog2(DEPTH),
parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}}
) (
input wire clk,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
input wire clk,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out
);
reg [DATAW-1:0] entries [DEPTH-1:0];
@@ -87,19 +22,24 @@ module VX_shift_register_nr #(
end
end
assign data_out = entries [DEPTH-1];
for (genvar i = 0; i < NTAPS; ++i) begin
assign data_out [i*DATAW+:DATAW] = entries [ TAPS[i*DEPTHW+:DEPTHW] ];
end
endmodule
module VX_shift_register_wr #(
parameter DATAW = 1,
parameter DEPTH = 1
parameter DATAW = 1,
parameter DEPTH = 1,
parameter NTAPS = 1,
parameter DEPTHW = $clog2(DEPTH),
parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}}
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out
);
reg [DEPTH-1:0][DATAW-1:0] entries;
@@ -126,8 +66,89 @@ module VX_shift_register_wr #(
end
end
end
end
for (genvar i = 0; i < NTAPS; ++i) begin
assign data_out [i*DATAW+:DATAW] = entries [ TAPS[i*DEPTHW+:DEPTHW] ];
end
endmodule
module VX_shift_register #(
parameter DATAW = 1,
parameter RESETW = DATAW,
parameter DEPTH = 1,
parameter NTAPS = 1,
parameter DEPTHW = $clog2(DEPTH),
parameter [(DEPTHW*NTAPS)-1:0] TAPS = {NTAPS{DEPTHW'(DEPTH-1)}}
) (
input wire clk,
input wire reset,
input wire enable,
input wire [DATAW-1:0] data_in,
output wire [(NTAPS*DATAW)-1:0] data_out
);
if (RESETW != 0) begin
if (RESETW == DATAW) begin
VX_shift_register_wr #(
.DATAW (DATAW),
.DEPTH (DEPTH),
.NTAPS (NTAPS),
.TAPS (TAPS)
) sr (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in),
.data_out (data_out)
);
end else begin
VX_shift_register_wr #(
.DATAW (RESETW),
.DEPTH (DEPTH),
.NTAPS (NTAPS),
.TAPS (TAPS)
) sr_wr (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (data_in[DATAW-1:DATAW-RESETW]),
.data_out (data_out[DATAW-1:DATAW-RESETW])
);
VX_shift_register_nr #(
.DATAW (DATAW-RESETW),
.DEPTH (DEPTH),
.NTAPS (NTAPS),
.TAPS (TAPS)
) sr_nr (
.clk (clk),
.enable (enable),
.data_in (data_in[DATAW-RESETW-1:0]),
.data_out (data_out[DATAW-RESETW-1:0])
);
end
end else begin
`UNUSED_VAR (reset)
VX_shift_register_nr #(
.DATAW (DATAW),
.DEPTH (DEPTH),
.NTAPS (NTAPS),
.TAPS (TAPS)
) sr (
.clk (clk),
.enable (enable),
.data_in (data_in),
.data_out (data_out)
);
end
assign data_out = entries [DEPTH-1];
endmodule