Commit Graph

91 Commits

Author SHA1 Message Date
felsabbagh3
6340ffcc2a new cache states 2019-10-23 15:07:14 -04:00
felsabbagh3
1645a04b1d Fixed SM + added def SYN 2019-10-22 15:56:30 -04:00
felsabbagh3
9d8273afe4 Finished Cache Integration 2019-10-22 06:02:08 -04:00
felsabbagh3
b7af8c3f34 Integrated Shared Memory 2019-10-22 05:03:47 -04:00
felsabbagh3
1bfafca896 Cleanup before integration 2019-10-22 03:03:17 -04:00
felsabbagh3
b3f464dd89 Barriers impl + tested 2019-10-22 01:47:39 -04:00
felsabbagh3
31d3d51392 WSPAWN imp + tested 2019-10-21 23:35:53 -04:00
felsabbagh3
c21e400f9f Readded IPDOM stack + SPLIT/Join tested 2019-10-21 21:26:21 -04:00
felsabbagh3
b6375e76de Readded IPDOM stack + SPLIT/Join tested 2019-10-21 21:24:49 -04:00
Lingjun Zhu
e2cd8102eb Uncommented the necessary line about write_bit_mask on VX_gpr.v again, try synthesizing 2019-10-21 17:09:51 -04:00
felsabbagh3
0672389edc fix 2019-10-21 12:16:17 -04:00
felsabbagh3
ce49e2f223 proper init warp scheduelr 2019-10-21 12:13:34 -04:00
felsabbagh3
8050419511 added begin 2019-10-21 12:06:10 -04:00
felsabbagh3
85004899bd added reset to ws 2019-10-21 12:03:07 -04:00
felsabbagh3
99586279d9 always fix stack 2019-10-21 11:49:10 -04:00
felsabbagh3
292c792339 generic stack reset 2019-10-21 11:45:51 -04:00
felsabbagh3
4bfdbb5188 reset posedge 2019-10-21 11:34:12 -04:00
felsabbagh3
49b139d512 fix 2019-10-21 11:24:45 -04:00
felsabbagh3
121a985d12 Reset to Generic Register 2019-10-21 11:21:13 -04:00
felsabbagh3
bab1852a99 Added Split/Join - not tested 2019-10-21 03:03:15 -04:00
felsabbagh3
84f5ccb484 Added CSR TID/WID reads 2019-10-21 02:10:05 -04:00
felsabbagh3
797801ebae CENA/CENB Modifications + Still not working 2019-10-19 14:52:57 -04:00
felsabbagh3
4cae140ac1 Mem technology compiling but still reading all zeros 2019-10-18 16:45:42 -04:00
felsabbagh3
f7d826593f TMC working and tested 2019-10-18 16:09:06 -04:00
felsabbagh3
f7b55427b4 Added ISA2 infrastructure with bugs 2019-10-18 05:21:32 -04:00
felsabbagh3
629ed3f8f9 Before ISA2.0 2019-10-18 04:15:34 -04:00
felsabbagh3
559c64cb36 Cleanup 2019-10-18 02:20:38 -04:00
felsabbagh3
505bbc20c8 Removed FWD 2019-10-18 02:01:39 -04:00
felsabbagh3
6b729fd2ea minor 2019-10-18 01:46:38 -04:00
felsabbagh3
ccbb2acab5 LSU+EXU minor 2019-10-17 22:38:09 -04:00
felsabbagh3
6779d0fade Instruction Multiplex LSU/EXU 1 cycle DONE 2019-10-17 22:29:21 -04:00
Lingjun Zhu
a4d6ada16d Fixed the issues of memory during synthesis 2019-10-17 14:18:52 -04:00
felsabbagh3
9bf186fc77 minor 2019-10-17 11:51:11 -04:00
felsabbagh3
e8a43fa7a9 minor 2019-10-17 11:44:19 -04:00
felsabbagh3
10fbb53c38 minor 2019-10-17 11:29:40 -04:00
felsabbagh3
33e20a2d80 minor 2019-10-17 11:25:29 -04:00
felsabbagh3
b08297eafb minor 2019-10-17 11:04:06 -04:00
felsabbagh3
7fd5312b67 minor 2019-10-17 10:50:36 -04:00
felsabbagh3
95047fcadc Rename Stage that removes the need for forwarding 2019-10-17 00:48:54 -04:00
felsabbagh3
8bc3b8b0a5 Need to link SystemC for sc_time_stamp() 2019-10-14 23:25:14 -04:00
felsabbagh3
22f02820cf GPR back-end with mem 2019-10-14 19:10:47 -04:00
felsabbagh3
ee83e6d8c8 Moved GPR to back-end 2019-10-14 19:08:32 -04:00
Lingjun Zhu
f28cd286e6 Implemented the GPR model with the CLN28HPC memory block 2019-10-13 20:27:28 -04:00
Lingjun Zhu
d5dad1c442 Updated the two-port GPR model 2019-10-13 19:52:14 -04:00
felsabbagh3
e67310acfb New Warp Scheduler + VCD Enable 2019-09-15 00:12:41 -04:00
felsabbagh3
fb3bc60189 Finalized GPR with 3-Port Structure 2019-09-11 14:53:32 -04:00
felsabbagh3
1b25b10644 Full Evaluation Attempt 1 2019-09-11 01:39:00 -04:00
felsabbagh3
3c3a443bd5 New RF with Evaluation 2019-09-11 01:04:23 -04:00
felsabbagh3
8d143d7739 Quartus + GPR evaluation 2019-09-10 20:23:01 -04:00
felsabbagh3
4e8da1811a New GPR structure - Clone or WSPAWN 2019-09-09 22:17:20 -04:00