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Fixed the issues of memory during synthesis

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Lingjun Zhu
2019-10-17 14:18:52 -04:00
parent 6cfb44396e
commit a4d6ada16d
2 changed files with 2 additions and 2 deletions
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2
rtl/VX_gpr.v
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@@ -48,7 +48,7 @@ module VX_gpr (
// .q1 (out_b_reg_data)
// );
// wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 first_ram (
.CENYA(),