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Need to link SystemC for sc_time_stamp()

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This commit is contained in:
felsabbagh3
2019-10-14 23:25:14 -04:00
parent 22f02820cf
commit 8bc3b8b0a5
22 changed files with 958 additions and 372 deletions
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6
rtl/Makefile
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@@ -1,13 +1,13 @@
all: RUNFILE
# -LDFLAGS '-lsystemc'
VERILATOR:
echo "#define VCD_OFF" > tb_debug.h
verilator --compiler gcc -Wall -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS -std=c++11 -O3
verilator --compiler gcc -Wno-fatal -Wno-UNOPTFLAT -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-lint -cc Vortex.v -I. -I../models/memory/cln28hpc/rf2_32x128_wm1/ -I/usr/local/systemc/ -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS '-std=c++11 -O3' -LDFLAGS '-L/usr/local/systemc/'
compdebug:
echo "#define VCD_OUTPUT" > tb_debug.h
verilator --compiler gcc --prof-cfuncs -DVL_DEBUG=1 --coverage -Wall --trace -cc Vortex.v -I. -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS '-std=c++11 -DVL_DEBUG'
verilator --compiler gcc -Wno-fatal -Wno-UNOPTFLAT -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-lint --prof-cfuncs -DVL_DEBUG=1 --coverage --trace -cc Vortex.v -I/usr/local/systemc/ -I. -I../models/memory/cln28hpc/rf2_32x128_wm1/ -Iinterfaces/ -Ipipe_regs/ --exe test_bench.cpp -CFLAGS '-std=c++11 -DVL_DEBUG' -LDFLAGS '-L/usr/local/systemc/'
RUNFILE: VERILATOR
(cd obj_dir && make -j -f VVortex.mk)

4
rtl/VX_decode.v
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@@ -33,9 +33,7 @@ module VX_decode(
assign VX_frE_to_bckE_req.curr_PC = in_curr_PC;
wire in_valid[`NT_M1:0];
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) assign in_valid[index] = fd_inst_meta_de.valid[index];
wire[`NT_M1:0] in_valid = fd_inst_meta_de.valid;
wire[6:0] curr_opcode;

11
rtl/VX_gpr.v
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@@ -55,7 +55,11 @@ module VX_gpr (
// .q1 (out_b_reg_data)
// );
wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
// Port A is a read port, Port B is a write port
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 first_ram (
.CENYA(),
.AYA(),
@@ -70,7 +74,7 @@ module VX_gpr (
.AA(VX_gpr_read.rs1),
.CLKB(clk),
.CENB(1'b0),
.WENB({32{~(VX_writeback_inter.wb_valid[3])}, 32{~(VX_writeback_inter.wb_valid[2])}, 32{~(VX_writeback_inter.wb_valid[1])}, 32{~(VX_writeback_inter.wb_valid[0])}}),
.WENB(write_bit_mask),
.AB(VX_writeback_inter.rd),
.DB(VX_writeback_inter.write_data),
.EMAA(3'b011),
@@ -92,7 +96,9 @@ module VX_gpr (
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 second_ram (
.CENYA(),
.AYA(),
@@ -107,7 +113,7 @@ module VX_gpr (
.AA(VX_gpr_read.rs2),
.CLKB(clk),
.CENB(1'b0),
.WENB({32{~(VX_writeback_inter.wb_valid[3])}, 32{~(VX_writeback_inter.wb_valid[2])}, 32{~(VX_writeback_inter.wb_valid[1])}, 32{~(VX_writeback_inter.wb_valid[0])}}),
.WENB(write_bit_mask),
.AB(VX_writeback_inter.rd),
.DB(VX_writeback_inter.write_data),
.EMAA(3'b011),
@@ -129,6 +135,7 @@ module VX_gpr (
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
// >>>>>>> 5680b997b599ce2900997cab976681fe3881e880

6
rtl/VX_gpr_stage.v
View File

@@ -26,8 +26,10 @@ module VX_gpr_stage (
);
// wire[31:0] curr_PC = VX_bckE_req.curr_PC;
// wire[2:0] branchType = VX_bckE_req.branch_type;
wire[31:0] curr_PC = VX_bckE_req.curr_PC;
wire[2:0] branchType = VX_bckE_req.branch_type;
wire jalQual = VX_bckE_req.jalQual;
assign VX_fwd_req_de.src1 = VX_bckE_req.rs1;

6
rtl/byte_enabled_simple_dual_port_ram.v
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@@ -5,10 +5,10 @@
module byte_enabled_simple_dual_port_ram
(
input we, clk,
input wire[4:0] waddr, raddr1,
input wire[4:0] waddr, raddr1, raddr2,
input wire[`NT_M1:0] be,
input wire[`NT_M1:0][31:0] wdata,
output reg[`NT_M1:0][31:0] q1
output reg[`NT_M1:0][31:0] q1, q2
);
// integer regi;
@@ -42,7 +42,7 @@ module byte_enabled_simple_dual_port_ram
end
assign q1 = GPR[raddr1];
assign q2 = GPR[raddr2];
// assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1];
// assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2];

8
rtl/results.txt
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@@ -1,7 +1,7 @@
# Dynamic Instructions: 58157
# of total cycles: 58172
# Dynamic Instructions: 13
# of total cycles: 24
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.00026
# time to simulate: 2.18459e-314 milliseconds
# CPI: 1.84615
# time to simulate: 6.95312e-310 milliseconds
# GRADE: Failed on test: 4294967295

2
rtl/tb_debug.h
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@@ -1 +1 @@
#define VCD_OFF
#define VCD_OUTPUT

2
rtl/test_bench.h
View File

@@ -376,7 +376,7 @@ bool Vortex::simulate(std::string file_to_simulate)
// while (this->stats_total_cycles < 10)
{
// std::cout << "Counter: " << counter << "\n";
// std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
// dstop = !dbus_driver();
vortex->clk = 1;