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Fixed SM + added def SYN

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This commit is contained in:
felsabbagh3
2019-10-22 15:56:30 -04:00
parent 3cb5820ecd
commit 1645a04b1d
13 changed files with 2388 additions and 2364 deletions
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4
rtl/Makefile
View File

@@ -13,7 +13,7 @@ COMP=--compiler gcc
WNO=-Wno-UNOPTFLAT -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED
LIGHTW=-Wno-UNOPTFLAT --Wno-PINMISSING -Wno-WIDTH -Wno-STMTDLY
LIGHTW=-Wno-UNOPTFLAT
# LIB=-LDFLAGS '-L/usr/local/systemc/'
LIB=
@@ -27,7 +27,7 @@ MAKECPP=(cd obj_dir && make -j -f VVortex.mk)
# -LDFLAGS '-lsystemc'
VERILATOR:
echo "#define VCD_OFF" > simulate/tb_debug.h
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF)
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW)
VERILATORnoWarnings:
echo "#define VCD_OFF" > simulate/tb_debug.h

1
rtl/VX_define.v
View File

@@ -9,6 +9,7 @@
// Uncomment the below line if NW=1
// `define ONLY
// `define SYN 1
`define NUMBER_BANKS 8

210
rtl/VX_gpr.v
View File

@@ -11,116 +11,122 @@ module VX_gpr (
output reg[`NT_M1:0][31:0] out_b_reg_data
);
wire write_enable;
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs1),
.raddr2(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data),
.q1 (out_a_reg_data),
.q2 (out_b_reg_data)
);
`ifndef SYN
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs1),
.raddr2(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data),
.q1 (out_a_reg_data),
.q2 (out_b_reg_data)
);
`else
wire[`NT_M1:0][31:0] write_bit_mask;
genvar curr_t;
for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin
wire local_write = write_enable & VX_writeback_inter.wb_valid[curr_t];
assign write_bit_mask[curr_t] = {32{~local_write}};
end
wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid);
// wire[`NT_M1:0][31:0] write_bit_mask;
wire cenb = !going_to_write;
// genvar curr_t;
// for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin
// wire local_write = write_enable & VX_writeback_inter.wb_valid[curr_t];
// assign write_bit_mask[curr_t] = {32{~local_write}};
// end
wire cena_1 = (VX_gpr_read.rs1 == 0);
wire cena_2 = (VX_gpr_read.rs2 == 0);
// wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid);
// wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 first_ram (
.CENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(out_a_reg_data),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena_1),
.AA(VX_gpr_read.rs1),
.CLKB(clk),
.CENB(cenb),
.WENB(write_bit_mask),
.AB(VX_writeback_inter.rd),
.DB(VX_writeback_inter.write_data),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(5'b0),
.TENB(1'b1),
.TCENB(1'b0),
.TWENB(128'b0),
.TAB(5'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
// wire cenb = !going_to_write;
// wire cena_1 = (VX_gpr_read.rs1 == 0);
// wire cena_2 = (VX_gpr_read.rs2 == 0);
// // wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
// /* verilator lint_off PINCONNECTEMPTY */
// rf2_32x128_wm1 first_ram (
// .CENYA(),
// .AYA(),
// .CENYB(),
// .WENYB(),
// .AYB(),
// .QA(out_a_reg_data),
// .SOA(),
// .SOB(),
// .CLKA(clk),
// .CENA(cena_1),
// .AA(VX_gpr_read.rs1),
// .CLKB(clk),
// .CENB(cenb),
// .WENB(write_bit_mask),
// .AB(VX_writeback_inter.rd),
// .DB(VX_writeback_inter.write_data),
// .EMAA(3'b011),
// .EMASA(1'b0),
// .EMAB(3'b011),
// .TENA(1'b1),
// .TCENA(1'b0),
// .TAA(5'b0),
// .TENB(1'b1),
// .TCENB(1'b0),
// .TWENB(128'b0),
// .TAB(5'b0),
// .TDB(128'b0),
// .RET1N(1'b1),
// .SIA(2'b0),
// .SEA(1'b0),
// .DFTRAMBYP(1'b0),
// .SIB(2'b0),
// .SEB(1'b0),
// .COLLDISN(1'b1)
// );
// /* verilator lint_on PINCONNECTEMPTY */
// /* verilator lint_off PINCONNECTEMPTY */
// rf2_32x128_wm1 second_ram (
// .CENYA(),
// .AYA(),
// .CENYB(),
// .WENYB(),
// .AYB(),
// .QA(out_b_reg_data),
// .SOA(),
// .SOB(),
// .CLKA(clk),
// .CENA(cena_2),
// .AA(VX_gpr_read.rs2),
// .CLKB(clk),
// .CENB(cenb),
// .WENB(write_bit_mask),
// .AB(VX_writeback_inter.rd),
// .DB(VX_writeback_inter.write_data),
// .EMAA(3'b011),
// .EMASA(1'b0),
// .EMAB(3'b011),
// .TENA(1'b1),
// .TCENA(1'b0),
// .TAA(5'b0),
// .TENB(1'b1),
// .TCENB(1'b0),
// .TWENB(128'b0),
// .TAB(5'b0),
// .TDB(128'b0),
// .RET1N(1'b1),
// .SIA(2'b0),
// .SEA(1'b0),
// .DFTRAMBYP(1'b0),
// .SIB(2'b0),
// .SEB(1'b0),
// .COLLDISN(1'b1)
// );
// /* verilator lint_on PINCONNECTEMPTY */
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 second_ram (
.CENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(out_b_reg_data),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena_2),
.AA(VX_gpr_read.rs2),
.CLKB(clk),
.CENB(cenb),
.WENB(write_bit_mask),
.AB(VX_writeback_inter.rd),
.DB(VX_writeback_inter.write_data),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(5'b0),
.TENB(1'b1),
.TCENB(1'b0),
.TWENB(128'b0),
.TAB(5'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
`endif
endmodule

2
rtl/VX_gpr_stage.v
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@@ -82,7 +82,7 @@ module VX_gpr_stage (
wire flush_rest = schedule_delay;
wire stall_lsu = is_lsu && memory_delay;
wire stall_lsu = memory_delay;
wire flush_lsu = schedule_delay && !stall_lsu;

268
rtl/cache/VX_cache_data.v vendored
View File

@@ -27,167 +27,169 @@ module VX_cache_data (
wire currently_writing = (|we);
wire update_dirty = ((!dirty_use) && currently_writing) || (evict);
/////////////////
// (3:0) 4 bytes
reg[`NUM_WORDS_PER_BLOCK-1:0][31:0] data[NUMBER_INDEXES-1:0]; // Actual Data
reg[16:0] tag[NUMBER_INDEXES-1:0];
reg valid[NUMBER_INDEXES-1:0];
reg dirty[NUMBER_INDEXES-1:0];
// 16 bytes
assign data_use = data[addr]; // Read Port
assign tag_use = tag[addr];
assign valid_use = valid[addr];
assign dirty_use = dirty[addr];
wire dirt_new = evict ? 0 : (|we);
integer f;
always @(posedge clk) begin : dirty_update
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
end
always @(posedge clk) begin : data_update
for (f = 0; f < `NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f]) data[addr][f] <= data_write[f];
end
end
`ifndef SYN
always @(posedge clk) begin : tag_update
if (evict) tag[addr] <= tag_write;
end
always @(posedge clk) begin : valid_update
if (evict) valid[addr] <= 1;
end
// (3:0) 4 bytes
reg[`NUM_WORDS_PER_BLOCK-1:0][31:0] data[NUMBER_INDEXES-1:0]; // Actual Data
reg[16:0] tag[NUMBER_INDEXES-1:0];
reg valid[NUMBER_INDEXES-1:0];
reg dirty[NUMBER_INDEXES-1:0];
//////////////////////////////
// 16 bytes
assign data_use = data[addr]; // Read Port
assign tag_use = tag[addr];
assign valid_use = valid[addr];
assign dirty_use = dirty[addr];
// wire cena = 1;
integer f;
always @(posedge clk) begin : dirty_update
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
end
// wire cenb_d = (|we);
// wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write;
// wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d;
// wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d;
// genvar cur_b;
// for (cur_b = 0; cur_b < `NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin
// assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}};
// end
// assign data_use = data_out_d;
always @(posedge clk) begin : data_update
for (f = 0; f < `NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f]) data[addr][f] <= data_write[f];
end
end
always @(posedge clk) begin : tag_update
if (evict) tag[addr] <= tag_write;
end
always @(posedge clk) begin : valid_update
if (evict) valid[addr] <= 1;
end
`else
// // Using ASIC MEM
// /* verilator lint_off PINCONNECTEMPTY */
// rf2_256x128_wm1 data (
// .CENYA(),
// .AYA(),
// .CENYB(),
// .WENYB(),
// .AYB(),
// .QA(data_out_d),
// .SOA(),
// .SOB(),
// .CLKA(clk),
// .CENA(cena),
// .AA(addr),
// .CLKB(clk),
// .CENB(cenb_d),
// .WENB(write_bit_mask_d),
// .AB(addr),
// .DB(wdata_d),
// .EMAA(3'b011),
// .EMASA(1'b0),
// .EMAB(3'b011),
// .TENA(1'b1),
// .TCENA(1'b0),
// .TAA(5'b0),
// .TENB(1'b1),
// .TCENB(1'b0),
// .TWENB(128'b0),
// .TAB(5'b0),
// .TDB(128'b0),
// .RET1N(1'b1),
// .SIA(2'b0),
// .SEA(1'b0),
// .DFTRAMBYP(1'b0),
// .SIB(2'b0),
// .SEB(1'b0),
// .COLLDISN(1'b1)
// );
// /* verilator lint_on PINCONNECTEMPTY */
wire cena = 1;
wire cenb_d = (|we);
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_d = data_write;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] write_bit_mask_d;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_d;
genvar cur_b;
for (cur_b = 0; cur_b < `NUM_WORDS_PER_BLOCK; cur_b=cur_b+1) begin
assign write_bit_mask_d[cur_b] = {32{~we[cur_b]}};
end
assign data_use = data_out_d;
// Using ASIC MEM
/* verilator lint_off PINCONNECTEMPTY */
rf2_256x128_wm1 data (
.CENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(data_out_d),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(addr),
.CLKB(clk),
.CENB(cenb_d),
.WENB(write_bit_mask_d),
.AB(addr),
.DB(wdata_d),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(5'b0),
.TENB(1'b1),
.TCENB(1'b0),
.TWENB(128'b0),
.TAB(5'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
// wire[16:0] old_tag;
// wire old_valid;
// wire old_dirty;
wire[16:0] old_tag;
wire old_valid;
wire old_dirty;
// wire[16:0] new_tag = evict ? tag_write : old_tag;
// wire new_valid = evict ? 1 : old_valid;
// wire new_dirty = update_dirty ? new_dirty : old_dirty;
wire[16:0] new_tag = evict ? tag_write : old_tag;
wire new_valid = evict ? 1 : old_valid;
wire new_dirty = update_dirty ? dirt_new : old_dirty;
// wire cenb_m = (evict || update_dirty);
// wire[19-1:0][31:0] write_bit_mask_m = cenb_m ? 19'b0 : 19'b1;
wire cenb_m = (evict || update_dirty);
wire[19-1:0][31:0] write_bit_mask_m = cenb_m ? 19'b0 : 19'b1;
// wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid};
// wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m;
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] wdata_m = {new_tag, new_dirty, new_valid};
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_out_m;
// assign {old_tag, old_dirty, old_valid} = data_out_m;
assign {old_tag, old_dirty, old_valid} = data_out_m;
// assign dirty_use = old_dirty;
// assign valid_use = old_valid;
// assign tag_use = old_tag;
assign dirty_use = old_dirty;
assign valid_use = old_valid;
assign tag_use = old_tag;
// /* verilator lint_off PINCONNECTEMPTY */
// rf2_256x19_wm0 meta (
// .CENYA(),
// .AYA(),
// .CENYB(),
// // .WENYB(),
// .AYB(),
// .QA(data_out_m),
// .SOA(),
// .SOB(),
// .CLKA(clk),
// .CENA(cena),
// .AA(addr),
// .CLKB(clk),
// .CENB(cenb_m),
// // .WENB(write_bit_mask_m),
// .AB(addr),
// .DB(wdata_m),
// .EMAA(3'b011),
// .EMASA(1'b0),
// .EMAB(3'b011),
// .TENA(1'b1),
// .TCENA(1'b0),
// .TAA(5'b0),
// .TENB(1'b1),
// .TCENB(1'b0),
// // .TWENB(128'b0),
// .TAB(5'b0),
// .TDB(128'b0),
// .RET1N(1'b1),
// .SIA(2'b0),
// .SEA(1'b0),
// .DFTRAMBYP(1'b0),
// .SIB(2'b0),
// .SEB(1'b0),
// .COLLDISN(1'b1)
// );
// /* verilator lint_on PINCONNECTEMPTY */
/* verilator lint_off PINCONNECTEMPTY */
rf2_256x19_wm0 meta (
.CENYA(),
.AYA(),
.CENYB(),
// .WENYB(),
.AYB(),
.QA(data_out_m),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(addr),
.CLKB(clk),
.CENB(cenb_m),
// .WENB(write_bit_mask_m),
.AB(addr),
.DB(wdata_m),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(5'b0),
.TENB(1'b1),
.TCENB(1'b0),
// .TWENB(128'b0),
.TAB(5'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
`endif
endmodule

7
rtl/results.txt
View File

@@ -1,7 +0,0 @@
# Dynamic Instructions: 14
# of total cycles: 26
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.85714
# time to simulate: 6.95313e-310 milliseconds
# GRADE: Failed on test: 4294967295

123
rtl/shared_memory/VX_priority_encoder_sm.v
View File

@@ -16,73 +16,84 @@ module VX_priority_encoder_sm
// To SM Module
output reg[NB:0] out_valid,
output reg[NB:0][31:0] out_address,
output reg[NB:0][31:0] out_data,
output reg[NB:0][31:0] out_data,
// To Processor
output wire[NB:0][1:0] req_num,
output reg stall,
output wire send_data // Finished all of the requests
output wire send_data // Finished all of the requests
);
wire[NB:0][`NT_M1:0] bank_valids;
wire[NB:0][`NT_M1:0] temp_bank_valids;
reg[NB:0][`NT_M1:0] temp_valid; // State - If there's any ones here, then stall
wire[NB:0] temp_stall;
integer counter[NB:0] ;
wire[NB:0][`NT_M1:0] mask;
wire[NB:0] update_temp_valid;
reg[NB:0] req_done;
reg[`NT_M1:0] left_requests;
VX_bank_valids #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_bank_valid(
.in_valids(in_valid),
.in_addr(in_address),
.bank_valids(bank_valids)
);
genvar j;
for(j=0; j <= NB; j++) begin
assign temp_stall[j] = ($countones(temp_valid[j]) != 0);
assign temp_bank_valids[j] = (temp_stall[j] || req_done[j]) ? temp_valid[j] : bank_valids[j];
assign update_temp_valid[j] = !req_done[j] && ($countones(bank_valids[j]) > 1);
VX_generic_priority_encoder #(.N(4)) vx_priority_encoder(
.valids(temp_bank_valids[j]),
.index(req_num[j]),
.found(out_valid[j])
);
VX_set_bit vx_set_bit(
.index(req_num[j]),
.mask (mask[j])
);
assign out_address[j] = out_valid[j] ? in_address[req_num[j]] : 0;
assign out_data[j] = out_valid[j] ? in_data[req_num[j]] : 0;
end
wire[`NT_M1:0] use_valid;
assign stall = |temp_stall;
assign send_data = &req_done;
wire requests_left = (|left_requests);
genvar i;
always @(posedge clk) begin
for(i = 0; i <= NB; i = i+1) begin
if (update_temp_valid[i]) begin
counter[i] <= counter[i] + 1;
if(counter[i] == 0) temp_valid[i] <= bank_valids[i] & mask[i];
else if (counter[i] > 0) temp_valid[i] <= temp_bank_valids[i] & mask[i];
end
if(($countones(in_valid) > 0) && ($countones(bank_valids[i]) == 0)) begin
req_done[i] <= 1;
end
else if((counter[i][2:0] == ($countones(bank_valids[i])-1))) begin
req_done[i] <= 1;
counter[i] <= 0;
end
else begin
req_done[i] <= 0;
assign use_valid = (requests_left) ? left_requests : in_valid;
wire[NB:0][`NT_M1:0] bank_valids;
VX_bank_valids #(.NB(NB), .BITS_PER_BANK(BITS_PER_BANK)) vx_bank_valid(
.in_valids(use_valid),
.in_addr(in_address),
.bank_valids(bank_valids)
);
wire[NB:0] more_than_one_valid;
genvar curr_bank;
for (curr_bank = 0; curr_bank <= NB; curr_bank = curr_bank + 1)
begin
assign more_than_one_valid[curr_bank] = $countones(bank_valids[curr_bank]) > 1;
end
assign stall = (|more_than_one_valid);
assign send_data = (!stall) && (|in_valid); // change
wire[NB:0][1:0] internal_req_num;
wire[NB:0] internal_out_valid;
// There's one or less valid per bank
genvar curr_bank_o;
for (curr_bank_o = 0; curr_bank_o <= NB; curr_bank_o = curr_bank_o + 1)
begin
VX_generic_priority_encoder #(.N(4)) vx_priority_encoder(
.valids(bank_valids[curr_bank_o]),
.index(internal_req_num[curr_bank_o]),
.found(internal_out_valid[curr_bank_o])
);
assign out_address[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_address[internal_req_num[curr_bank_o]] : 0;
assign out_data[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_data[internal_req_num[curr_bank_o]] : 0;
end
reg[`NT_M1:0] serviced;
genvar curr_b;
always @(*) begin
serviced = 0;
for (curr_b = 0; curr_b <= NB; curr_b=curr_b+1) begin
serviced[internal_req_num[curr_b]] = 1;
end
end
end
assign req_num = internal_req_num;
assign out_valid = internal_out_valid;
wire[`NT_M1:0] serviced_qual = in_valid & (serviced);
wire[`NT_M1:0] new_left_requests = (left_requests == 0) ? (in_valid & ~serviced_qual) : (left_requests & ~ serviced_qual);
// wire[`NT_M1:0] new_left_requests = left_requests & ~(serviced_qual);
always @(posedge clk) begin
if (!stall) left_requests <= 0;
else left_requests <= new_left_requests;
end
endmodule

127
rtl/shared_memory/VX_shared_memory_block.v
View File

@@ -9,73 +9,78 @@ module VX_shared_memory_block (
);
logic [3:0][31:0] shared_memory[127:0];
//wire need_to_write = (|we);
`ifndef SYN
always @(posedge clk) begin
if(shm_write) begin
if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
logic [3:0][31:0] shared_memory[127:0];
//wire need_to_write = (|we);
always @(posedge clk) begin
if(shm_write) begin
if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
if (we == 2'b11) shared_memory[addr][3][31:0] <= wdata[3][31:0];
end
end
end
assign data_out = shm_write ? 0 : shared_memory[addr];
assign data_out = shm_write ? 0 : shared_memory[addr];
`else
wire cena = 1;
wire cenb = shm_write;
wire[3:0][31:0] write_bit_mask;
assign write_bit_mask[0] = (we == 2'b00) ? 1 : {32{1'b0}};
assign write_bit_mask[1] = (we == 2'b01) ? 1 : {32{1'b0}};
assign write_bit_mask[2] = (we == 2'b10) ? 1 : {32{1'b0}};
assign write_bit_mask[3] = (we == 2'b11) ? 1 : {32{1'b0}};
// Using ASIC MEM
/* verilator lint_off PINCONNECTEMPTY */
rf2_128x128_wm1 first_ram (
.CENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(data_out),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(addr),
.CLKB(clk),
.CENB(cenb),
.WENB(write_bit_mask),
.AB(addr),
.DB(wdata),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(5'b0),
.TENB(1'b1),
.TCENB(1'b0),
.TWENB(128'b0),
.TAB(5'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
// wire cena = 1;
// wire cenb = shm_write;
// wire[3:0][31:0] write_bit_mask;
// assign write_bit_mask[0] = (we == 2'b00) ? 1 : {32{1'b0}};
// assign write_bit_mask[1] = (we == 2'b01) ? 1 : {32{1'b0}};
// assign write_bit_mask[2] = (we == 2'b10) ? 1 : {32{1'b0}};
// assign write_bit_mask[3] = (we == 2'b11) ? 1 : {32{1'b0}};
// // Using ASIC MEM
// /* verilator lint_off PINCONNECTEMPTY */
// rf2_128x128_wm1 first_ram (
// .CENYA(),
// .AYA(),
// .CENYB(),
// .WENYB(),
// .AYB(),
// .QA(data_out),
// .SOA(),
// .SOB(),
// .CLKA(clk),
// .CENA(cena),
// .AA(addr),
// .CLKB(clk),
// .CENB(cenb),
// .WENB(write_bit_mask),
// .AB(addr),
// .DB(wdata),
// .EMAA(3'b011),
// .EMASA(1'b0),
// .EMAB(3'b011),
// .TENA(1'b1),
// .TCENA(1'b0),
// .TAA(5'b0),
// .TENB(1'b1),
// .TCENB(1'b0),
// .TWENB(128'b0),
// .TAB(5'b0),
// .TDB(128'b0),
// .RET1N(1'b1),
// .SIA(2'b0),
// .SEA(1'b0),
// .DFTRAMBYP(1'b0),
// .SIB(2'b0),
// .SEB(1'b0),
// .COLLDISN(1'b1)
// );
// /* verilator lint_on PINCONNECTEMPTY */
`endif
endmodule

2
rtl/simulate/tb_debug.h
View File

@@ -1 +1 @@
#define VCD_OFF
#define VCD_OUTPUT