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142cbb8f3b
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minor update
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2021-09-14 09:17:08 -04:00 |
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4e8293c3e3
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cache bank pipeline optimization
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2021-09-14 02:09:35 -07:00 |
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5192846c72
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minor updates
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2021-09-10 02:57:05 -07:00 |
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ca46b0a0be
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OUTPUT_REG => OUT_REG renaming
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2021-09-09 03:05:38 -07:00 |
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134cbcfc5a
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optimize critical path inside cache bank
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2021-09-07 23:44:51 -07:00 |
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3e014c8285
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fmax optimizations bundles
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2021-09-06 01:36:57 -07:00 |
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90b50277d0
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cache multi-porting fixes + optimization
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2021-08-29 18:33:49 -07:00 |
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e26cfab04d
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bank area optimization
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2021-08-29 02:25:55 -07:00 |
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6674e8c44a
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cache bank area optimization + multi-porting fix for l2/l3 caches
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2021-08-28 21:34:06 -07:00 |
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26e94dde44
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cache area optimization by disabling BRAM read-during-write bypassing for tag/data stores
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2021-08-26 12:27:38 -07:00 |
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f12be56d7c
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fixed Verilator warnings
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2021-08-13 05:52:43 -04:00 |
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c2b3aaa7d1
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enabling delayed tracing
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2021-08-12 20:05:43 -07:00 |
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9098495153
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MSHR Redesign: removed fifo replay constraints and overheads
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2021-08-12 01:49:32 -07:00 |
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7b8fe11e6a
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unused variables refactoring
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2021-08-05 01:46:26 -07:00 |
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6525dff158
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fixed no shared memory bug, fixed cache debug log
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2021-08-02 15:59:33 -07:00 |
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b307c40ae7
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mshr critical path optimization
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2021-07-26 21:11:17 -07:00 |
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ea1e0f201e
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OUTPUT_REG refactoring
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2021-07-23 06:58:37 -07:00 |
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1f94a1e673
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minor update
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2021-07-22 14:11:59 -07:00 |
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b3e54a837e
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minor update
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2021-07-20 12:01:04 -07:00 |
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53b3d42908
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cache's core response queue size control
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2021-07-16 13:09:29 -07:00 |
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0bec734532
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icache readonly optimization
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2021-07-15 14:16:05 -07:00 |
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d9425cc484
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cache elastic buffer optimization
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2021-07-15 11:59:49 -07:00 |
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8678150ce0
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cache multi-porting optimization
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2021-07-15 11:54:27 -07:00 |
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10e9ee124b
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using onehot multiplexer to reduce critical path
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2021-07-08 00:26:59 -07:00 |
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f84c8a0b5d
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instr_sched => ibuffer
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2021-06-27 19:36:43 -07:00 |
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57143f5889
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synthesis optimizations
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2021-06-17 16:43:43 -07:00 |
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47c3234659
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minor update
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2021-06-13 10:58:48 -07:00 |
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5d2437d887
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refactoring cache_config
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2021-05-27 14:41:46 -07:00 |
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d8517d4d08
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minor update
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2021-05-26 13:37:07 -07:00 |
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Blaise Tine
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04a1c0e9eb
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IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr
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2021-05-01 13:44:08 -07:00 |
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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aff5903a22
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minor ibuffer critical path optimization.
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2021-04-19 20:53:13 -07:00 |
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625689796f
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minor update
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2021-04-04 23:42:57 -07:00 |
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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7560202f8b
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cache bank refactoring - removing unecessary core response fifo & restoring single port data access
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2021-02-21 21:47:46 -08:00 |
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ccb74ef286
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cache data access with decoupled read/write ports
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2021-02-21 15:18:24 -08:00 |
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05f93fac20
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minor update
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2021-02-20 13:15:15 -08:00 |
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Blaise Tine
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9eed48435c
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instruction decode optimization
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2021-02-14 00:19:54 -08:00 |
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Blaise Tine
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3c37db877a
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cache specialization for in-order DRAM reponses
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2021-02-13 20:23:29 -08:00 |
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Blaise Tine
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665b97b810
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multi-ported cache support for streaming
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2021-02-08 16:13:32 -08:00 |
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Blaise Tine
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111cc29482
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minor update
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2021-02-04 15:28:04 -08:00 |
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Blaise Tine
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32b94f61f2
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minor update
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2021-02-01 11:00:09 -08:00 |
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Blaise Tine
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62ff97d6e1
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minor update - smem perf update
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2021-02-01 10:29:20 -08:00 |
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Blaise Tine
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dc18bfabb8
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minor update - remove mshr data store
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2021-01-30 06:40:48 -08:00 |
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Blaise Tine
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5419859281
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fcvt fix
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2021-01-25 02:22:00 -08:00 |
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Blaise Tine
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8775f63ec4
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lkg build rollout with 16cores optimization on arria10
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2021-01-24 16:49:22 -08:00 |
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Blaise Tine
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74a687e395
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minor updates
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2021-01-18 05:43:30 -08:00 |
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Blaise Tine
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a7f6b9fffc
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minor updates
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2021-01-17 18:18:05 -08:00 |
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