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300eff4f9a89663343eeb83751a1ebe2f70683f3
Commit Graph

57 Commits

Author SHA1 Message Date
Hansung Kim
300eff4f9a Fix misleading maxSize param in Req/RespQueueEntry 2023-05-10 23:25:57 -07:00
Richard Yan
7bd9fd43f8 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-05-09 09:37:59 -07:00
Richard Yan
bce2c6230f more test fixes 2023-05-09 09:36:29 -07:00
Hansung Kim
2d4e28e862 Use WithoutTLMonitors to slightly speed up chiseltests 2023-05-08 14:38:15 -07:00
Hansung Kim
737a760fcd Enable coverage tests for chiseltest 2023-05-07 22:58:20 -07:00
Hansung Kim
a6dbfc3901 Fix config for unittest 2023-05-07 18:38:23 -07:00
Richard Yan
d2e56be157 update unit tests for new timing behavior & config 2023-05-07 14:35:53 -07:00
Richard Yan
86e7d3d60d numerous coalescer bug fixes + working unit test 2023-05-07 02:31:28 -07:00
Hansung Kim
42b03edbf7 Update import path to cde to reflect upstream changes 2023-05-05 14:51:13 -07:00
Hansung Kim
1fa2e36740 Add global enable to coalescer config 2023-05-04 16:38:38 -07:00
Richard Yan
ebd6c54d67 tl graph changes, coalescer bug fixes & coalescer unit test 2023-05-03 17:58:25 -07:00
Richard Yan
459c14bb62 add testing infrastructure for coalescing unit 2023-05-02 17:38:49 -07:00
Richard Yan
997b421c42 active byte lane implementation for multi coalescer & add one shift queue test 2023-05-02 00:07:45 -07:00
Richard Yan
6757ea1bbd shift queue bug fixes + new unit test 2023-05-01 00:51:31 -07:00
Richard Yan
55b2f7c33f reworked shift queue 2023-04-30 17:59:10 -07:00
Richard Yan
12d2912368 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-04-28 20:51:08 -07:00
Richard Yan
c655874470 width widget in DummyCoalescingUnitTB 2023-04-28 20:47:47 -07:00
Hansung Kim
fec788d648 Invalidate head when dequeued but allowShift was false 2023-04-28 15:46:45 -07:00
Hansung Kim
a49931ae60 Add invalidate/enq test case for depth=1 CoalShiftQueue 2023-04-28 15:08:39 -07:00
Hansung Kim
44d3c09b6d Fix used bit logic when invalidating but not dequeueing 2023-04-28 14:58:47 -07:00
Hansung Kim
2622bf04d3 Add allowShift to CoalShiftQueue IO to synchronize shifting 2023-04-28 14:12:51 -07:00
Hansung Kim
f7bf277e89 Fix unittest for CoalShiftQueue deq.valid change 2023-04-28 00:50:34 -07:00
Hansung Kim
b5b1a7da66 Add uncoalescer test case for all-lane-same-offset case 2023-04-27 21:53:36 -07:00
Hansung Kim
edc05d51e6 Fix not respecting invalidate.valid from coalescer 2023-04-27 21:35:26 -07:00
Hansung Kim
699520073e Make maxSize accessor function 2023-04-27 20:34:20 -07:00
Hansung Kim
ba2bc3020b Fix truncation bug in matchCount 2023-04-27 20:24:15 -07:00
Hansung Kim
84ac332637 Add chiseltest for stride = 0 2023-04-27 19:51:17 -07:00
Hansung Kim
7780250c7a More comments & renames 2023-04-27 19:17:07 -07:00
Richard Yan
900f5adb20 running coalescing flow 2023-04-26 01:23:21 -07:00
Richard Yan
99348e1e40 mostly running coalescing test 2023-04-25 02:50:14 -07:00
Richard Yan
3a0fdb2c67 WIP diplomacy set up for coal unit test 2023-04-25 02:26:13 -07:00
Richard Yan
be40c77d06 merge graphics 2023-04-25 00:10:51 -07:00
Richard Yan
37620400db WIP coalescing flow test 2023-04-25 00:09:23 -07:00
Hansung Kim
31e04e9402 Fix CoalShiftQueue invalidate logic 
IO type change to Valid[UInt] was not reflected in the valid bit logic.
 2023-04-24 14:01:39 -07:00
Hansung Kim
7539c39c45 Store SizeEnum in entry instead of UInt 2023-04-23 22:34:19 -07:00
Hansung Kim
0f2e4ee8aa Store UInt instead of ChiselEnum in entry; pass tests 
Scala isn't happy with storing ChiselEnum type for some reason
 2023-04-23 15:28:12 -07:00
Hansung Kim
8cee61a591 Uncoalesce using table size enum 2023-04-23 14:42:10 -07:00
Hansung Kim
ccf9b95fb5 Create custom response bundle to decouple from TileLink 
... and easier unit testing.
 2023-04-23 13:37:10 -07:00
Hansung Kim
6ae08b6541 Add missing sizeWidth to uncoalescer test 2023-04-21 11:24:57 -07:00
Hansung Kim
de6d6eee1a Fix request shift queue not enqueuing when empty 
The queue was enabling shifting of the registers whenever deq.ready
was 1, even when the queue was empty.  This caused `wen` to disable
writing enq.bits to any of the entries in the queue.  Fixed by setting
`shift` to 0 when queue is empty.
 2023-04-20 21:12:19 -07:00
Hansung Kim
abecd30b2b Store sourceId for every old req entry in table 2023-04-07 14:50:40 -07:00
Hansung Kim
d62732fb89 Invalidate outgoing per-lane requests that got coalesced 
Now the response queue no longer blocks the flow!
 2023-04-01 14:33:46 -07:00
Hansung Kim
d9f6e27a04 Move coalescer chiseltest to its own package 2023-03-31 20:51:34 -07:00
Hansung Kim
4aabbecda1 Do not deassert deq.valid right after invalidate(head) 
... to avoid combinational cycle.
 2023-03-31 20:40:12 -07:00
Hansung Kim
1c0c8fa112 Complete test for enqueuing to invalidated tail 2023-03-31 20:15:49 -07:00
Hansung Kim
3ee639f376 Eliminate unnecessary delay when invalidating head 
When invalidate signal is given for queue head, that head should be
gone immediately at the next cycle, regardless of what deq.ready was
at the previous cycle.
 2023-03-31 19:55:36 -07:00
Hansung Kim
6ca22a39e0 Implement automatic dequeuing of invalid entries 2023-03-31 19:40:10 -07:00
Hansung Kim
f44dfc8d5a Implement invalidation for the queue 2023-03-31 19:25:45 -07:00
Hansung Kim
a0d75530cb Use used mask in CoalShiftQueue 
Easier to use than wptr when enqueuing & dequeueing at the same time.
 2023-03-31 17:10:09 -07:00
Hansung Kim
303c43a5e2 Make CoalShiftQueue use wptr; add unit test 
Cannot solely rely on valid mask because there may be holes in the
middle.
 2023-03-29 19:06:08 -07:00