Hansung Kim
134dd4eb59
Update BlackBox to include Vortex 2.0
2023-11-15 21:58:40 -08:00
Hansung Kim
105bb37421
Make VortexCoreParams; bring VortexTile into rocketchip.tile
...
Reduces duplicate declarations. Need to properly split it out of
rocket-chip later.
2023-10-23 13:04:48 -07:00
Hansung Kim
ff302c1ba5
Use VortexTLAdapter for useVxCache = true as well
2023-10-18 20:04:31 -07:00
Hansung Kim
fb97bd3c2b
Decouple Vortex imem bundle from TL
2023-10-17 12:18:58 -07:00
Hansung Kim
8ab0529354
Move VortexBundleA/D to Core; resolve TODOs
2023-10-16 17:54:12 -07:00
Hansung Kim
eb9772b750
Decouple Vortex dmem bundle from TL
...
Previously VortexBundle was being instantiated using the parameters of
the TileLink bundle from VortexTile. This results in tight coupling
between Vortex interface parameters and downstream TileLink parameters.
This change adds a standalone Bundle used by the VortexCore wrapper
and is independently instantiated from the TL params, i.e. different
source widths. Ideally we want to move away from using TL-like
structures for VortexBundle and handling adapter logic completely
outside the core blackbox.
2023-10-16 17:42:17 -07:00
Hansung Kim
ff4fc66c56
Reformat
2023-10-15 13:36:55 -07:00
Hansung Kim
dab1d907d6
Comment out hartid and fpu from VortexBundle
...
These are mostly copied from Rocket and we're not sure they're necessary
for Vortex.
2023-10-11 20:29:15 -07:00
Hansung Kim
acc66e413a
Set Vortex CORE_ID parameter using Tile hartId
2023-10-11 20:28:04 -07:00
joshua
63aee46908
still not sure what error is
2023-09-23 17:52:02 -07:00
joshua
e3f85da12c
add vortex cache temporarily
2023-09-23 13:03:53 -07:00
Richard Yan
7c5281cd0e
multilane support, args.bin ROM, verilog sources cleanup and vortex bump
2023-09-15 11:16:55 -07:00
Richard Yan
d392d76608
bump vortex and increase source ids
2023-09-11 14:06:08 -07:00
Richard Yan
43f95175f1
bump verilog sources, remove files and mem changes
2023-09-09 01:55:02 -07:00
Richard Yan
8cef2ae135
integrate vortex as tile
2023-09-08 14:25:37 -07:00
