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  • 71db99911b extra cleanup [ci skip] abejgonzalez 2019-09-25 17:54:47 -07:00
  • c6df870912 [docs][ci skip] Update SHA3 description to reflect current RTL Jerry Zhao 2019-09-25 17:38:42 -07:00
  • 23b667ad76 [ci skip] [docs] Abe's comments 2 Brendan Sweeney 2019-09-25 17:27:10 -07:00
  • 438bb8c785 [docs] [skip ci] Change based on Abe's comments Brendan Sweeney 2019-09-25 17:26:44 -07:00
  • 2f3c87dade add explanation of LazyModule vs. LazyModuleImp [skip ci] Howard Mao 2019-09-25 17:25:38 -07:00
  • 824c3177d8 Added software section. Marshal is populated (mostly points to Marshal's own readthedocs). Spike is a stub. Nathan Pemberton 2019-09-25 17:22:18 -07:00
  • e8a197d8a8 [docs] [ci skip] Brendan Sweeney 2019-09-25 17:18:27 -07:00
  • 0f793bfb07 add makefile asm-tests note alonamid 2019-09-25 17:16:38 -07:00
  • b3d6ac3163 Merge pull request #253 from ucb-bar/raxi Albert Magyar 2019-09-25 17:09:39 -07:00
  • bb819cfbbf hwacha link alonamid 2019-09-25 16:56:32 -07:00
  • 2524b02806 PR comments alonamid 2019-09-25 16:52:54 -07:00
  • 9dc0abb485 explain how to add IceNet and TestChipIP hardware to design Howard Mao 2019-09-25 16:41:32 -07:00
  • beae2cfcf9 emphasize that firrtl-interpreter is deprecated | mention smaller modules [ci skip] abejgonzalez 2019-09-25 16:38:09 -07:00
  • 17578ddc93 [skip ci] docs bump for review Harrison Liew 2019-09-25 15:11:41 -07:00
  • 7ee395468d [docs][ci skip] Add docs on SHA3 mixin Jerry Zhao 2019-09-25 14:06:04 -07:00
  • 318cccd541 docs reorg alonamid 2019-09-25 14:03:54 -07:00
  • 38fef1782f add firrtl interpreter to the docs [ci skip] abejgonzalez 2019-09-25 13:50:22 -07:00
  • a3a05ec988 [docs] [ci skip] Update generators and quick start so it is clear how to edit the generators to get changed outputs (You just edit the source) Brendan Sweeney 2019-09-25 13:45:21 -07:00
  • fc0e86d744 Fix typo in tutorial config Albert Magyar 2019-09-25 13:37:59 -07:00
  • e90d53e31e add tranforms to index [ci skip] abejgonzalez 2019-09-25 13:20:16 -07:00
  • 9199a02e1e add literal references | cleanup firrtl-transform-docs [ci skip] abejgonzalez 2019-09-25 11:18:25 -07:00
  • c8e8465180 add Test Chip IP section [ci skip] Howard Mao 2019-09-25 13:01:51 -07:00
  • 12d4e7d837 add section on IceNet [ci skip] Howard Mao 2019-09-25 11:24:08 -07:00
  • f7138a8d71 Notes on building with macOS doesn't really work Brendan Sweeney 2019-09-25 12:53:08 -07:00
  • 50dfe03278 talk about fesvr and combine with dtm/jtag [skip ci] abejgonzalez 2019-09-25 12:30:48 -07:00
  • b858c76f09 fix rocket core ref alonamid 2019-09-25 12:28:39 -07:00
  • c6f5755900 some more hwacha info alonamid 2019-09-25 12:18:56 -07:00
  • 80328d0c4d clarify GPIO top example alonamid 2019-09-25 12:08:08 -07:00
  • 8fbf02c8fe fix index alonamid 2019-09-25 11:58:50 -07:00
  • 9af3391f87 fix index alonamid 2019-09-25 11:56:34 -07:00
  • eae7645159 sifive generators alonamid 2019-09-25 11:56:26 -07:00
  • 8b61a9d51a [docs] SHA3 docs. Copypasta'd from old SHA3 content Jerry Zhao 2019-09-25 10:38:54 -07:00
  • 4c443d2077 start firrtl transform docs [skip ci] abejgonzalez 2019-09-25 10:26:40 -07:00
  • d046611943 hwacha update alonamid 2019-09-25 10:20:03 -07:00
  • 0168c8f841 Merge pull request #245 from ucb-bar/master Howard Mao 2019-09-26 01:00:35 +08:00
  • 5fe971efe5 Rocket core vs Rocket Chip alonamid 2019-09-25 09:29:31 -07:00
  • f44f3aacbf [FireChip] Allow users to register new EndpointBinders in P David Biancolin 2019-09-24 03:04:27 +00:00
  • 29898bb677 move documentation to docs/ and new Makefile plumbing Harrison Liew 2019-09-23 10:20:42 -07:00
  • 148421bcab Merge pull request #243 from ucb-bar/abe-doc-updates Abraham Gonzalez 2019-09-20 18:02:28 -07:00
  • fd6d3272e4 add quotes around core/tile [skip ci] abejgonzalez 2019-09-20 17:58:48 -07:00
  • 898f0fd2d4 cleanup grammar a bit [skip ci] abejgonzalez 2019-09-20 17:51:46 -07:00
  • ff992ef24e add hart of 2 to heter explanation | footnote about tile v core [skip ci] abejgonzalez 2019-09-20 17:36:53 -07:00
  • edaf99ca9a small clarifications + cleanup [skip ci] abejgonzalez 2019-09-20 12:22:39 -07:00
  • 37b934236a Merge pull request #241 from ucb-bar/no_unify Jerry Zhao 2019-09-20 10:41:05 -07:00
  • cfba37afc9 bump hammer, remove saed32 Harrison Liew 2019-09-19 22:43:18 -07:00
  • 971809a546 update submodules script Harrison Liew 2019-09-03 09:32:57 -07:00
  • e6027677b3 accidentally changed a make variable Harrison Liew 2019-09-02 23:35:52 -07:00
  • dc04c0cc8c margins for M2 DRCs Harrison Liew 2019-09-02 23:27:48 -07:00
  • d28077ff0b updated DCO collateral Harrison Liew 2019-09-02 16:59:14 -07:00
  • 7fe73bbe0d shouldn't have tools/B Harrison Liew 2019-09-01 18:13:11 -07:00
  • 6ad433d5c7 power straps fixes, sha3 w/ dco skeleton Harrison Liew 2019-09-01 18:09:38 -07:00
  • 6bc91680cd rebased on dev Harrison Liew 2019-09-01 14:12:49 -07:00
  • fb35782841 fix incorrect block for syn/par, but still have timing violations Harrison Liew 2019-09-01 10:42:49 -07:00
  • 6179a91a29 some plumbing but still need to remove sram generator target for asap7 Harrison Liew 2019-08-31 20:04:35 -07:00
  • 859492c2a2 added starter example.yml dpgrubb13 2019-08-31 00:40:25 -07:00
  • a44b043a2a additions to example-vlsi for asap7 demo dpgrubb13 2019-08-30 18:57:11 -07:00
  • 829f8fd84d [firechip] Remove unneeded HasDefaultBusConfiguration David Biancolin 2019-09-19 15:32:09 -07:00
  • 38588b67ef Bump FireSim, update reset delay in ScalaTests David Biancolin 2019-09-19 15:21:08 -07:00
  • 6bb1de5a59 Merge remote-tracking branch 'origin/dev' into midas2-endpoint-rework David Biancolin 2019-09-19 09:42:09 -07:00
  • c461540f65 Merge remote-tracking branch 'origin/dev' into midas2-endpoint-rework David Biancolin 2019-09-18 19:40:50 -07:00
  • 4c087b5c3f [firechip] Remove some antiquated midas imports David Biancolin 2019-09-17 23:50:04 -07:00
  • 26042b682c Replace UnifiedBoomConfig with SmallRv32BoomConfig Jerry Zhao 2019-09-17 15:36:56 -07:00
  • a77226cdba Merge pull request #240 from ucb-bar/order-fix Jerry Zhao 2019-09-16 16:01:51 -07:00
  • 17f1387846 Fix Sha3RocketConfig ordering Jerry Zhao 2019-09-16 15:54:32 -07:00
  • cfb14f26e4 Merge pull request #235 from ucb-bar/howie-docs Howard Mao 2019-09-17 06:03:01 +08:00
  • 6c26b447cc Merge pull request #238 from ucb-bar/vcs-vpd-fix Jerry Zhao 2019-09-16 10:59:46 -07:00
  • 99fa21348c move image to _static directory Howard Mao 2019-09-16 10:28:05 -07:00
  • 6465d9c591 move NodeTypes code to scala source Howard Mao 2019-09-16 10:25:10 -07:00
  • f96a70fc61 fix another instance of broken references Howard Mao 2019-09-16 10:21:10 -07:00
  • fce25f4486 Merge pull request #239 from ucb-bar/remove-published-deps David Biancolin 2019-09-13 11:22:24 -07:00
  • ce94ca7840 Fix Makefile .vpd rules not generating .out Jerry Zhao 2019-09-13 01:52:23 -07:00
  • ac8385a0c5 [firechip] Remove unneeded FASED target Mixin David Biancolin 2019-09-13 00:40:50 -07:00
  • 95ae46f4f2 [sbt] Use tools/chisel3 not rocketchip/chisel3 David Biancolin 2019-09-12 15:45:45 -07:00
  • 16cc565238 [sbt] Purge berkeley library dependencies from all subprojects David Biancolin 2019-09-12 15:39:56 -07:00
  • e68536a852 add Google Group to the index Howard Mao 2019-09-12 18:14:39 -07:00
  • d5bccc0455 add additional example code as literalincludes Howard Mao 2019-09-12 18:08:45 -07:00
  • 6ae60b94c6 correct capitalization in Adding an Accelerator/Device Howard Mao 2019-09-12 17:56:12 -07:00
  • 9a8d6c908f fix verilator invocation in Adding an Accelerator Howard Mao 2019-09-12 17:54:08 -07:00
  • 2d717bfcae add documentation code snippets to example project Howard Mao 2019-09-12 17:35:18 -07:00
  • 36b7944cb6 Merge pull request #230 from ucb-bar/midas2-merge David Biancolin 2019-09-12 17:17:54 -07:00
  • f31f629505 replace broken :numref: Howard Mao 2019-09-12 17:05:47 -07:00
  • a71153a94d fix some reference in Chipyard Components Howard Mao 2019-09-12 16:57:11 -07:00
  • 19a61b3c1a document return values of edge methods Howard Mao 2019-09-12 16:12:35 -07:00
  • 173743be6d [sbt] Remove the firrtl subproject David Biancolin 2019-09-11 18:29:38 -07:00
  • bc903b8407 more on customization of L1 Howard Mao 2019-09-12 14:34:57 -07:00
  • 069bb55442 a bit more explanation of site, here, up Howard Mao 2019-09-12 14:26:51 -07:00
  • c6f6b2e117 mention address of BootROM and first instruction Howard Mao 2019-09-10 11:10:00 -07:00
  • 200fec07e6 make purpose of CachelessRocketConfig clearer Howard Mao 2019-09-10 11:09:44 -07:00
  • 9bb4215c7d add changes Alon requested Howard Mao 2019-09-10 10:55:50 -07:00
  • 714d79e87d fix a AXI4UserYanker reference Howard Mao 2019-09-10 10:09:11 -07:00
  • cf5d64f8c8 fix Diplomacy Connectors symbols Howard Mao 2019-09-10 10:07:19 -07:00
  • 646d7cba4c use literalinclude directive to pull source directly from example package Howard Mao 2019-09-09 22:47:23 -07:00
  • fd5e0024a7 capitalize Diplomacy when used as a name Howard Mao 2019-09-09 20:28:30 -07:00
  • 1fee2b12f1 fix some language about TileLink's relationship to Diplomacy Howard Mao 2019-09-09 20:28:13 -07:00
  • a4371fa917 add section on SoC boot process Howard Mao 2019-09-09 18:07:08 -07:00
  • 753788ad67 add documentation on TileLink/AXI4 diplomatic widgets Howard Mao 2019-09-08 21:30:47 -07:00
  • e9bce0fc3d clarification of AddressRange arguments Howard Mao 2019-09-08 16:19:21 -07:00
  • 334e443003 add part about AXI4RegisterNode Howard Mao 2019-09-08 16:19:08 -07:00
  • 0e8dc833b8 write Register Router documentation Howard Mao 2019-09-07 22:34:08 -07:00
  • dfbf87061b get started on documenting TileLink/Diplomacy Howard Mao 2019-09-06 23:34:43 -07:00