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  • 5b1b4b3efe Bump Gemmini/Hwacha/Sha3 abejgonzalez 2020-11-19 15:28:24 -08:00
  • 95e8365105 Small change to Arty reset binder name, per Jerry's PR comment. James Dunn 2020-11-18 16:53:37 -08:00
  • 1b00d540f0 Add config fragment for replacing L2 with broadcastManager Jerry Zhao 2020-11-17 15:14:30 -08:00
  • a0d479f3ea Working FIRRTL/RC/Chisel3 build | chisel-testers still broken abejgonzalez 2020-11-16 22:55:04 -08:00
  • 9d9813fe0a [temp] Following RC's way to build Chisel from source or Maven [ci skip] abejgonzalez 2020-11-16 22:24:18 -08:00
  • fef06f2f97 Merge remote-tracking branch 'origin/dev' into hammer-docs alonamid 2020-11-16 17:07:31 -08:00
  • 1c0707b25b Merge remote-tracking branch 'origin' into hammer-docs alonamid 2020-11-16 17:06:33 -08:00
  • 70d43210d8 [temp] Unable to build/get past chisel-testers abejgonzalez 2020-11-15 18:18:04 -08:00
  • ba59d0318f Bump barstools abejgonzalez 2020-11-15 16:14:38 -08:00
  • 9ea23d43a7 Merge remote-tracking branch 'origin/dev' into local-chisel34 abejgonzalez 2020-11-15 16:03:25 -08:00
  • d94a8efd43 Fix TLMemPort comment | Use Option instead of NoSimulator abejgonzalez 2020-11-15 15:44:38 -08:00
  • c8add488ad Reduce BOOM default freq. (play it safe) abejgonzalez 2020-11-15 14:31:14 -08:00
  • f54dce13d6 Merge pull request #709 from ucb-bar/small-backwards-compat Abraham Gonzalez 2020-11-15 14:07:31 -08:00
  • d7cc6b9963 update hammer basic flow doc alonamid 2020-11-15 10:00:40 -08:00
  • 2dd8bb46b8 Merge branch 'hammer-docs' of https://github.com/ucb-bar/chipyard into hammer-docs Alon Amid 2020-11-15 09:59:57 -08:00
  • 06f90119f6 update example yml files Alon Amid 2020-11-15 09:56:45 -08:00
  • 650ba7cc63 Merge pull request #715 from ucb-bar/bus-crossing-fix David Biancolin 2020-11-14 15:37:08 -08:00
  • 8e5757b5ce Merge pull request #92 from sifive/chisel34 Chick Markley 2020-11-13 11:43:02 -08:00
  • f8bd8eaa27 Small fix to run_impl_bitstream abejgonzalez 2020-11-12 16:24:10 -08:00
  • 61e1730c90 Small fix to docs abejgonzalez 2020-11-12 16:23:05 -08:00
  • 1b4826ad82 Generalize debug-bitstream abejgonzalez 2020-11-12 16:20:22 -08:00
  • d4d989ce0f Rename make target to bitstream | Delete unused make stuff / tcl abejgonzalez 2020-11-12 15:41:05 -08:00
  • 63b3d4290f Change NotSimulator to NoSimulator abejgonzalez 2020-11-12 15:39:47 -08:00
  • 55f19f79d3 Address fpga srcs abejgonzalez 2020-11-12 15:39:29 -08:00
  • 999ae05bfe Address some docs, build.sbt, .gitmodules abejgonzalez 2020-11-12 15:31:34 -08:00
  • d5a0fd1a8e Address CircleCI abejgonzalez 2020-11-12 15:30:43 -08:00
  • 7ca3be236c Bump bringup VCU118 | Ignore HTIF if no-debug module abejgonzalez 2020-11-12 11:47:16 -08:00
  • 1110dd702c Bump RC, firesim and barstools for chisel3.4 updates Tim Snyder 2020-11-11 18:57:16 +00:00
  • 80487cc371 Update HierarchicalMulticlockBusTopologyParams to use cross{In, Out} David Biancolin 2020-11-10 11:58:53 -08:00
  • bb5d6bc9fb Merge pull request #713 from ucb-bar/better-bus-freq-spec David Biancolin 2020-11-09 19:18:44 -08:00
  • 714fb56423 Addressing PR comments in docs. dunn 2020-11-09 14:56:54 -08:00
  • 230bd81e0e [firechip] Update legacy firechip config David Biancolin 2020-11-08 11:20:24 -08:00
  • 098a83ce98 [CI] Add a multiclock config David Biancolin 2020-11-07 21:57:18 -08:00
  • 08c31014cc Build out a more complete multiclock example configuration David Biancolin 2020-11-07 21:29:31 -08:00
  • 4da9e49fc1 [clocking] Fix up() invocations in freq specification fragments David Biancolin 2020-11-07 21:24:04 -08:00
  • 04cd6b59bd [clocking] Add a fragment to set bus clock-sink freqs more intuitively David Biancolin 2020-11-07 18:45:48 -08:00
  • 41454650e7 Merge pull request #7 from ucb-bar/local-fpga-support-more-modular Abraham Gonzalez 2020-11-08 17:51:37 -08:00
  • 082b230452 Add missing file abejgonzalez 2020-11-08 17:51:21 -08:00
  • 244205e2b4 Separate new sys_clk and ddr2 from TSI abejgonzalez 2020-11-08 17:49:32 -08:00
  • a559d624df [clocking] Drive all buses directly from the asyncClockGroup David Biancolin 2020-11-07 18:42:29 -08:00
  • 38a6bae872 Add CI for Arty/VCU118 (just verilog) abejgonzalez 2020-11-07 17:27:19 -08:00
  • 9c12ce08b7 Create new prototyping section | Address some comments | Small clarifications abejgonzalez 2020-11-07 17:05:39 -08:00
  • 5a4cad0172 Merge pull request #6 from ucb-bar/local-fpga-support-docs Abraham Gonzalez 2020-11-06 21:03:15 -08:00
  • a9b9054120 Merge pull request #5 from ucb-bar/local-fpga-temp Abraham Gonzalez 2020-11-06 21:02:17 -08:00
  • c5e8fecb5c Small renaming and cleanup abejgonzalez 2020-11-06 21:00:18 -08:00
  • 9144e3c706 Fix pin mappings for TSI DDR Abraham Gonzalez 2020-11-06 20:51:11 -08:00
  • 8fb76dda7b Fixed syntax. James Dunn 2020-11-06 20:00:29 -08:00
  • e20311da84 Adding implementation details for the Arty. James Dunn 2020-11-06 19:58:52 -08:00
  • 98fcea7b57 Adding initial Arty documentation; will be expanded further. James Dunn 2020-11-06 17:25:05 -08:00
  • 7baa1341ee Use 2nd system clock for TSI DDR | Small cleanups abejgonzalez 2020-11-06 16:34:45 -08:00
  • 6aae66c54f Add TSI Host Widget abejgonzalez 2020-11-06 15:50:28 -08:00
  • 5c5a4b51e3 Merge pull request #710 from ucb-bar/rename-ariane Abraham Gonzalez 2020-11-06 14:53:54 -08:00
  • b7ef848605 Add some docs on debugging abejgonzalez 2020-11-06 11:13:27 -08:00
  • b0eed5075f [temp] start integrating tsi host widget Abraham Gonzalez 2020-11-06 10:57:55 -08:00
  • c721d897f3 Point to SiFive license | Add require on Arty abejgonzalez 2020-11-06 10:18:10 -08:00
  • 84508bee6e More FPGA prototyping docs abejgonzalez 2020-11-05 21:51:25 -08:00
  • 313fa4f129 Merge branch 'local-fpga-support' into local-fpga-support-docs abejgonzalez 2020-11-05 21:24:03 -08:00
  • b0fc0457aa Use Chipyard configs as base (Arty) abejgonzalez 2020-11-05 20:44:48 -08:00
  • 9a5b67bf8c Use Chipyard configs as a base (VCU118) abejgonzalez 2020-11-05 20:30:49 -08:00
  • 255e88fe8f Initial outline of FPGA prototyping docs abejgonzalez 2020-11-05 17:06:34 -08:00
  • 2de5f7dd7e [ci skip] Note that CVA6 was called Ariane in the past abejgonzalez 2020-11-05 15:48:50 -08:00
  • 083f34ab23 Revert Chipyard system | Create new VCU118 Chipyard system abejgonzalez 2020-11-05 15:44:54 -08:00
  • 43e64ded93 Readd ignore fpga-shells in main submodule setup abejgonzalez 2020-11-05 15:13:09 -08:00
  • a281869041 Fix Arty merge and errors from CY bump abejgonzalez 2020-11-05 15:04:44 -08:00
  • a7ab0dab59 Updated VCU118 | Bumped naming on Arty abejgonzalez 2020-11-05 13:59:10 -08:00
  • 356fa70c3c Update fpga-shells submodule | Fix Arty Makefile lines abejgonzalez 2020-11-05 11:16:17 -08:00
  • 3994bcecdf Merge remote-tracking branch 'secret/local-fpga-arty-harnessbinders' into local-fpga-support abejgonzalez 2020-11-05 11:08:36 -08:00
  • c619df2c00 Merge branch 'local-fpga-temp' into local-fpga-support abejgonzalez 2020-11-05 11:01:56 -08:00
  • 0685812c34 Bump CVA6 abejgonzalez 2020-11-05 10:30:00 -08:00
  • c083d5d947 Merge pull request #707 from ucb-bar/simple-pll-fixes David Biancolin 2020-11-05 09:59:54 -05:00
  • 60cd999002 Bump CVA6 for Make fix abejgonzalez 2020-11-04 21:09:24 -08:00
  • 9052b41328 Re-ignore QEMU from gnu-toolchain | Avoid piping make version in toolchain build Abraham Gonzalez 2020-11-04 20:59:14 -08:00
  • 59c9163bd5 Bump CVA6 for submodule fixes abejgonzalez 2020-11-04 18:37:26 -08:00
  • fc8c5e4b30 Use HTTPS for submodules abejgonzalez 2020-11-04 18:02:49 -08:00
  • 94eceeb624 Use empty variable instead of t/f Abraham Gonzalez 2020-11-04 15:54:09 -08:00
  • a2ebbee2ac Rename Ariane to CVA6 abejgonzalez 2020-11-04 15:05:11 -08:00
  • 5e3d1a605d Add --ignore-qemu flag to toolchains | Prepare QEMU when it builds Abraham Gonzalez 2020-11-04 11:57:23 -08:00
  • 16c34e2cf3 Bump Dromajo for old glibc Abraham Gonzalez 2020-11-04 11:46:02 -08:00
  • f504b7a0f5 [clocking] Improve reference clock selection using a multiple-of-fastest strategy David Biancolin 2020-11-03 09:13:18 -08:00
  • aa4a44925e [clocking] Add ScalaTests for the divider-only PLL configurator David Biancolin 2020-11-02 10:40:39 -08:00
  • f387634a41 [clocking] Bound SimplePllConfiguration by maximum reference freq David Biancolin 2020-11-02 10:38:37 -08:00
  • 946a191221 [clocking] Provide a default div for ClockDividerN sv implementation (#706) David Biancolin 2020-11-03 12:14:18 -05:00
  • 57a0bc5dfc Fix zsh compatibility in init-submodules-no-rv-tools (#705) David Biancolin 2020-11-03 12:14:02 -05:00
  • 37415157d6 Merge pull request #699 from ucb-bar/lazy-iobinders Jerry Zhao 2020-11-02 20:14:54 -08:00
  • 8bf23177d3 VLSI docs revamp midpoint alonamid 2020-11-02 14:32:39 -08:00
  • 0f3f283893 example ymls Alon Amid 2020-11-02 22:31:24 +00:00
  • 3e4fddbc69 make hammer work according to docs Alon Amid 2020-11-02 22:30:06 +00:00
  • 2d010b63f3 Merge branch 'dev' into lazy-iobinders Jerry Zhao 2020-11-02 10:02:44 -08:00
  • a38596323c Merge pull request #703 from ucb-bar/default-async-reset Jerry Zhao 2020-10-29 10:34:22 -07:00
  • 7b83da054a Clean up HarnessBinders Jerry Zhao 2020-10-28 16:18:22 -07:00
  • f4d70128c0 Remove redundant ChipTop reset synchronizer Jerry Zhao 2020-10-28 15:34:14 -07:00
  • 0eca51ba4d Reorganize into bringup/simple | Bump sifive-blocks Abraham Gonzalez 2020-10-27 12:57:34 -07:00
  • 3c42e2cae7 Fixed BootROM | Updated HarnessBinders Abraham Gonzalez 2020-10-26 18:15:58 -07:00
  • f387c4b994 Merge pull request #688 from amsharifian/patch-1 alonamid 2020-10-26 17:56:17 -07:00
  • 93e57ef230 Make the ChipTop reset pin async always Jerry Zhao 2020-10-26 15:18:34 -07:00
  • d61b31a6fe Merge pull request #702 from ucb-bar/multirocc-gemmini Jerry Zhao 2020-10-26 10:03:26 -07:00
  • 4fdb9eb6b0 Merge pull request #647 from ucb-bar/verilator-makefile-fix Fang, Zitao 2020-10-23 21:54:58 -07:00
  • abbeb2af9e Fixed comments Zitao Fang 2020-10-23 17:00:56 -07:00
  • 0c4dcffb0d Fixed lowercase p bug Zitao Fang 2020-10-23 16:39:56 -07:00
  • ac19117ec5 Add MultiRoCCGemmini config fragment Jerry Zhao 2020-10-23 15:41:49 -07:00