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  • 20d370be49 Merge branch 'firrtl-1.4-remove-clk-stuff' into chisel34 Tim Snyder 2020-10-23 13:08:48 -05:00
  • 446cb84cbf fixup! Update MacroCompiler for Chisel 3.4 Tim Snyder 2020-10-23 18:02:35 +00:00
  • aca4bd579f update build.sbt for Chisel3.4/FIRRTL1.4 Tim Snyder 2020-10-23 18:01:06 +00:00
  • fc3a3eabff Update MacroCompiler for Chisel 3.4 Tim Snyder 2020-10-21 21:08:51 +00:00
  • a07369acaf Merge remote-tracking branch 'ch/lazy-iobinders' into local-fpga-temp Abraham Gonzalez 2020-10-20 21:23:11 -07:00
  • db73cab164 Add BootROM | Fix ResetWrangler for DDR | Add scripts Abraham Gonzalez 2020-10-20 21:20:11 -07:00
  • 7a55c55aa3 Fix no-MBUS configs Jerry Zhao 2020-10-19 16:17:46 -07:00
  • e0bf907a06 Merge remote-tracking branch 'origin/dev' into lazy-iobinders Jerry Zhao 2020-10-19 13:22:01 -07:00
  • a3c0e3a0b2 Merge pull request #690 from ucb-bar/diplomatic-clocks-mbus-crossing David Biancolin 2020-10-19 15:15:09 -04:00
  • dd358f45ab UART Working... Bumped to newer fpga-shells Abraham Gonzalez 2020-10-19 11:29:25 -07:00
  • f3d666d2b7 Clarify HarnessBinders ClassTag naming Jerry Zhao 2020-10-19 10:16:44 -07:00
  • 11fdf69544 Merge pull request #693 from ucb-bar/smartelf2hex-memsiz Jerry Zhao 2020-10-19 09:05:50 -07:00
  • c5e3ad0a01 Bump tcip and fsim David Biancolin 2020-10-19 15:32:48 +00:00
  • 035e2e4315 Add test for make TOP=DigitalTop Jerry Zhao 2020-10-17 22:55:07 -07:00
  • 9927231bc4 Support lazy-iobinders Jerry Zhao 2020-10-17 22:47:50 -07:00
  • 1b94e7f10c Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing David Biancolin 2020-10-16 23:21:20 +00:00
  • 46ea900538 Merge pull request #695 from ucb-bar/shared-configs alonamid 2020-10-16 14:28:35 -07:00
  • 8de7aa8d69 bump firesim Alon Amid 2020-10-16 18:18:35 +00:00
  • 6eaac63e1b address PR comments Alon Amid 2020-10-16 06:34:26 +00:00
  • f3e1cb434d Merge pull request #696 from ucb-bar/no-default-core-fame-models David Biancolin 2020-10-15 18:03:27 -04:00
  • 84e0bf7338 Don't annotate cores with FAMEModelAnnotations Albert Magyar 2020-10-15 12:25:39 -07:00
  • 9ba4918cb8 Inject MMCDevice into TLSPI Node abejgonzalez 2020-10-15 11:46:42 -07:00
  • b747116363 Bump FireSim David Biancolin 2020-10-15 10:00:53 -07:00
  • 74c1c9d7ab Punch out reset in AXI4MMIO IOBinder David Biancolin 2020-10-15 10:00:07 -07:00
  • fd4a70dfb6 docs typos Alon Amid 2020-10-15 18:04:31 +00:00
  • 6479d54f53 bump firesim Alon Amid 2020-10-15 17:53:25 +00:00
  • c7a197d79a docs Alon Amid 2020-10-15 17:51:28 +00:00
  • 20d3b9f9ce bump firesim Alon Amid 2020-10-15 17:08:06 +00:00
  • 2c935b4ad7 pull firesim mem model config into firesim tweaks Alon Amid 2020-10-15 17:07:51 +00:00
  • 4a317b0cab differentiate default config package delimiter Alon Amid 2020-10-15 17:07:20 +00:00
  • 7f387a254b Working up until the MMC attachment abejgonzalez 2020-10-14 23:09:49 -07:00
  • dcac9b79df Basic working with UART abejgonzalez 2020-10-14 16:15:10 -07:00
  • 9c8d2948af [firechip] Fix a broken config David Biancolin 2020-10-14 15:33:32 -07:00
  • 6aefb73ab5 Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing David Biancolin 2020-10-14 15:29:00 -07:00
  • 949d60597f Revert "Support evaluation of HarnessBinders in LazyModule context" abejgonzalez 2020-10-14 14:50:38 -07:00
  • dda7622c29 temp commit abejgonzalez 2020-10-14 14:49:22 -07:00
  • 5f488bc068 Bump FireSim for multiclock FAME1 xform fix David Biancolin 2020-10-14 14:44:48 -07:00
  • 211c33f996 Address comments in #690 David Biancolin 2020-10-14 14:42:45 -07:00
  • 341a6cc48d Merge remote-tracking branch 'origin/lazy-harnessbinders' into local-fpga-temp abejgonzalez 2020-10-13 16:23:41 -07:00
  • 5bbd865447 Add MMC Device section to the DTS abejgonzalez 2020-10-13 16:18:00 -07:00
  • 9c298eedfe Support evaluation of HarnessBinders in LazyModule context Jerry Zhao 2020-10-13 15:10:41 -07:00
  • 8257775e96 Connect DDR from harness abejgonzalez 2020-10-12 21:50:50 -07:00
  • d958b8e1aa [ci skip] Update smartelf2hex to use MemSiz instead of FileSiz Jerry Zhao 2020-10-12 17:45:07 -07:00
  • 8f86b6d19a Merge pull request #683 from ucb-bar/unify-fesvr Jerry Zhao 2020-10-12 11:17:23 -07:00
  • 64632c8aee Merge pull request #686 from eddygta17/master Nathan Pemberton 2020-10-12 10:50:35 -07:00
  • 895dcd6831 referencing fully qualified chipyard.harness.OverrideHarnessBinder to debug import issue. James Dunn 2020-10-11 11:12:33 -07:00
  • dca56cd858 Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala. James Dunn 2020-10-10 19:55:02 -07:00
  • 54acfe71fc Some HarnessBinder testing with Jerry's debug suggestions. James Dunn 2020-10-10 13:45:27 -07:00
  • 7d1a1539e6 Initial pass at HarnessBinders for Arty. dunn 2020-10-09 23:17:36 -07:00
  • 0c46ed1676 Rename testchip_fesvr to testchip_tsi Jerry Zhao 2020-10-09 09:34:20 -07:00
  • 25129c27ca Add testchip_fesvr to uncondtionally used resources Jerry Zhao 2020-10-02 13:07:42 -07:00
  • d71c3b6357 Unify htif implementation with firesim Jerry Zhao 2020-10-02 11:22:55 -07:00
  • 986b5831c8 [clocking] Sketch out a topology that puts the MBUS is a separate domain David Biancolin 2020-10-09 07:23:17 -07:00
  • 30b278687b [clocking] Also aggregate clocks in AsyncClockGroup David Biancolin 2020-10-09 07:13:55 -07:00
  • b583276d1e Merge pull request #682 from ucb-bar/clocking-features Jerry Zhao 2020-10-08 14:39:53 -07:00
  • bf8dbaa297 Merge pull request #689 from ucb-bar/bumpMarshal1.10 Nathan Pemberton 2020-10-08 11:07:23 -07:00
  • 399b909dec Bump firemarshal to v1.10.0 Nathan Pemberton 2020-10-07 20:50:26 -04:00
  • 252f9c6a12 Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging. dunn 2020-10-07 11:55:16 -07:00
  • ce13ee920d Update Gemmini.rst Amirali Sharifian 2020-10-07 11:38:41 -07:00
  • 392d5b0801 [clocking] Synchronize all output clocks from DividerOnly generator David Biancolin 2020-09-30 13:18:44 -07:00
  • a67318928a Bumping submodules to upstream dev's commits. dunn 2020-10-07 09:02:30 -07:00
  • 5282965b5b Filter specified HTIF arguments and plusargs only Zitao Fang 2020-10-06 15:50:11 -07:00
  • 309b9ee7ae Merge remote-tracking branch 'upstream/dev' into local-fpga-arty-abe dunn 2020-10-06 12:23:18 -07:00
  • 9664b848e9 Pointing common.mk's SOURCE_DIR to subdirectories of fpga, to avoid circular dependency caused by pointing to fpga, which contains generated-src. dunn 2020-10-06 11:20:27 -07:00
  • 355e4ba606 Change to filter all arguments that begin with a '-' Zitao Fang 2020-10-05 10:49:04 -07:00
  • afc085a5f4 Removed AON block from E300 design. Debug over JTAG still functioning. James Dunn 2020-10-04 18:13:47 -07:00
  • 3d0022667a Bump testchipip Jerry Zhao 2020-10-01 22:43:43 -07:00
  • b057cfbd8c Merge remote-tracking branch 'origin/dev' into clocking-features Jerry Zhao 2020-10-01 20:12:20 -07:00
  • 2db3c90f83 Merge pull request #648 from ucb-bar/sodor-integrate Jerry Zhao 2020-10-01 17:31:45 -07:00
  • fb519e7b83 Merge pull request #679 from ucb-bar/add-multithreading-annos Albert Magyar 2020-10-01 14:23:54 -07:00
  • 79042e4ce8 Bump to support firesim simulation of no-AXI4DRAM designs Jerry Zhao 2020-10-01 10:21:43 -07:00
  • 164617e2d6 Fix no-mbus example design Jerry Zhao 2020-10-01 10:20:10 -07:00
  • 489ae695fc Add tile-resetter to all designs Jerry Zhao 2020-10-01 10:19:43 -07:00
  • 93a06cc5e7 Fix CI master check Zitao Fang 2020-10-01 10:11:04 -07:00
  • 6c33672c66 Bump Sodor submodule after merge Zitao Fang 2020-10-01 10:08:39 -07:00
  • 2f5790d611 Add model multi-threading annotations (ignored by default) to FireChip Albert Magyar 2020-09-30 12:04:22 -07:00
  • 45d40eb2af Merge pull request #676 from ucb-bar/diplomatic-clocks-pll-redux David Biancolin 2020-09-30 22:30:35 -07:00
  • a1dfd4f774 Remove all of the PadStuff chick 2020-09-30 15:04:56 -07:00
  • 7d7f7ae4a8 Bump FireSim David Biancolin 2020-09-30 14:43:29 -07:00
  • ef03a5efe0 Bump testchipip Zitao Fang 2020-09-30 14:36:45 -07:00
  • ebfe3103a4 [clocks] IdealizedPll -> DividerOnlyClockGenerator David Biancolin 2020-09-29 17:33:49 -07:00
  • 5b414f5829 [clocks] Emit frequency summary for divider-only PLL model David Biancolin 2020-09-29 16:59:37 -07:00
  • a6ce850391 [clocks] ClockDividerN: make first output edge occur on first input edge David Biancolin 2020-09-29 16:06:48 -07:00
  • 8903c04c2d - fix call to ceilLog2 in macros chick 2020-09-29 10:59:48 -07:00
  • 1a82c082b3 - Make transfrorms run in as close to same order as before - Fix parsing of PadPlacement JSON chick 2020-09-29 10:11:46 -07:00
  • f51156bf1f - Fixed ResetNSpec chick 2020-09-28 15:34:36 -07:00
  • 0430403920 - Simplest way to make custom transforms run in same place as they did prior to Dependency API chick 2020-09-28 15:20:42 -07:00
  • 2aac38b4c8 Fix CI bug Zitao Fang 2020-09-27 23:15:10 -07:00
  • f7407709d2 Attempt to fix CI (2) Zitao Fang 2020-09-25 21:31:12 -07:00
  • 751c0c300e Remove comments Zitao Fang 2020-09-25 20:49:18 -07:00
  • 5243ee2a35 Add HTIF args back to emulator.cc Zitao Fang 2020-09-25 20:36:07 -07:00
  • 23847a6dca Merge branch 'dev' of github.com:ucb-bar/chipyard into verilator-makefile-fix Zitao Fang 2020-09-25 20:33:05 -07:00
  • 942766ad86 Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate Zitao Fang 2020-09-25 11:41:40 -07:00
  • b76972d34b Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-pll-redux David Biancolin 2020-09-25 10:52:33 -07:00
  • 67145c6ccd [clocking] Fix FireSim clock look up David Biancolin 2020-09-25 10:05:28 -07:00
  • 1b3514f95f [clocks] Specify a default frequency for TraceGen David Biancolin 2020-09-25 10:03:46 -07:00
  • 7b8a954d04 [firechip] Rework FireSim clocking to be more similar to default CY targets David Biancolin 2020-09-24 23:32:07 -07:00
  • cc949aadab [clocking] Address some of Colin's PR comments David Biancolin 2020-09-24 23:28:47 -07:00
  • f6989a1968 [clocks] Use the periphery frequency as the default David Biancolin 2020-09-24 23:24:08 -07:00
  • 96bf702c3b [clocks] Factor out the PLL calculations into their own class David Biancolin 2020-09-24 23:23:11 -07:00