Generalize debug-bitstream

2020-11-12 16:20:22 -08:00
parent d4d989ce0f
commit 1b4826ad82
3 changed files with 55 additions and 36 deletions
--- a/docs/Prototyping/General.rst
+++ b/docs/Prototyping/General.rst
@@ -60,7 +60,7 @@ ILA (integrated logic analyzers) can be added to certain designs for debugging r
 First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``).
 Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA).
 This can be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``.
-This will create a new bitstream called ``debug_output`` in the same location as the normal bitstream (``generated-src/<LONG_NAME>/obj``).
+This will create a new bitstream called ``top.bit`` in a folder named ``generated-src/<LONG_NAME>/debug_obj/``.
 For example, running the bitstream build for an added ILA for a BOOM config.:

 .. code-block:: shell
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -27,6 +27,7 @@ ifeq ($(SUB_PROJECT),vcu118)
 	TB                ?= none # unused
 	TOP               ?= ChipTop
 	BOARD             ?= vcu118
+	FPGA_BRAND        ?= xilinx
 endif

 ifeq ($(SUB_PROJECT),bringup)
@@ -40,6 +41,7 @@ ifeq ($(SUB_PROJECT),bringup)
 	TB                ?= none # unused
 	TOP               ?= ChipTop
 	BOARD             ?= vcu118
+	FPGA_BRAND        ?= xilinx
 endif

 ifeq ($(SUB_PROJECT),arty)
@@ -54,6 +56,7 @@ ifeq ($(SUB_PROJECT),arty)
 	TB                ?= none # unused
 	TOP               ?= ChipTop
 	BOARD             ?= arty
+	FPGA_BRAND        ?= xilinx
 endif

 include $(base_dir)/variables.mk
@@ -67,7 +70,7 @@ default: $(mcs)
 #########################################################################################
 # misc. directories
 #########################################################################################
-fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx
+fpga_dir := $(base_dir)/fpga/fpga-shells/$(FPGA_BRAND)
 fpga_common_script_dir := $(fpga_dir)/common/tcl

 #########################################################################################
@@ -98,10 +101,10 @@ $(BIT_FILE): $(synth_list_f)
 		-nojournal -mode batch \
 		-source $(fpga_common_script_dir)/vivado.tcl \
 		-tclargs \
-		-top-module "$(MODEL)" \
-		-F "$(synth_list_f)" \
-		-ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \
-		-board "$(BOARD)"
+			-top-module "$(MODEL)" \
+			-F "$(synth_list_f)" \
+			-ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \
+			-board "$(BOARD)"

 .PHONY: bitstream
 bitstream: $(BIT_FILE)
@@ -112,9 +115,10 @@ debug-bitstream: $(build_dir)/obj/post_synth.dcp
 		-nojournal -mode batch \
 		-source $(sim_dir)/scripts/run_impl_bitstream.tcl \
 		-tclargs \
-		$(build_dir)/obj/post_synth.dcp \
-		xcvu9p-flga2104-2l-e \
-		$(build_dir)/obj/debug_output
+			$(build_dir)/obj/post_synth.dcp \
+			$(BOARD) \
+			$(build_dir)/debug_obj \
+			$(fpga_common_script_dir)

 #########################################################################################
 # general cleanup rules
--- a/fpga/scripts/run_impl_bitstream.tcl
+++ b/fpga/scripts/run_impl_bitstream.tcl
@@ -2,44 +2,59 @@
 # argv[0] = absolute path to post_synth checkpoint file
 # argv[1] = part
 # argv[2] = output directory
+# argv[3] = common fpga brand tcl

 set synth_checkpoint_file [lindex $argv 0]
-set part [lindex $argv 1]
-set output_dir [lindex $argv 2]
+set board [lindex $argv 1]
+set wrkdir [lindex $argv 2]
+
+set scriptdir [lindex $argv 3]
+
+# Set the variable for all the common files
+set commondir [file dirname $scriptdir]
+
+# Set the variable that points to board specific files
+set boarddir [file join [file dirname $commondir] $board]
+source [file join $boarddir tcl board.tcl]

 # Set the project part to the part passed into this script
-set_part ${part}
+set_part $part_fpga

-# Create output directory if it doesn't exist
-file mkdir ${output_dir}
-file mkdir ${output_dir}/reports
-file mkdir ${output_dir}/outputs
+# Create output directories if they doesn't exist
+file mkdir $wrkdir
+set rptdir [file join $wrkdir report]
+file mkdir $rptdir

 # Load synthesis checkpoint
-open_checkpoint ${synth_checkpoint_file}
+open_checkpoint $synth_checkpoint_file

-# Run implementation and save reports as needed
+# opt
 opt_design
+write_checkpoint -force [file join $wrkdir post_opt]
+
+# place
 place_design
 phys_opt_design
-write_checkpoint -force ${output_dir}/outputs/post_place
-report_timing_summary -file ${output_dir}/reports/post_place_timing_summary.rpt
-report_drc -file ${output_dir}/reports/post_place_drc.rpt
+write_checkpoint -force [file join $wrkdir post_place]

+report_timing_summary -file [file join $rptdir post_place_timing_summary.rpt]
+report_drc -file [file join $rptdir post_place_drc.rpt]
+
+# route
 route_design
-write_checkpoint -force ${output_dir}/outputs/post_route
-report_timing_summary -file ${output_dir}/reports/post_route_timing_summary.rpt
-report_timing -sort_by group -max_paths 100 -path_type summary -file ${output_dir}/reports/post_route_timing.rpt
-report_clock_utilization -file ${output_dir}/reports/post_route_clock_utilization.rpt
-report_utilization -file ${output_dir}/reports/post_route_utilization.rpt
-report_drc -file ${output_dir}/reports/post_route_drc.rpt
-report_cdc -details -file ${output_dir}/reports/post_route_cdc.rpt
-report_clock_interaction -file ${output_dir}/reports/post_route_clock_interaction.rpt
-report_bus_skew -file ${output_dir}/reports/post_route_bus_skew.rpt
-report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file ${output_dir}/reports/post_route_timing_violations.rpt
+write_checkpoint -force [filel join $wrkdir post_route]
+report_timing_summary -file [file join $rptdir post_route_timing_summary.rpt]
+report_timing -sort_by group -max_paths 100 -path_type summary -file [file join $rptdir post_route_timing.rpt]
+report_clock_utilization -file [file join $rptdir post_route_clock_utilization.rpt]
+report_utilization -file [file join $rptdir post_route_utilization.rpt]
+report_drc -file [file join $rptdir post_route_drc.rpt]
+report_cdc -details -file [file join $rptdir post_route_cdc.rpt]
+report_clock_interaction -file [file join $rptdir post_route_clock_interaction.rpt]
+report_bus_skew -file [file join $rptdir post_route_bus_skew.rpt]
+report_design_analysis -logic_level_distribution -of_timing_paths [get_timing_paths -max_paths 1000 -slack_lesser_than 0] -file [file join $rptdir post_route_timing_violations.rpt]

-write_verilog -force ${output_dir}/outputs/post_route.v
-write_xdc -no_fixed_only -force ${output_dir}/outputs/post_route.xdc
-
-write_bitstream -force ${output_dir}/outputs/top.bit
-write_debug_probes -force ${output_dir}/outputs/debug_nets.ltx
+# bitstream
+write_verilog -force [file join $wrkdir post_route.v]
+write_xdc -no_fixed_only -force [file join $wrkdir post_route.xdc]
+write_bitstream -force [file join $wrkdir top.bit]
+write_debug_probes -force [file join $wrkdir debug_nets.ltx]