Jerry Zhao
1b00d540f0
Add config fragment for replacing L2 with broadcastManager
2020-11-17 15:14:30 -08:00
abejgonzalez
70d43210d8
[temp] Unable to build/get past chisel-testers
2020-11-15 18:18:04 -08:00
abejgonzalez
9ea23d43a7
Merge remote-tracking branch 'origin/dev' into local-chisel34
2020-11-15 16:03:25 -08:00
abejgonzalez
d94a8efd43
Fix TLMemPort comment | Use Option instead of NoSimulator
2020-11-15 15:44:38 -08:00
abejgonzalez
63b3d4290f
Change NotSimulator to NoSimulator
2020-11-12 15:39:57 -08:00
abejgonzalez
7ca3be236c
Bump bringup VCU118 | Ignore HTIF if no-debug module
2020-11-12 11:47:16 -08:00
Tim Snyder
1110dd702c
Bump RC, firesim and barstools for chisel3.4 updates
...
Note: firesim and barstools point to commits in the sifive forks of those repos
I didn't update the URL in .gitmodules because I'm not sure how that works in a PR
(because you wouldn't really want to merge sync'ing to the sifive repo).
Requires: ucb-bar/barstools#92 and firesim/firesim#658
The version of rocket-chip, chisel3 and firrtl is chosen here because it is
the latest known to pass my tests. You will likely want to bump further.
2020-11-11 18:57:16 +00:00
David Biancolin
80487cc371
Update HierarchicalMulticlockBusTopologyParams to use cross{In, Out}
2020-11-10 11:58:53 -08:00
David Biancolin
230bd81e0e
[firechip] Update legacy firechip config
2020-11-09 09:26:30 -08:00
David Biancolin
08c31014cc
Build out a more complete multiclock example configuration
2020-11-09 09:26:23 -08:00
David Biancolin
4da9e49fc1
[clocking] Fix up() invocations in freq specification fragments
2020-11-09 08:32:25 -08:00
David Biancolin
04cd6b59bd
[clocking] Add a fragment to set bus clock-sink freqs more intuitively
2020-11-09 08:32:19 -08:00
David Biancolin
a559d624df
[clocking] Drive all buses directly from the asyncClockGroup
2020-11-07 21:57:42 -08:00
abejgonzalez
6aae66c54f
Add TSI Host Widget
2020-11-06 15:50:28 -08:00
Abraham Gonzalez
5c5a4b51e3
Merge pull request #710 from ucb-bar/rename-ariane
...
Rename Ariane to CVA6
2020-11-06 14:53:54 -08:00
Abraham Gonzalez
b0eed5075f
[temp] start integrating tsi host widget
2020-11-06 10:57:55 -08:00
abejgonzalez
b0fc0457aa
Use Chipyard configs as base (Arty)
2020-11-05 20:46:03 -08:00
abejgonzalez
9a5b67bf8c
Use Chipyard configs as a base (VCU118)
2020-11-05 20:30:49 -08:00
abejgonzalez
083f34ab23
Revert Chipyard system | Create new VCU118 Chipyard system
2020-11-05 15:44:54 -08:00
abejgonzalez
a7ab0dab59
Updated VCU118 | Bumped naming on Arty
2020-11-05 13:59:10 -08:00
abejgonzalez
3994bcecdf
Merge remote-tracking branch 'secret/local-fpga-arty-harnessbinders' into local-fpga-support
2020-11-05 11:08:36 -08:00
abejgonzalez
c619df2c00
Merge branch 'local-fpga-temp' into local-fpga-support
2020-11-05 11:01:56 -08:00
abejgonzalez
0685812c34
Bump CVA6
2020-11-05 10:30:00 -08:00
abejgonzalez
60cd999002
Bump CVA6 for Make fix
2020-11-04 21:09:24 -08:00
abejgonzalez
59c9163bd5
Bump CVA6 for submodule fixes
2020-11-04 18:37:26 -08:00
abejgonzalez
a2ebbee2ac
Rename Ariane to CVA6
2020-11-04 15:42:30 -08:00
David Biancolin
f504b7a0f5
[clocking] Improve reference clock selection using a multiple-of-fastest strategy
2020-11-03 09:14:55 -08:00
David Biancolin
aa4a44925e
[clocking] Add ScalaTests for the divider-only PLL configurator
2020-11-03 09:14:55 -08:00
David Biancolin
f387634a41
[clocking] Bound SimplePllConfiguration by maximum reference freq
2020-11-03 09:14:55 -08:00
David Biancolin
946a191221
[clocking] Provide a default div for ClockDividerN sv implementation ( #706 )
2020-11-03 12:14:18 -05:00
Jerry Zhao
2d010b63f3
Merge branch 'dev' into lazy-iobinders
2020-11-02 10:02:44 -08:00
Jerry Zhao
7b83da054a
Clean up HarnessBinders
2020-10-28 16:18:22 -07:00
Jerry Zhao
f4d70128c0
Remove redundant ChipTop reset synchronizer
2020-10-28 15:37:31 -07:00
Abraham Gonzalez
0eca51ba4d
Reorganize into bringup/simple | Bump sifive-blocks
2020-10-27 12:57:34 -07:00
Abraham Gonzalez
3c42e2cae7
Fixed BootROM | Updated HarnessBinders
2020-10-26 18:15:58 -07:00
Jerry Zhao
93e57ef230
Make the ChipTop reset pin async always
2020-10-26 15:18:34 -07:00
Jerry Zhao
d61b31a6fe
Merge pull request #702 from ucb-bar/multirocc-gemmini
...
Add MultiRoCCGemmini config fragment
2020-10-26 10:03:26 -07:00
Fang, Zitao
4fdb9eb6b0
Merge pull request #647 from ucb-bar/verilator-makefile-fix
...
Fix Verilator Simulation run-binary-debug Error
2020-10-23 21:54:58 -07:00
Zitao Fang
abbeb2af9e
Fixed comments
2020-10-23 17:00:56 -07:00
Zitao Fang
0c4dcffb0d
Fixed lowercase p bug
2020-10-23 16:39:56 -07:00
Jerry Zhao
ac19117ec5
Add MultiRoCCGemmini config fragment
2020-10-23 15:41:49 -07:00
Abraham Gonzalez
a07369acaf
Merge remote-tracking branch 'ch/lazy-iobinders' into local-fpga-temp
2020-10-20 21:23:11 -07:00
Jerry Zhao
7a55c55aa3
Fix no-MBUS configs
2020-10-20 01:12:28 -07:00
Jerry Zhao
e0bf907a06
Merge remote-tracking branch 'origin/dev' into lazy-iobinders
2020-10-19 13:22:01 -07:00
Abraham Gonzalez
dd358f45ab
UART Working... Bumped to newer fpga-shells
2020-10-19 11:29:25 -07:00
Jerry Zhao
f3d666d2b7
Clarify HarnessBinders ClassTag naming
2020-10-19 10:16:44 -07:00
Jerry Zhao
9927231bc4
Support lazy-iobinders
2020-10-17 22:47:50 -07:00
David Biancolin
1b94e7f10c
Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing
2020-10-16 23:21:20 +00:00
Alon Amid
6eaac63e1b
address PR comments
2020-10-16 06:34:26 +00:00
Albert Magyar
84e0bf7338
Don't annotate cores with FAMEModelAnnotations
2020-10-15 12:25:39 -07:00
