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Use Chipyard configs as a base (VCU118)

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abejgonzalez
2020-11-05 20:30:49 -08:00
parent 083f34ab23
commit 9a5b67bf8c
4 changed files with 21 additions and 24 deletions
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generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -49,6 +49,6 @@ class AbstractConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2
new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system