Merge pull request #710 from ucb-bar/rename-ariane

Rename Ariane to CVA6

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -21,7 +21,7 @@ import hwacha.{Hwacha}
 import gemmini.{Gemmini, GemminiConfigs}
 
 import boom.common.{BoomTileAttachParams}
-import ariane.{ArianeTileAttachParams}
+import cva6.{CVA6TileAttachParams}
 
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
@@ -120,7 +120,7 @@ class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
-    case tp: ArianeTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
     case other => other
   }

generators/chipyard/src/main/scala/TestSuites.scala

@@ -7,9 +7,6 @@ import freechips.rocketchip.tile.{XLen, TileParams}
 import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
-import boom.common.{BoomTileAttachParams}
-import ariane.{ArianeTileAttachParams}
-
 /**
  * A set of pre-chosen regression tests
  */

generators/chipyard/src/main/scala/config/ArianeConfigs.scala

@@ -1,19 +0,0 @@
-package chipyard
-
-import chisel3._
-
-import freechips.rocketchip.config.{Config}
-
-// ---------------------
-// Ariane Configs
-// ---------------------
-
-class ArianeConfig extends Config(
-  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.config.AbstractConfig)
-
-class dmiArianeConfig extends Config(
-  new chipyard.harness.WithSerialAdapterTiedOff ++     // Tie off the serial port, override default instantiation of SimSerial
-  new chipyard.config.WithDMIDTM ++                    // have debug module expose a clocked DMI port
-  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/CVA6Configs.scala

@@ -0,0 +1,19 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+// ---------------------
+// CVA6 Configs
+// ---------------------
+
+class CVA6Config extends Config(
+  new cva6.WithNCVA6Cores(1) ++                    // single CVA6 core
+  new chipyard.config.AbstractConfig)
+
+class dmiCVA6Config extends Config(
+  new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial
+  new chipyard.config.WithDMIDTM ++                // have debug module expose a clocked DMI port
+  new cva6.WithNCVA6Cores(1) ++                    // single CVA6 core
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/example/TutorialTile.scala

@@ -16,7 +16,7 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.amba.axi4._
 
-// Example parameter class copied from Ariane, not included in documentation but for compile check only
+// Example parameter class copied from CVA6, not included in documentation but for compile check only
 // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure
 // out what parameters you need before you write the parameter class
 case class MyCoreParams(
@@ -127,9 +127,9 @@ class MyTile(
 
   // TODO: Create TileLink nodes and connections here.
   // DOC include end: Tile class
-  
+
   // DOC include start: AXI4 node
-  // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more. 
+  // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more.
   val idBits = 4
   val memAXI4Node = AXI4MasterNode(
     Seq(AXI4MasterPortParameters(
@@ -160,17 +160,17 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
 
   // TODO: Create the top module of the core and connect it with the ports in "outer"
 
-  // If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like 
-  //   val core = Module(new MyCoreBlackbox(params...)) 
+  // If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like
+  //   val core = Module(new MyCoreBlackbox(params...))
   // (as described in the blackbox tutorial) and connect appropriate signals. See the blackbox tutorial
   // (link on the top of the page) for more info.
-  // You can look at https://github.com/ucb-bar/ariane-wrapper/blob/master/src/main/scala/ArianeTile.scala
+  // You can look at https://github.com/ucb-bar/cva6-wrapper/blob/master/src/main/scala/CVA6Tile.scala
   // for a Verilog example.
 
   // If your core is in Chisel, you can simply instantiate the top module here like other Chisel module
   // and connect appropriate signal. You can even implement this class as your top module.
   // See https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/common/tile.scala and
-  // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for 
+  // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for
   // Chisel example.
 
   // DOC include end: Implementation class

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -22,7 +22,7 @@ import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotatio
 import firesim.bridges._
 import firesim.configs.MemModelKey
 import tracegen.{TraceGenSystemModuleImp}
-import ariane.ArianeTile
+import cva6.CVA6Tile
 
 import boom.common.{BoomTile}
 import barstools.iocell.chisel._

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -128,7 +128,7 @@ class FireSimQuadRocketConfig extends Config(
   new chipyard.QuadRocketConfig)
 
 // A stripped down configuration that should fit on all supported hosts.
-// Flat to avoid having to reorganize the config class hierarchy to remove certain features 
+// Flat to avoid having to reorganize the config class hierarchy to remove certain features
 class FireSimSmallSystemConfig extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
@@ -188,13 +188,13 @@ class SupernodeFireSimRocketConfig extends Config(
   new FireSimRocketConfig)
 
 //**********************************************************************************
-//* Ariane Configurations
+//* CVA6 Configurations
 //*********************************************************************************/
-class FireSimArianeConfig extends Config(
+class FireSimCVA6Config extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks ++
-  new chipyard.ArianeConfig)
+  new chipyard.CVA6Config)
 
 //**********************************************************************************
 //* Multiclock Configurations

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -110,7 +110,7 @@ class RocketMulticlockF1Tests extends FireSimTestSuite(
   "FireSimMulticlockRocketConfig",
   "WithSynthAsserts_BaseF1Config")
 
-class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config")
+class CVA6F1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimCVA6Config", "BaseF1Config")
 
 // This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call.
 class CITests extends Suites(