Paul Rigge
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bf23d7aa6c
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Fix VCS build.
VCS doesn't use the same arguments for C headers that verilator uses.
Generate the dot-f file differently for the different simulators.
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2019-03-06 23:06:24 -08:00 |
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Paul Rigge
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8a522ba404
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Fix some build system problems.
1) Bump testchipip to include forgotten commit
2) Add some support for generating VCS files
3) Fix some makefile deps
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2019-03-06 22:10:31 -08:00 |
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John Wright
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acd76e5410
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Adding barstools to separate the top from harness and to generate the
memories as external modules, which makes VLSI flows easier to plug in.
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2019-02-13 21:13:08 -08:00 |
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Howard Mao
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4c8c6e29f0
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update rocket-chip again
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2018-04-18 17:13:07 -07:00 |
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Howard Mao
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7e70e3525f
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move bootrom to testchipip
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2018-04-17 15:13:47 -07:00 |
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Howard Mao
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d88c2fa84f
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add regression tests to makefile
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2018-02-23 13:48:45 -08:00 |
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Howard Mao
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91df4098f3
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remove SimpleNIC
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2017-08-31 11:06:41 -07:00 |
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Howard Mao
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cb6290539c
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add network simulation C++ code
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2017-07-01 19:58:31 -07:00 |
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Howard Mao
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bac811a173
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add ExampleTopWithBlockDevice and tests
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2017-06-21 11:09:55 -07:00 |
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Howard Mao
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3e2b6a1d55
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make clean should clean everything
Also add "make clean" for verisim"
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2017-06-07 17:14:46 -07:00 |
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Howard Mao
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062d443863
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upgrade to latest rocket-chip
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2017-05-25 12:55:52 -07:00 |
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Howard Mao
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27bd063441
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update to tilelink2
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2017-04-20 18:12:44 -07:00 |
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Howard Mao
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adb8c80ab3
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change up gitignore rules
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2017-02-07 17:37:26 -08:00 |
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Howard Mao
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964992cb12
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use TestDriver.v from rocket-chip instead of one from testchipip
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2016-10-24 17:04:17 -07:00 |
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Howard Mao
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9a6f0f57e5
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add vsim clean rule
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2016-10-21 21:08:34 -07:00 |
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Howard Mao
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7074420aba
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initial commit
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2016-10-21 16:03:26 -07:00 |
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