Zitao Fang
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bb1d0a10ae
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Stage 3 (single port) passed all tests
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2020-08-31 18:00:40 -07:00 |
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Zitao Fang
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5c5af7bfad
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Stage 3 passed all tests
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2020-08-28 18:37:47 -07:00 |
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Zitao Fang
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b0b09870dd
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2-stage core passed all tests
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2020-08-17 21:11:44 -07:00 |
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Zitao Fang
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84359abd19
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Isolated master adapter's TileLink valid signals from the core
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2020-08-16 16:07:38 -07:00 |
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Zitao Fang
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97f595f415
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1-stage passed all tests
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2020-08-16 15:41:44 -07:00 |
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Zitao Fang
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f6992c61c8
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5-stage CPU passed all tests
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2020-08-15 00:20:47 -07:00 |
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Zitao Fang
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03e50178f1
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Add misalignment detection & make M-extension test optional
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2020-08-14 16:00:38 -07:00 |
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Zitao Fang
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90a7caa323
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Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
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2020-08-12 14:27:08 -07:00 |
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Zitao Fang
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751215dec1
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5-stage core running
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2020-08-12 14:26:49 -07:00 |
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Colin Schmidt
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b3fe2cae24
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Merge pull request #639 from ucb-bar/esp-tsi-loadmem
Make fragment to generate and use hex from elfs
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2020-08-06 07:26:24 -07:00 |
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Zitao Fang
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7f5b324d06
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Added interrupt
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2020-08-05 17:16:36 -07:00 |
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Colin Schmidt
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8499b76941
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Bump esp-spike to master
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2020-08-05 15:36:13 -07:00 |
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Colin Schmidt
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caab6fb968
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Add run-binary-hex docs
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2020-08-05 11:27:14 -07:00 |
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Colin Schmidt
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edbb86ef98
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Move elf2hex preprocessing into separate script
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2020-08-05 11:23:48 -07:00 |
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Colin Schmidt
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5bfc289677
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Bump fesvr for better loadmem impl. Fix verilator loadmem support
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2020-08-05 10:05:02 -07:00 |
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Colin Schmidt
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93c7fef942
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We need to uppercase hex chars for bc
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2020-08-05 10:03:21 -07:00 |
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Howard Mao
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09cc1bb985
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Merge pull request #635 from ucb-bar/loadmem
Implement fast loadmem feature
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2020-08-04 15:39:45 -07:00 |
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Howard Mao
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813d1fdb9e
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bump firesim
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2020-08-03 16:09:16 -07:00 |
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Jerry Zhao
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3c4c4a1ad3
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Merge pull request #630 from banahogg/patch-1
Update BOOM URL in README.md
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2020-08-03 14:47:02 -07:00 |
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Jerry Zhao
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c7586be0c5
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Merge pull request #629 from ucb-bar/random-seed
Add RANDOM_SEED variable to set random init for VCS and Verilator simulations
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2020-08-03 14:46:16 -07:00 |
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Howard Mao
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d7f3f91f18
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implement fast loadmem feature
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2020-08-01 15:04:18 -07:00 |
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Zitao Fang
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a2bd26b91c
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Finished Sodor Design
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2020-07-31 20:54:42 -07:00 |
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ssteffl
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2e3b871beb
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Merge pull request #636 from ucb-bar/openroad
updated openroad hash
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2020-07-31 11:57:56 -07:00 |
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Sam Steffl
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16d4186ea4
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updated openroad hash
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2020-07-31 10:29:53 -07:00 |
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ssteffl
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88fceafb68
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Merge pull request #608 from ucb-bar/openroad
OpenROAD complete backend with nangate45
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2020-07-30 16:27:10 -07:00 |
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Zitao Fang
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98ef89cbde
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Created Internal Tiles
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2020-07-29 15:02:33 -07:00 |
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Zitao Fang
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6131ab58e5
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Connect cores
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2020-07-28 13:37:07 -07:00 |
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Zitao Fang
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14e2a9dbd1
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Fixed tile_master
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2020-07-24 14:17:29 -07:00 |
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Zitao Fang
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d56df6252c
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Sync
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2020-07-23 19:24:44 -07:00 |
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Nathan Pemberton
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29c924d45a
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Merge pull request #633 from ucb-bar/opensbi
Opensbi
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2020-07-22 10:00:47 -07:00 |
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Nathan Pemberton
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df07790a5a
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Bump FireMarshal/QEMU/riscv-isa-sim for OpenSBI
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2020-07-21 18:43:14 -07:00 |
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Jerry Zhao
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b719919934
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Add RANDOM_SEED variable to set random init for VCS and Verilator simulations
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2020-07-20 18:25:18 -07:00 |
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Fang, Zitao
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11c1e87638
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Merge pull request #615 from ucb-bar/custom-core-doc
Documentation for Third-Party Core Integration
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2020-07-20 11:56:56 -07:00 |
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Zitao Fang
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692b120b65
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Fixed typo
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2020-07-19 21:48:07 -07:00 |
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Zitao Fang
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0a39819f44
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Add source file note
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2020-07-19 21:46:32 -07:00 |
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Zitao Fang
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2c7e7f3199
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Fixed file links
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2020-07-19 21:36:50 -07:00 |
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banahogg
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ae1e44a9e3
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Update BOOM URL in README.md
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2020-07-18 17:44:52 -07:00 |
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Zitao Fang
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fddf218147
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5th revision
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2020-07-16 15:39:07 -07:00 |
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Zitao Fang
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7bb1a48b1a
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Connect TileLink nodes
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2020-07-16 14:12:29 -07:00 |
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Jerry Zhao
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862d1fb774
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Merge pull request #627 from ucb-bar/firrtl-logging
Add variable to control FIRRTL logging verbosity
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2020-07-16 13:45:57 -07:00 |
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Zitao Fang
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97b8c3035c
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Merge branch 'dev' of github.com:ucb-bar/chipyard into custom-core-doc
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2020-07-15 11:15:46 -07:00 |
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Zitao Fang
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9fbc0a5bea
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Add links
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2020-07-15 11:08:36 -07:00 |
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Zitao Fang
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7ea464dc90
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4th revision
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2020-07-14 12:49:36 -07:00 |
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Zitao Fang
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1933fd8cbe
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Update sodor package structure
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2020-07-14 12:10:12 -07:00 |
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Zitao Fang
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14399e88b3
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Minor change
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2020-07-12 01:23:34 -07:00 |
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Zitao Fang
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ced7ea634c
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3rd Revision
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2020-07-12 01:08:13 -07:00 |
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David Biancolin
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d5a2d43f85
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Merge pull request #612 from ucb-bar/zynq-target
[firechip] Add a small target that should fit on all hosts
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2020-07-10 18:12:34 -07:00 |
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Albert Ou
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fbc71d4215
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Merge pull request #625 from ucb-bar/uart
Override default baud rate for FireChip
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2020-07-10 10:55:50 -07:00 |
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Jerry Zhao
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f8c9b316e2
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Merge pull request #620 from ucb-bar/simple_configs
Deduplicate across Chipyard configs into a ChipyardBaseConfig
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2020-07-09 17:12:19 -07:00 |
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Jerry Zhao
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2196a621c6
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Pass FIRRTL_LOGLEVEL to GenerateTopAndHarness
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2020-07-09 12:39:17 -07:00 |
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