Merge pull request #608 from ucb-bar/openroad

OpenROAD complete backend with nangate45
This commit is contained in:
ssteffl
2020-07-30 16:27:10 -07:00
committed by GitHub
6 changed files with 101 additions and 17 deletions

3
vlsi/.gitignore vendored
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@@ -3,4 +3,5 @@ __pycache__
hammer*.log
build
src/test/output-*.json
generated-src
generated-src
output.json

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@@ -19,25 +19,27 @@ include $(base_dir)/variables.mk
#########################################################################################
sim_name ?= vcs # needed for GenerateSimFiles, but is unused
tech_name ?= asap7
tech_dir ?= $(if $(filter $(tech_name), asap7), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
tech_dir ?= $(if $(filter $(tech_name),asap7 nangate45),\
$(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \
$(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
SMEMS_COMP ?= $(tech_dir)/sram-compiler.json
SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
ifeq ($(tech_name),asap7)
MACROCOMPILER_MODE ?= --mode synflops
else
MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER)
endif
MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\
--mode synflops,\
-l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict)
ENV_YML ?= $(vlsi_dir)/env.yml
INPUT_CONFS ?= example.yml
HAMMER_EXEC ?= ./example-vlsi
INPUT_CONFS ?= $(if $(filter $(tech_name),nangate45),\
example-nangate45.yml,\
example-asap7.yml)
HAMMER_EXEC ?= example-vlsi
VLSI_TOP ?= $(TOP)
VLSI_HARNESS_DUT_NAME ?= dut
VLSI_OBJ_DIR ?= $(vlsi_dir)/build
ifneq ($(CUSTOM_VLOG), )
OBJ_DIR ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
ifneq ($(CUSTOM_VLOG),)
OBJ_DIR ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
else
OBJ_DIR ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
OBJ_DIR ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
endif
#########################################################################################

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@@ -0,0 +1,73 @@
#----------------------
# Technology Setup
#----------------------
vlsi.core.technology: nangate45
# the nangate45.tech.json can't reference the $OPENROAD environment variable,
# so we need to set the install dir here.
# TODO: figure out how to remove this, or override it within OpenROADTool
technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD"
vlsi.core.max_threads: 12
#----------------------
# General Hammer Inputs
#----------------------
# Hammer will auto-generate a CPF for simple power designs;
# see hammer/src/hammer-vlsi/defaults.yml for more info
vlsi.inputs.power_spec_mode: "auto"
vlsi.inputs.power_spec_type: "cpf"
# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock", period: "5ns", uncertainty: "0.5ns"}
]
# Generate Make include to aid in flow
vlsi.core.build_system: make
#----------------------
# Placement Constraints
#----------------------
# For nangate45, size should be multiple of (0.19,1.4) placement grid
vlsi.inputs.placement_constraints:
- path: "ChipTop"
type: toplevel
x: 0
y: 0
width: 3334.72
height: 3798.2
margins:
left: 0
right: 0
top: 0
bottom: 0
# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
## You should specify a location for the SRAM generator in the tech plugin
vlsi.core.sram_generator_tool_path: [
"hammer/src/hammer-vlsi/technology/nangate45"]
vlsi.core.sram_generator_tool_path_meta: "append"
#----------------------
# Tool options. Replace with your tool plugin of choice.
#----------------------
# OpenROAD-yosys options
vlsi.core.synthesis_tool: "yosys"
vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"]
vlsi.core.synthesis_tool_path_meta: "append"
# OpenROAD-par options
vlsi.core.par_tool: "openroad"
vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"]
vlsi.core.par_tool_path_meta: "append"
# OpenROAD-drc options (no lvs)
vlsi.core.drc_tool: "openroad"
vlsi.core.drc_tool_path: ["hammer/src/hammer-vlsi/drc"]
vlsi.core.drc_tool_path_meta: "append"

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@@ -1,4 +1,8 @@
#!/usr/bin/env python3
#
# NOTE: this ExampleDriver works for asap7 and nangate45. the custom hooks are
# only used for asap7 though.
import os
import hammer_vlsi
@@ -7,21 +11,24 @@ from hammer_vlsi import CLIDriver, HammerToolHookAction
from typing import Dict, Callable, Optional, List
def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
x.append('''
if x.get_setting("vlsi.core.technology") == "asap7":
x.append('''
# TODO
# Place custom TCL here
''')
return True
def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
x.append('''
if x.get_setting("vlsi.core.technology") == "asap7":
x.append('''
# TODO
# Place custom TCL here
''')
return True
def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool:
x.append('''
if x.get_setting("vlsi.core.technology") == "asap7":
x.append('''
# TODO
# Place custom TCL here
set_db route_design_bottom_routing_layer 2
@@ -34,7 +41,8 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool:
Scale the final GDS by a factor of 4
hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script
"""
x.append('''
if x.get_setting("vlsi.core.technology") == "asap7":
x.append('''
# Write script out to a temporary file and execute it
set fp [open "{script_file}" "w"]
puts -nonewline $fp "{script_text}"