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Author SHA1 Message Date
Colin Schmidt
a00771d33a Merge branch 'master' into bump_chisel_3.2.x 2020-02-19 18:05:16 -08:00
Colin Schmidt
db0efd38fc Fix CI tests 2020-02-19 17:23:10 -08:00
Colin Schmidt
7de4c478c3 Update to chisel 3.2.x 2020-02-18 14:56:17 -08:00
Albert Magyar
8ca876503c Correctly specify width of default zero output value (#74) 2020-02-11 20:04:22 -07:00
Colin Schmidt
5198b3883c Merge pull request #73 from ucb-bar/rc-bump-aug-2019 
Rc bump aug 2019
 2019-12-12 13:20:53 -08:00
Colin Schmidt
e0081208b9 Updates for rocket-chip bump 2019-12-06 15:39:14 -08:00
Colin Schmidt
e4cce07c78 Fix issues after chisel update for august 2019 2019-12-06 15:38:19 -08:00
Abraham Gonzalez
3bba55ccc8 Merge pull request #68 from ucb-bar/print-firrtl-exception 
Print the firrtl exception if we get one
 2019-11-07 13:39:12 -08:00
Abraham Gonzalez
1e114d0355 Match inner variables 2019-11-07 10:17:24 -08:00
Abraham Gonzalez
7a0246ba7f Merge pull request #70 from ucb-bar/abejgonzalez-patch-1 
Fix MacroCompiler for CE-less Library Memories
 2019-11-06 23:37:20 -08:00
Abraham Gonzalez
ecc52b9b7c add test case for we bug 2019-11-05 21:29:57 -08:00
Abraham Gonzalez
4db4ebb5f5 Merge pull request #66 from ucb-bar/large-anno-remove 
Remove large annotations
 2019-11-05 17:16:03 -08:00
Abraham Gonzalez
34984802b2 enforce re is disabled when we is enabled 2019-11-05 14:16:53 -08:00
Abraham Gonzalez
46e2ecb9ae Fix MacroCompiler for CE-less Library Memories 
If a memory doesn't have a mask and doesn't have a chip enable, make sure that you use the `mem` chip enable to connect to the `we` port on the `lib` memory. Fixes a bug where the `lib` `we` signal would be tied to the `mem` `wmode` signal but then the macro would have no `en` signal connected to it.
 2019-11-05 14:04:31 -08:00
Abraham Gonzalez
8b0ef4d770 Merge pull request #69 from ucb-bar/abejgonzalez-patch-1 
Fix macrocompiler for RW mask port
 2019-11-04 13:23:05 -08:00
Abraham Gonzalez
6c59cac744 fix spacing 2019-10-28 13:47:07 -07:00
Abraham Gonzalez
be3b05a909 add test case 2019-10-28 13:45:05 -07:00
Colin Schmidt
c1004790cc Use x instead of e to match other case 2019-10-28 07:33:04 -07:00
Abraham Gonzalez
7f0828cb30 Fix macrocompiler for RW mask port 2019-10-25 20:42:55 -07:00
Colin Schmidt
c96a5e5f44 Print the firrtl exception if we get one 
Fixes #67
 2019-10-24 14:55:03 -07:00
Albert Magyar
76ccb75b00 Filter out all deleted annotations 2019-08-19 09:08:30 -07:00
Abraham Gonzalez
76f6c8adb2 remove large annotations 2019-08-17 10:35:41 -07:00
Albert Magyar
26096e07f6 Coordinate Top and Harness generation (#63) 
* Coordinate Top and Harness generation

* Update to use .f filename override annotations

* Move top generation to def to help GC
 2019-07-30 22:42:05 -07:00
Albert Magyar
e3c822709b Filter all EmittedAnnotations from JSON emission (#64) 
* Filter all EmittedAnnotations from JSON emission

* Filter more annotations
 2019-07-29 20:39:07 -07:00
John Wright
82636b3ff4 Upstream MemConf and use it (with some slight tweaks) 2019-05-14 10:10:47 -07:00
Colin Schmidt
c23b2b6f84 SRAM depth to bigint 
max synflop depth support
Fix annotation mangling on the harness side
 2019-05-14 10:10:47 -07:00
John Wright
e548210ef4 Add options to emit top/harness firrtl and annotations (#54) 2019-03-29 13:55:18 -07:00
Colin Schmidt
8f7af5b0bf Fix annos (#53) 
* Fixes #36 by using the renamemap
* Also fix harness passes annotation handling h/t azidar
* Remove old comment
 2019-03-27 17:20:41 -07:00
Colin Schmidt
affd033f0a Emit hammer IR from MacroCompiler (#50) 2019-03-25 22:52:39 -07:00
Colin Schmidt
fdad525007 HighForm has whens so we need to check for instances there (#49) 
Fixes a bug
 2019-03-18 11:25:58 -07:00
Abraham Gonzalez
817726ff1f stop exceptions on empty conf files (#43) 
* stop exceptions on empty conf files

* emit empty verilog file | warn users

* put else's on same line as closing bracket
 2019-03-18 10:15:50 -07:00
Colin Schmidt
de94c2376a Add Travis (#48) 2019-03-18 10:07:10 -07:00
Colin Schmidt
f5b452229a Avoid using the github redirect for mdf 2019-03-18 09:25:59 -07:00
Colin Schmidt
0b9d74ada7 Fix unit tests update cost function once more 
bump mdf to master
 2019-03-18 07:25:04 -07:00
Colin Schmidt
44e97826d4 Fix cost metric for non Compiler libs 
Also a small fix from reviewer
 2019-03-18 07:25:04 -07:00
Colin Schmidt
6cdf978a6d Fix forms of passes to happen before replseqmem 
This ensures the conf file doesn't have any testharness
memories, which are too big and break downstream tools
 2019-03-18 07:25:04 -07:00
Colin Schmidt
98a410812c Filter compiler libraries before mapping 
The filter is always by family and maskability and then by any
integral mappings.
 2019-03-18 07:25:04 -07:00
Colin Schmidt
a0510e6664 Change cost to double from BigInt and fix default metric 
I don't think it was adding anything and now we can get rid of
the weird +1/-1
 2019-03-18 07:25:04 -07:00
Colin Schmidt
45278a6de0 Make SRAM per port clocks optional 
Connects to whatever clock ports are available
 2019-03-18 07:25:04 -07:00
Colin Schmidt
a10a6cca35 Add SimDTM to list of extmodules 2019-03-01 18:52:41 -08:00
James Dunn
9d505d6063 Fixed index offset in mask port mapping. (#38) 
Fixed index offset in mask port mapping.
 2019-02-13 15:17:12 -08:00
John Wright
1f58ea1e14 Style/Comments from review of #35 2019-02-13 10:15:51 -08:00
John Wright
efd2f09b21 Naming consistency (memMode -> memFormat) 2019-02-13 10:15:51 -08:00
John Wright
f0c7bab3ea Use the correct 'magic values' for the port names 
Ensure backwards compatiblity by using -m for MDF input and -n for conf
input. Also fix the naming scheme for memory ports.
 2019-02-13 10:15:51 -08:00
John Wright
d861fdd95c Don't run DCE && Profit 2019-02-13 10:15:51 -08:00
John Wright
12842cb3a7 Add MemConf and change MacroCompiler to use a conf file instead of MDF JSON 2019-02-13 10:15:51 -08:00
John Wright
79b8fd324b This compiles and works correctly, but is kind of hacky, and will break as soon as any additional external/blackbox modules are added to the test harness. The test harness should detect external modules and not rename them instead of what is happening here. 2019-02-13 10:15:51 -08:00
John Wright
c8efc5e88b Refactor the harness generation; use upstream arguments and passes where appropriate 2019-02-13 10:15:51 -08:00
Paul Rigge
22e6d9c5d4 Fix repl-seq-mem 2019-02-13 10:15:51 -08:00
Paul Rigge
7bbf7f00f6 Run transforms in slightly different order 
Also, don't rename TestHarness.
 2019-02-13 10:15:51 -08:00