Jerry Zhao
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d61b31a6fe
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Merge pull request #702 from ucb-bar/multirocc-gemmini
Add MultiRoCCGemmini config fragment
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2020-10-26 10:03:26 -07:00 |
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Fang, Zitao
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4fdb9eb6b0
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Merge pull request #647 from ucb-bar/verilator-makefile-fix
Fix Verilator Simulation run-binary-debug Error
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2020-10-23 21:54:58 -07:00 |
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Zitao Fang
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abbeb2af9e
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Fixed comments
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2020-10-23 17:00:56 -07:00 |
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Zitao Fang
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0c4dcffb0d
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Fixed lowercase p bug
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2020-10-23 16:39:56 -07:00 |
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Jerry Zhao
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ac19117ec5
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Add MultiRoCCGemmini config fragment
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2020-10-23 15:41:49 -07:00 |
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David Biancolin
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1b94e7f10c
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Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing
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2020-10-16 23:21:20 +00:00 |
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Alon Amid
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6eaac63e1b
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address PR comments
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2020-10-16 06:34:26 +00:00 |
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Albert Magyar
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84e0bf7338
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Don't annotate cores with FAMEModelAnnotations
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2020-10-15 12:25:39 -07:00 |
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David Biancolin
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74c1c9d7ab
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Punch out reset in AXI4MMIO IOBinder
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2020-10-15 11:28:36 -07:00 |
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Alon Amid
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2c935b4ad7
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pull firesim mem model config into firesim tweaks
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2020-10-15 17:07:51 +00:00 |
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Alon Amid
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4a317b0cab
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differentiate default config package delimiter
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2020-10-15 17:07:20 +00:00 |
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David Biancolin
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9c8d2948af
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[firechip] Fix a broken config
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2020-10-14 15:33:32 -07:00 |
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David Biancolin
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6aefb73ab5
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Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing
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2020-10-14 15:29:00 -07:00 |
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David Biancolin
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211c33f996
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Address comments in #690
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2020-10-14 14:42:45 -07:00 |
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Jerry Zhao
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0c46ed1676
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Rename testchip_fesvr to testchip_tsi
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2020-10-09 09:34:20 -07:00 |
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Jerry Zhao
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25129c27ca
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Add testchip_fesvr to uncondtionally used resources
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2020-10-09 09:27:58 -07:00 |
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Jerry Zhao
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d71c3b6357
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Unify htif implementation with firesim
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2020-10-09 09:27:58 -07:00 |
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David Biancolin
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986b5831c8
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[clocking] Sketch out a topology that puts the MBUS is a separate domain
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2020-10-09 07:23:17 -07:00 |
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David Biancolin
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30b278687b
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[clocking] Also aggregate clocks in AsyncClockGroup
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2020-10-09 07:13:55 -07:00 |
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David Biancolin
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392d5b0801
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[clocking] Synchronize all output clocks from DividerOnly generator
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2020-10-07 09:32:48 -07:00 |
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Zitao Fang
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5282965b5b
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Filter specified HTIF arguments and plusargs only
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2020-10-06 15:50:11 -07:00 |
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Zitao Fang
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355e4ba606
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Change to filter all arguments that begin with a '-'
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2020-10-05 10:49:04 -07:00 |
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Jerry Zhao
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3d0022667a
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Bump testchipip
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2020-10-01 22:43:43 -07:00 |
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Jerry Zhao
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b057cfbd8c
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Merge remote-tracking branch 'origin/dev' into clocking-features
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2020-10-01 20:12:20 -07:00 |
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Jerry Zhao
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2db3c90f83
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Merge pull request #648 from ucb-bar/sodor-integrate
Sodor Integration
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2020-10-01 17:31:45 -07:00 |
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Jerry Zhao
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79042e4ce8
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Bump to support firesim simulation of no-AXI4DRAM designs
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2020-10-01 10:21:43 -07:00 |
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Jerry Zhao
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164617e2d6
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Fix no-mbus example design
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2020-10-01 10:20:10 -07:00 |
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Jerry Zhao
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489ae695fc
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Add tile-resetter to all designs
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2020-10-01 10:19:43 -07:00 |
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Zitao Fang
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6c33672c66
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Bump Sodor submodule after merge
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2020-10-01 10:08:39 -07:00 |
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Albert Magyar
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2f5790d611
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Add model multi-threading annotations (ignored by default) to FireChip
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2020-09-30 23:32:49 -07:00 |
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Zitao Fang
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ef03a5efe0
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Bump testchipip
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2020-09-30 14:36:45 -07:00 |
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David Biancolin
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ebfe3103a4
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[clocks] IdealizedPll -> DividerOnlyClockGenerator
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2020-09-29 17:33:49 -07:00 |
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David Biancolin
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5b414f5829
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[clocks] Emit frequency summary for divider-only PLL model
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2020-09-29 16:59:37 -07:00 |
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David Biancolin
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a6ce850391
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[clocks] ClockDividerN: make first output edge occur on first input edge
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2020-09-29 16:19:05 -07:00 |
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Zitao Fang
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2aac38b4c8
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Fix CI bug
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2020-09-27 23:15:10 -07:00 |
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Zitao Fang
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f7407709d2
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Attempt to fix CI (2)
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2020-09-25 21:31:12 -07:00 |
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Zitao Fang
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751c0c300e
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Remove comments
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2020-09-25 20:49:18 -07:00 |
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Zitao Fang
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5243ee2a35
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Add HTIF args back to emulator.cc
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2020-09-25 20:36:07 -07:00 |
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David Biancolin
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b76972d34b
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Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-pll-redux
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2020-09-25 11:02:51 -07:00 |
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David Biancolin
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67145c6ccd
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[clocking] Fix FireSim clock look up
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2020-09-25 10:05:28 -07:00 |
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David Biancolin
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1b3514f95f
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[clocks] Specify a default frequency for TraceGen
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2020-09-25 10:03:46 -07:00 |
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David Biancolin
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7b8a954d04
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[firechip] Rework FireSim clocking to be more similar to default CY targets
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2020-09-24 23:32:07 -07:00 |
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David Biancolin
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cc949aadab
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[clocking] Address some of Colin's PR comments
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2020-09-24 23:28:47 -07:00 |
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David Biancolin
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f6989a1968
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[clocks] Use the periphery frequency as the default
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2020-09-24 23:24:08 -07:00 |
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David Biancolin
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96bf702c3b
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[clocks] Factor out the PLL calculations into their own class
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2020-09-24 23:23:11 -07:00 |
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Zitao Fang
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6641c1f983
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Attempt to fix CI
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2020-09-24 22:42:49 -07:00 |
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David Biancolin
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84195d28bb
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[clocks] Don't override existing take frequency if present.
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2020-09-23 15:29:52 -07:00 |
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Zitao Fang
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a02700a1d4
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Add documentation for sodor
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2020-09-18 23:14:47 -07:00 |
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Zitao Fang
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0c8771c35e
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Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
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2020-09-18 22:33:42 -07:00 |
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Zitao Fang
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a43400acb9
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Update CI
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2020-09-18 15:36:33 -07:00 |
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