Jerry Zhao
d2b42cee2c
Bump testchipip
2020-09-12 23:31:54 -07:00
abejgonzalez
69bf39bf13
Added more overlays | Closer to bringup platform
2020-09-12 18:18:13 -07:00
chick
67de39e957
Refactor tapeout for Chisel 3.4, Firrtl 1.4
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- Remove clk package based on discussion with Colin
- Annotations need to be refactored to using latest API
- Generally that involves making annos generated by a anonymous ChiselAnnotation
- The chisel annotations will use RunFirrtlTransform to queue up its associated transform
- Chisel annotation provieds toFirrtl to generate Firrtl form of annotation
- Usages of unapply on firrtl annotations cannot use generic unapply(target, transform, data) which has been eliminated
- Have transforms use with DependencyAPIMigration to avoid deprecated `form`s
- Added some 'see License comments
- TechnologyLocation section of AddIOPadsSpec does not currently run because there is no content for it.
- Added some tests for annotation serialization here
2020-09-11 17:06:19 -07:00
abejgonzalez
382e5f1ae8
Add forgotten file
2020-09-11 17:02:22 -07:00
abejgonzalez
e98a0f172f
Connected UART nicely
2020-09-11 16:55:25 -07:00
Jerry Zhao
a5385c0a54
Update testchipip/icenet to use rocket-chip Located API
2020-09-11 00:02:07 -07:00
chick
e4cd2b01fe
This is mess clean it up
2020-09-10 14:35:10 -07:00
Zitao Fang
15d53e2cda
Bump to the latest Rocket
2020-09-09 15:12:37 -07:00
Jerry Zhao
facef464e6
Update BridgeBinders | fix runtime HarnessBinder port type checks
2020-09-09 00:15:02 -07:00
Jerry Zhao
8f9574fd79
Clean up passing ports from IOBinders to HarnessBinders
2020-09-08 22:30:17 -07:00
abejgonzalez
56eead4053
NOT WORKING: VCU118 Commit
2020-09-08 17:04:56 -07:00
Jerry Zhao
11a9ad2428
Address code review comments
2020-09-08 15:52:09 -07:00
abejgonzalez
2580073d75
Comment cleanup
2020-09-07 15:30:21 -07:00
abejgonzalez
c49eef3224
Small cleanup to CY DigitalTop | Move E300 configs to unique folder
2020-09-07 15:26:30 -07:00
Jerry Zhao
b4e270219d
Bump firesim
2020-09-07 14:02:31 -07:00
abejgonzalez
a8083aa570
First pass at fpga-shells with IOBinders
2020-09-07 11:48:27 -07:00
Jerry Zhao
7ed02a7d38
Fix Typos
2020-09-07 11:36:37 -07:00
Zitao Fang
fb7804070c
Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
2020-09-06 23:09:50 -07:00
Zitao Fang
11dcd71a48
Clean up 5-stage instruction fetch
2020-09-06 23:06:00 -07:00
Abraham Gonzalez
b6a54ead59
Merge pull request #669 from ucb-bar/local-fpga-arty-abe
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Misc Additions to Local FPGA Branch
2020-09-06 21:00:57 -07:00
Jerry Zhao
24b39da31c
Merge pull request #672 from ucb-bar/htif-dts-fix
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DTM only supports HTIF in DMI mode
2020-09-05 17:40:48 -07:00
Jerry Zhao
927244bf2e
DTM only supports HTIF in DMI mode
2020-09-05 11:45:06 -07:00
Jerry Zhao
ab21c53a42
Add documentation on HarnessBinders
2020-09-04 23:51:36 -07:00
Jerry Zhao
9eb88c55fc
Fix FireSim submodule
2020-09-04 23:07:23 -07:00
Jerry Zhao
b613c14f1c
Fix remaining HarnessBinders bugs
2020-09-04 20:03:12 -07:00
abejgonzalez
1fa1b6d57f
Small makefile cleanup
2020-09-04 19:03:26 -07:00
abejgonzalez
8eb807a2fd
Use DigitalTop in Platform | Use Chipyard BootRom
2020-09-04 18:56:32 -07:00
Jerry Zhao
0f50e4d118
Split IOBinders into IOBinders and Harness Binders | punch out clocks to harness for simwidgets and bridges
2020-09-04 15:20:13 -07:00
James Dunn
990362933d
Simple makefile variable fix to allow make mcs
2020-09-04 14:16:42 -07:00
Jerry Zhao
ba681676f3
Clean up IOCell types and parameterization
2020-09-04 13:29:31 -07:00
Jerry Zhao
178a0e38b5
Merge pull request #664 from ucb-bar/fix-debug-ios
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Only punch realistic subset of DebugIO through chiptop | default to JTAG+Serial
2020-09-04 09:47:59 -07:00
Jerry Zhao
3258fd8db8
Remove JTAG from firesim comfigs due to @(posedge ~clk) issue
2020-09-03 23:53:51 -07:00
abejgonzalez
5a885fdcfd
Delete old makefiles | Full switch to CY make system
2020-09-03 21:28:05 -07:00
abejgonzalez
0656c5da4f
First pass on using CY make system
2020-09-03 20:29:19 -07:00
Jerry Zhao
942d881c60
Merge pull request #667 from ucb-bar/fast-find
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Don't run find in base_dir to avoid slow filesystem search
2020-09-03 13:47:09 -07:00
Jerry Zhao
23e4c22a44
Don't run find in base_dir to avoid slow filesystem search
2020-09-02 23:52:55 -07:00
Zitao Fang
0995f1b04b
UCode passed all tests
2020-09-02 21:25:36 -07:00
Jerry Zhao
4b30462320
Change default IO set to JTAG+Serial, instead of JTAG+DMI
2020-09-02 20:19:27 -07:00
James Dunn
3b6d584672
Adding submodule update script for FPGA tools.
2020-09-02 13:27:31 -07:00
James Dunn
a8834c7766
First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
2020-09-02 12:48:44 -07:00
Zitao Fang
bb1d0a10ae
Stage 3 (single port) passed all tests
2020-08-31 18:00:40 -07:00
Jerry Zhao
c8448cc3e1
Bore out a bus clock to drive DebugIO from ChipTop
2020-08-30 18:10:52 -07:00
Zitao Fang
5c5af7bfad
Stage 3 passed all tests
2020-08-28 18:37:47 -07:00
Jerry Zhao
17239c56f8
Update AddIOCells.debug comment
2020-08-28 14:36:09 -07:00
Jerry Zhao
20013d1348
Add DTM based bringup to regressions
2020-08-28 14:31:00 -07:00
Jerry Zhao
5705f2645f
Bump toolchains
2020-08-28 14:31:00 -07:00
Jerry Zhao
27b78f4de2
Only punch realistic subset of DebugIO through chiptop
2020-08-28 14:30:59 -07:00
Jerry Zhao
98c4e6c711
Merge pull request #663 from ucb-bar/marshal-branch-check
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Add firemarshal's dev branch to its allowed-branch list
2020-08-28 09:50:03 -07:00
Jerry Zhao
933df4e05c
Whitelist firemarshal's dev branch for commit-on-master check
2020-08-27 23:27:24 -07:00
Jerry Zhao
ee1ce1141c
Merge pull request #614 from ucb-bar/diplomatic-clocks
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Diplomatic multiclock
2020-08-27 21:09:54 -07:00
