- Remove clk package based on discussion with Colin
- Annotations need to be refactored to using latest API
- Generally that involves making annos generated by a anonymous ChiselAnnotation
- The chisel annotations will use RunFirrtlTransform to queue up its associated transform
- Chisel annotation provieds toFirrtl to generate Firrtl form of annotation
- Usages of unapply on firrtl annotations cannot use generic unapply(target, transform, data) which has been eliminated
- Have transforms use with DependencyAPIMigration to avoid deprecated `form`s
- Added some 'see License comments
- TechnologyLocation section of AddIOPadsSpec does not currently run because there is no content for it.
- Added some tests for annotation serialization here
They no longer compile with the latest Chisel/FIRRTL, and
may not be supported. However, future work will need them, so
this keeps the files around but are ignored by sbt.
* modified CustomBundle to also apply on Int
* programmatic bundle should take T <: Data instead of Data
* turns out indexedElements doesn't synthesize
* had to change a bunch of files to get clk/pads compiling again with recent firrtl mods
[stevo]: adds a bunch of pad frame commits, as well as beginning work on clocking annotations and constraints
* start add io pads pass
* save progress adding yaml pad info
* saving some semi-presentable work -- parses yaml for pad templates and associates templates with ports
* added black boxes to the module; still need to hook up
* added supply pad yaml example; added option to not include pad for an IO, blackboxed that cat + bit extraction functions
* rewrite createbbs and some other parts of the transform
* finally got blackboxhelper to work -- seems there was a typo in the firrtl pass (?) have not connected them up properly in the padframe
* finished first version of pad transform; need to add bells and whistles + special case stuff
* made a bunch of changes in firrtl to shorthand things
* done with padframe for signals
* started major refactoring; first of pad yaml stuff
* forgot to update verilogTemplate -> verilog
* rename ParsePadYaml -> ChipPadsYaml; moved some stuff
* separated out stuff that describes pads i.e. direction, type, side
* forgot to update import for yamlhelpers
* trying to make the process of creating annotations more structured
* saving annotation helpers but prob better to switch to yaml
* saving changes -- reworking annotations
* fixing some bugs; properly annotated ports with pads
* annotate supply pads
* lesson (re)learned. cleaned up constants
* finished adding supply pads to pad frame; still need to generate io file
* also committing updated transform; still without io file
* big typo was causing pad verilog files not to be generated
* verilator passes with transform; had to fix verilog bb typo
* added unused pads; added more thorough tests + did visual inspection of output; made some port types more explicit
* renamed files/classes to be clearer
* started creating pad io template
* update spec so that transform order matters
* get rid of logger
* went around in circles with blackboxhelper + way to annotate
* finished adding + testing pad.io creation
* starting clkgen pass -- made model for asynchronously reset clk divider + wrappers for programmatic bundling
* temporarily locating albert's utility functions here
* saving work on clk constraints
* redid input config passing -- pass in tech directory instead; seems like getting clk sink, src, and relationship works
* not done; need to pause to do tapeout-y things. the clk gen pass gets all the clks and their sources, but i need to build a proper graph to handle clks coming out of muxes
* remove outdated files
* pulled resetinverter from dsptools + setup repo
* fix some package names, misc. dsptools dependencies, typo in build.sbt, + circuitstate in resetinverter pass
* add more comprehensive gitignore + license back in
* create directory structure to match package structure
* change package names to barstools.tapeout
* settled on barstools.tapeout.transforms package
* make directory + build structure more amenable for multiple sub projects
