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tests for macro compiler

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This commit is contained in:
Donggyu Kim
2017-07-04 16:30:23 -07:00
committed by edwardcwang
parent f3d39ad08f
commit 98155dd831
22 changed files with 1759 additions and 0 deletions
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35
tapeout/src/test/resources/macros/lib-1024x8-mrw.json Normal file
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[
{
"type": "sram",
"name": "vendor_sram",
"depth": 1024,
"width": 8,
"ports": [
{
"clock port name": "clock",
"mask granularity": 8,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
},
{
"type": "metal filler cell",
"name": "vender_dcap"
},
{
"type": "filler cell",
"name": "vender_fill"
}
]

27
tapeout/src/test/resources/macros/lib-1024x8-n28.json Normal file
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[
{
"type": "sram",
"name": "vendor_sram",
"depth": 1024,
"width": 8,
"ports": [
{
"clock port name": "clock",
"mask granularity": 1,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

34
tapeout/src/test/resources/macros/lib-1024x8-r-mw.json Normal file
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[
{
"type": "sram",
"name": "vendor_sram",
"depth": 1024,
"width": 8,
"ports": [
{
"clock port name": "clock",
"mask granularity": 8,
"output port name": "R0O",
"address port name": "R0A",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"address port polarity": "active high"
},
{
"clock port name": "clock",
"mask granularity": 8,
"input port name": "W0I",
"address port name": "W0A",
"mask port name": "W0M",
"chip enable port name": "W0E",
"write enable port name": "W0W",
"clock port polarity": "positive edge",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

24
tapeout/src/test/resources/macros/lib-2048x10-rw.json Normal file
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[
{
"type": "sram",
"name": "vendor_sram",
"depth": 2048,
"width": 10,
"ports": [
{
"clock port name": "clock",
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

52
tapeout/src/test/resources/macros/lib-2048x16-n28.json Normal file
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[
{
"type": "sram",
"name": "vendor_sram_16",
"depth": 2048,
"width": 16,
"ports": [
{
"clock port name": "clock",
"mask granularity": 1,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "vendor_sram_4",
"depth": 2048,
"width": 4,
"ports": [
{
"clock port name": "clock",
"mask granularity": 1,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

29
tapeout/src/test/resources/macros/lib-2048x8-mrw-re.json Normal file
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[
{
"type": "sram",
"name": "vendor_sram",
"depth": 2048,
"width": 8,
"ports": [
{
"clock port name": "clock",
"mask granularity": 8,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"read enable port name": "RW0R",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high",
"read enable port polarity": "active low"
}
]
}
]

27
tapeout/src/test/resources/macros/lib-2048x8-mrw.json Normal file
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[
{
"type": "sram",
"name": "vendor_sram",
"depth": 2048,
"width": 8,
"ports": [
{
"clock port name": "clock",
"mask granularity": 8,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

43
tapeout/src/test/resources/macros/lib-32x32-2rw.json Normal file
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[
{
"name": "SRAM2RW32x32",
"type": "sram",
"family": "2rw",
"depth": 32,
"width": 32,
"ports": [
{
"clock port name": "CE1",
"clock port polarity": "positive edge",
"address port name": "A1",
"address port polarity": "active high",
"input port name": "I1",
"input port polarity": "active high",
"output port name": "O1",
"output port polarity": "active high",
"read enable port name": "OEB1",
"read enable port polarity": "active low",
"write enable port name": "WEB1",
"write enable port polarity": "active low",
"chip enable port name": "CSB1",
"chip enable port polarity": "active low"
},
{
"clock port name": "CE2",
"clock port polarity": "positive edge",
"address port name": "A2",
"address port polarity": "active high",
"input port name": "I2",
"input port polarity": "active high",
"output port name": "O2",
"output port polarity": "active high",
"read enable port name": "OEB2",
"read enable port polarity": "active low",
"write enable port name": "WEB2",
"write enable port polarity": "active low",
"chip enable port name": "CSB2",
"chip enable port polarity": "active low"
}
]
}
]

27
tapeout/src/test/resources/macros/lib-32x80-mrw.json Normal file
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[
{
"type": "sram",
"name": "vendor_sram",
"depth": 32,
"width": 80,
"ports": [
{
"clock port name": "clock",
"mask granularity": 1,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

27
tapeout/src/test/resources/macros/mem-2000x8-mrw.json Normal file
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[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2000,
"width": 8,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 8,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

27
tapeout/src/test/resources/macros/mem-2048x16-mrw-2.json Normal file
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[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2048,
"width": 16,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 2,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

27
tapeout/src/test/resources/macros/mem-2048x16-mrw.json Normal file
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[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2048,
"width": 16,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 8,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

28
tapeout/src/test/resources/macros/mem-2048x20-mrw.json Normal file
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[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2048,
"width": 20,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 10,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

27
tapeout/src/test/resources/macros/mem-2048x8-mrw.json Normal file
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[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2048,
"width": 8,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 8,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

31
tapeout/src/test/resources/macros/mem-2048x8-r-mw.json Normal file
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[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2048,
"width": 8,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 8,
"input port name": "W0I",
"input port polarity": "active high",
"address port name": "W0A",
"address port polarity": "active high",
"mask port name": "W0M",
"mask port polarity": "active high",
"chip enable port name": "W0E",
"chip enable port polarity": "active high"
},
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"output port name": "R0O",
"output port polarity": "active high",
"address port name": "R0A",
"address port polarity": "active high"
}
]
}
]

22
tapeout/src/test/resources/macros/mem-24x52-r-w.json Normal file
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[
{
"type": "sram",
"name": "entries_info_ext",
"depth": 24,
"width": 52,
"ports": [
{
"clock port name": "R0_clk",
"output port name": "R0_data",
"address port name": "R0_addr",
"chip enable port name": "R0_en"
},
{
"clock port name": "W0_clk",
"input port name": "W0_data",
"address port name": "W0_addr",
"chip enable port name": "W0_en"
}
]
}
]

27
tapeout/src/test/resources/macros/mem-32x160-mrw.json Normal file
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[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 32,
"width": 160,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 20,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

76
tapeout/src/test/resources/macros/rocketchip.json Normal file
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[
{
"type": "sram",
"name": "tag_array_ext",
"depth": 64,
"width": 80,
"ports": [
{
"clock port name": "RW0_clk",
"mask granularity": 20,
"output port name": "RW0_rdata",
"input port name": "RW0_wdata",
"address port name": "RW0_addr",
"mask port name": "RW0_wmask",
"chip enable port name": "RW0_en",
"write enable port name": "RW0_wmode"
}
]
},
{
"type": "sram",
"name": "T_1090_ext",
"depth": 512,
"width": 64,
"ports": [
{
"clock port name": "RW0_clk",
"output port name": "RW0_rdata",
"input port name": "RW0_wdata",
"address port name": "RW0_addr",
"chip enable port name": "RW0_en",
"write enable port name": "RW0_wmode"
}
]
},
{
"type": "sram",
"name": "T_406_ext",
"depth": 512,
"width": 64,
"ports": [
{
"clock port name": "RW0_clk",
"mask granularity": 8,
"output port name": "RW0_rdata",
"input port name": "RW0_wdata",
"address port name": "RW0_addr",
"mask port name": "RW0_wmask",
"chip enable port name": "RW0_en",
"write enable port name": "RW0_wmode"
}
]
},
{
"type": "sram",
"name": "T_2172_ext",
"depth": 64,
"width": 88,
"ports": [
{
"clock port name": "W0_clk",
"mask granularity": 22,
"input port name": "W0_data",
"address port name": "W0_addr",
"chip enable port name": "W0_en",
"mask port name": "W0_mask"
},
{
"clock port name": "R0_clk",
"output port name": "R0_data",
"address port name": "R0_addr",
"chip enable port name": "R0_en"
}
]
}
]

186
tapeout/src/test/resources/macros/saed32.json Normal file
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[
{
"type": "sram",
"name": "SRAM1RW1024x8",
"width": 8,
"depth": 1024,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW512x32",
"width": 32,
"depth": 512,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW64x128",
"width": 128,
"depth": 64,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW64x32",
"width": 32,
"depth": 64,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW64x8",
"width": 8,
"depth": 64,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW512x8",
"width": 8,
"depth": 512,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM2RW64x32",
"width": 32,
"depth": 64,
"ports": [
{
"address port name": "A1",
"address port polarity": "active high",
"clock port name": "CE1",
"clock port polarity": "positive edge",
"write enable port name": "WEB1",
"write enable port polarity": "active low",
"read enable port name": "OEB1",
"read enable port polarity": "active low",
"chip enable port name": "CEB1",
"chip enable port polarity": "active low",
"output port name": "O1",
"output port polarity": "active high",
"input port name": "I1",
"input port polarity": "active high"
},
{
"address port name": "A2",
"address port polarity": "active high",
"clock port name": "CE2",
"clock port polarity": "positive edge",
"write enable port name": "WEB2",
"write enable port polarity": "active low",
"read enable port name": "OEB2",
"read enable port polarity": "active low",
"chip enable port name": "CEB2",
"chip enable port polarity": "active low",
"output port name": "O2",
"output port polarity": "active high",
"input port name": "I2",
"input port polarity": "active high"
}
]
}
]

296
tapeout/src/test/scala/transforms/macros/MacroCompilerSpec.scala Normal file
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package barstools.tapeout.transforms.macros
import firrtl._
import firrtl.ir.{Circuit, NoInfo}
import firrtl.passes.RemoveEmpty
import firrtl.Parser.parse
import java.io.{File, StringWriter}
abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalatest.Matchers {
val macroDir = new File("tapeout/src/test/resources/macros")
val testDir = new File("test_run_dir/macros") ; testDir.mkdirs
def args(mem: File, lib: Option[File], v: File, synflops: Boolean) =
List("-m", mem.toString, "-v", v.toString) ++
(lib match { case None => Nil case Some(l) => List("-l", l.toString) }) ++
(if (synflops) List("--syn-flops") else Nil)
def compile(mem: File, lib: Option[File], v: File, synflops: Boolean) {
MacroCompiler.run(args(mem, lib, v, synflops))
}
def execute(mem: Option[File], lib: Option[File], synflops: Boolean, output: String) {
require(mem.isDefined)
val macros = Utils.readJSON(mem).get map (x => (new Macro(x)).blackbox)
val circuit = Circuit(NoInfo, macros, macros.last.name)
val passes = Seq(new MacroCompilerPass(mem, lib), RemoveEmpty)
val result = (passes foldLeft circuit)((c, pass) => pass run c)
val gold = RemoveEmpty run parse(output)
(result.serialize) should be (gold.serialize)
}
}
class RocketChipTest extends MacroCompilerSpec {
val mem = new File(macroDir, "rocketchip.json")
val lib = new File(macroDir, "saed32.json")
val v = new File(testDir, "rocketchip.macro.v")
val output = // TODO: check correctness...
"""
circuit T_2172_ext :
module tag_array_ext :
input RW0_clk : Clock
input RW0_addr : UInt<6>
input RW0_wdata : UInt<80>
output RW0_rdata : UInt<80>
input RW0_en : UInt<1>
input RW0_wmode : UInt<1>
input RW0_wmask : UInt<4>
inst mem_0_0 of SRAM1RW64x32
inst mem_0_1 of SRAM1RW64x32
inst mem_0_2 of SRAM1RW64x32
inst mem_0_3 of SRAM1RW64x32
mem_0_0.CE <= RW0_clk
mem_0_0.A <= RW0_addr
node RW0_rdata_0_0 = bits(mem_0_0.O, 19, 0)
mem_0_0.I <= bits(RW0_wdata, 19, 0)
mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1")))
mem_0_0.CEB <= not(and(RW0_en, UInt<1>("h1")))
mem_0_1.CE <= RW0_clk
mem_0_1.A <= RW0_addr
node RW0_rdata_0_1 = bits(mem_0_1.O, 19, 0)
mem_0_1.I <= bits(RW0_wdata, 39, 20)
mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1")))
mem_0_1.CEB <= not(and(RW0_en, UInt<1>("h1")))
mem_0_2.CE <= RW0_clk
mem_0_2.A <= RW0_addr
node RW0_rdata_0_2 = bits(mem_0_2.O, 19, 0)
mem_0_2.I <= bits(RW0_wdata, 59, 40)
mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1")))
mem_0_2.CEB <= not(and(RW0_en, UInt<1>("h1")))
mem_0_3.CE <= RW0_clk
mem_0_3.A <= RW0_addr
node RW0_rdata_0_3 = bits(mem_0_3.O, 19, 0)
mem_0_3.I <= bits(RW0_wdata, 79, 60)
mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1")))
mem_0_3.CEB <= not(and(RW0_en, UInt<1>("h1")))
node RW0_rdata_0 = cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))
RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
extmodule SRAM1RW64x32 :
input CE : Clock
input A : UInt<6>
input I : UInt<32>
output O : UInt<32>
input CEB : UInt<1>
input OEB : UInt<1>
input WEB : UInt<1>
defname = SRAM1RW64x32
module T_1090_ext :
input RW0_clk : Clock
input RW0_addr : UInt<9>
input RW0_wdata : UInt<64>
output RW0_rdata : UInt<64>
input RW0_en : UInt<1>
input RW0_wmode : UInt<1>
inst mem_0_0 of SRAM1RW512x32
inst mem_0_1 of SRAM1RW512x32
mem_0_0.CE <= RW0_clk
mem_0_0.A <= RW0_addr
node RW0_rdata_0_0 = bits(mem_0_0.O, 31, 0)
mem_0_0.I <= bits(RW0_wdata, 31, 0)
mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_0.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1")))
mem_0_0.CEB <= not(and(RW0_en, UInt<1>("h1")))
mem_0_1.CE <= RW0_clk
mem_0_1.A <= RW0_addr
node RW0_rdata_0_1 = bits(mem_0_1.O, 31, 0)
mem_0_1.I <= bits(RW0_wdata, 63, 32)
mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_1.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1")))
mem_0_1.CEB <= not(and(RW0_en, UInt<1>("h1")))
node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0)
RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
module T_406_ext :
input RW0_clk : Clock
input RW0_addr : UInt<9>
input RW0_wdata : UInt<64>
output RW0_rdata : UInt<64>
input RW0_en : UInt<1>
input RW0_wmode : UInt<1>
input RW0_wmask : UInt<8>
inst mem_0_0 of SRAM1RW512x32
inst mem_0_1 of SRAM1RW512x32
inst mem_0_2 of SRAM1RW512x32
inst mem_0_3 of SRAM1RW512x32
inst mem_0_4 of SRAM1RW512x32
inst mem_0_5 of SRAM1RW512x32
inst mem_0_6 of SRAM1RW512x32
inst mem_0_7 of SRAM1RW512x32
mem_0_0.CE <= RW0_clk
mem_0_0.A <= RW0_addr
node RW0_rdata_0_0 = bits(mem_0_0.O, 7, 0)
mem_0_0.I <= bits(RW0_wdata, 7, 0)
mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1")))
mem_0_0.CEB <= not(and(RW0_en, UInt<1>("h1")))
mem_0_1.CE <= RW0_clk
mem_0_1.A <= RW0_addr
node RW0_rdata_0_1 = bits(mem_0_1.O, 7, 0)
mem_0_1.I <= bits(RW0_wdata, 15, 8)
mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1")))
mem_0_1.CEB <= not(and(RW0_en, UInt<1>("h1")))
mem_0_2.CE <= RW0_clk
mem_0_2.A <= RW0_addr
node RW0_rdata_0_2 = bits(mem_0_2.O, 7, 0)
mem_0_2.I <= bits(RW0_wdata, 23, 16)
mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1")))
mem_0_2.CEB <= not(and(RW0_en, UInt<1>("h1")))
mem_0_3.CE <= RW0_clk
mem_0_3.A <= RW0_addr
node RW0_rdata_0_3 = bits(mem_0_3.O, 7, 0)
mem_0_3.I <= bits(RW0_wdata, 31, 24)
mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1")))
mem_0_3.CEB <= not(and(RW0_en, UInt<1>("h1")))
mem_0_4.CE <= RW0_clk
mem_0_4.A <= RW0_addr
node RW0_rdata_0_4 = bits(mem_0_4.O, 7, 0)
mem_0_4.I <= bits(RW0_wdata, 39, 32)
mem_0_4.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_4.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 4, 4)), UInt<1>("h1")))
mem_0_4.CEB <= not(and(RW0_en, UInt<1>("h1")))
mem_0_5.CE <= RW0_clk
mem_0_5.A <= RW0_addr
node RW0_rdata_0_5 = bits(mem_0_5.O, 7, 0)
mem_0_5.I <= bits(RW0_wdata, 47, 40)
mem_0_5.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_5.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 5, 5)), UInt<1>("h1")))
mem_0_5.CEB <= not(and(RW0_en, UInt<1>("h1")))
mem_0_6.CE <= RW0_clk
mem_0_6.A <= RW0_addr
node RW0_rdata_0_6 = bits(mem_0_6.O, 7, 0)
mem_0_6.I <= bits(RW0_wdata, 55, 48)
mem_0_6.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_6.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 6, 6)), UInt<1>("h1")))
mem_0_6.CEB <= not(and(RW0_en, UInt<1>("h1")))
mem_0_7.CE <= RW0_clk
mem_0_7.A <= RW0_addr
node RW0_rdata_0_7 = bits(mem_0_7.O, 7, 0)
mem_0_7.I <= bits(RW0_wdata, 63, 56)
mem_0_7.OEB <= not(and(not(RW0_wmode), UInt<1>("h1")))
mem_0_7.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 7, 7)), UInt<1>("h1")))
mem_0_7.CEB <= not(and(RW0_en, UInt<1>("h1")))
node RW0_rdata_0 = cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))))))
RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
extmodule SRAM1RW512x32 :
input CE : Clock
input A : UInt<9>
input I : UInt<32>
output O : UInt<32>
input CEB : UInt<1>
input OEB : UInt<1>
input WEB : UInt<1>
defname = SRAM1RW512x32
module T_2172_ext :
input W0_clk : Clock
input W0_addr : UInt<6>
input W0_data : UInt<88>
input W0_en : UInt<1>
input W0_mask : UInt<4>
input R0_clk : Clock
input R0_addr : UInt<6>
output R0_data : UInt<88>
input R0_en : UInt<1>
inst mem_0_0 of SRAM2RW64x32
inst mem_0_1 of SRAM2RW64x32
inst mem_0_2 of SRAM2RW64x32
inst mem_0_3 of SRAM2RW64x32
mem_0_0.CE1 <= W0_clk
mem_0_0.A1 <= W0_addr
mem_0_0.I1 <= bits(W0_data, 21, 0)
mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), UInt<1>("h1")))
mem_0_0.CEB1 <= not(and(W0_en, UInt<1>("h1")))
mem_0_1.CE1 <= W0_clk
mem_0_1.A1 <= W0_addr
mem_0_1.I1 <= bits(W0_data, 43, 22)
mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 1, 1)), UInt<1>("h1")))
mem_0_1.CEB1 <= not(and(W0_en, UInt<1>("h1")))
mem_0_2.CE1 <= W0_clk
mem_0_2.A1 <= W0_addr
mem_0_2.I1 <= bits(W0_data, 65, 44)
mem_0_2.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
mem_0_2.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 2, 2)), UInt<1>("h1")))
mem_0_2.CEB1 <= not(and(W0_en, UInt<1>("h1")))
mem_0_3.CE1 <= W0_clk
mem_0_3.A1 <= W0_addr
mem_0_3.I1 <= bits(W0_data, 87, 66)
mem_0_3.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
mem_0_3.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 3, 3)), UInt<1>("h1")))
mem_0_3.CEB1 <= not(and(W0_en, UInt<1>("h1")))
mem_0_0.CE2 <= R0_clk
mem_0_0.A2 <= R0_addr
node R0_data_0_0 = bits(mem_0_0.O2, 21, 0)
mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
mem_0_0.CEB2 <= not(and(R0_en, UInt<1>("h1")))
mem_0_1.CE2 <= R0_clk
mem_0_1.A2 <= R0_addr
node R0_data_0_1 = bits(mem_0_1.O2, 21, 0)
mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
mem_0_1.CEB2 <= not(and(R0_en, UInt<1>("h1")))
mem_0_2.CE2 <= R0_clk
mem_0_2.A2 <= R0_addr
node R0_data_0_2 = bits(mem_0_2.O2, 21, 0)
mem_0_2.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
mem_0_2.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
mem_0_2.CEB2 <= not(and(R0_en, UInt<1>("h1")))
mem_0_3.CE2 <= R0_clk
mem_0_3.A2 <= R0_addr
node R0_data_0_3 = bits(mem_0_3.O2, 21, 0)
mem_0_3.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
mem_0_3.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
mem_0_3.CEB2 <= not(and(R0_en, UInt<1>("h1")))
node R0_data_0 = cat(R0_data_0_3, cat(R0_data_0_2, cat(R0_data_0_1, R0_data_0_0)))
R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<1>("h0"))
extmodule SRAM2RW64x32 :
input CE1 : Clock
input A1 : UInt<6>
input I1 : UInt<32>
output O1 : UInt<32>
input CEB1 : UInt<1>
input OEB1 : UInt<1>
input WEB1 : UInt<1>
input CE2 : Clock
input A2 : UInt<6>
input I2 : UInt<32>
output O2 : UInt<32>
input CEB2 : UInt<1>
input OEB2 : UInt<1>
input WEB2 : UInt<1>
defname = SRAM2RW64x32
"""
compile(mem, Some(lib), v, false)
}

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tapeout/src/test/scala/transforms/macros/SplitDepth.scala Normal file
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package barstools.tapeout.transforms.macros
import java.io.File
class SplitDepth2048x8_mrw extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-2048x8-mrw.json")
val lib = new File(macroDir, "lib-1024x8-mrw.json")
val v = new File(testDir, "split_depth_2048x8_mrw.v")
val output =
"""
circuit name_of_sram_module :
module name_of_sram_module :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<8>
output RW0O : UInt<8>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<1>
node RW0A_sel = bits(RW0A, 10, 10)
inst mem_0_0 of vendor_sram
mem_0_0.clock <= clock
mem_0_0.RW0A <= RW0A
node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
mem_0_0.RW0I <= bits(RW0I, 7, 0)
mem_0_0.RW0M <= bits(RW0M, 0, 0)
mem_0_0.RW0W <= and(RW0W, eq(RW0A_sel, UInt<1>("h0")))
mem_0_0.RW0E <= and(RW0E, eq(RW0A_sel, UInt<1>("h0")))
node RW0O_0 = RW0O_0_0
inst mem_1_0 of vendor_sram
mem_1_0.clock <= clock
mem_1_0.RW0A <= RW0A
node RW0O_1_0 = bits(mem_1_0.RW0O, 7, 0)
mem_1_0.RW0I <= bits(RW0I, 7, 0)
mem_1_0.RW0M <= bits(RW0M, 0, 0)
mem_1_0.RW0W <= and(RW0W, eq(RW0A_sel, UInt<1>("h1")))
mem_1_0.RW0E <= and(RW0E, eq(RW0A_sel, UInt<1>("h1")))
node RW0O_1 = RW0O_1_0
RW0O <= mux(eq(RW0A_sel, UInt<1>("h0")), RW0O_0, mux(eq(RW0A_sel, UInt<1>("h1")), RW0O_1, UInt<1>("h0")))
extmodule vendor_sram :
input clock : Clock
input RW0A : UInt<10>
input RW0I : UInt<8>
output RW0O : UInt<8>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<1>
defname = vendor_sram
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}
class SplitDepth2000x8_mrw extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-2000x8-mrw.json")
val lib = new File(macroDir, "lib-1024x8-mrw.json")
val v = new File(testDir, "split_depth_2000x8_mrw.v")
val output =
"""
circuit name_of_sram_module :
module name_of_sram_module :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<8>
output RW0O : UInt<8>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<1>
node RW0A_sel = bits(RW0A, 10, 10)
inst mem_0_0 of vendor_sram
mem_0_0.clock <= clock
mem_0_0.RW0A <= RW0A
node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
mem_0_0.RW0I <= bits(RW0I, 7, 0)
mem_0_0.RW0M <= bits(RW0M, 0, 0)
mem_0_0.RW0W <= and(RW0W, eq(RW0A_sel, UInt<1>("h0")))
mem_0_0.RW0E <= and(RW0E, eq(RW0A_sel, UInt<1>("h0")))
node RW0O_0 = RW0O_0_0
inst mem_1_0 of vendor_sram
mem_1_0.clock <= clock
mem_1_0.RW0A <= RW0A
node RW0O_1_0 = bits(mem_1_0.RW0O, 7, 0)
mem_1_0.RW0I <= bits(RW0I, 7, 0)
mem_1_0.RW0M <= bits(RW0M, 0, 0)
mem_1_0.RW0W <= and(RW0W, eq(RW0A_sel, UInt<1>("h1")))
mem_1_0.RW0E <= and(RW0E, eq(RW0A_sel, UInt<1>("h1")))
node RW0O_1 = RW0O_1_0
RW0O <= mux(eq(RW0A_sel, UInt<1>("h0")), RW0O_0, mux(eq(RW0A_sel, UInt<1>("h1")), RW0O_1, UInt<1>("h0")))
extmodule vendor_sram :
input clock : Clock
input RW0A : UInt<10>
input RW0I : UInt<8>
output RW0O : UInt<8>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<1>
defname = vendor_sram
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}
class SplitDepth2048x8_n28 extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-2048x8-mrw.json")
val lib = new File(macroDir, "lib-1024x8-n28.json")
val v = new File(testDir, "split_depth_2048x8_n28.v")
val output =
"""
circuit name_of_sram_module :
module name_of_sram_module :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<8>
output RW0O : UInt<8>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<1>
node RW0A_sel = bits(RW0A, 10, 10)
inst mem_0_0 of vendor_sram
mem_0_0.clock <= clock
mem_0_0.RW0A <= RW0A
node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
mem_0_0.RW0I <= bits(RW0I, 7, 0)
mem_0_0.RW0M <= cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), bits(RW0M, 0, 0))))))))
mem_0_0.RW0W <= and(RW0W, eq(RW0A_sel, UInt<1>("h0")))
mem_0_0.RW0E <= and(RW0E, eq(RW0A_sel, UInt<1>("h0")))
node RW0O_0 = RW0O_0_0
inst mem_1_0 of vendor_sram
mem_1_0.clock <= clock
mem_1_0.RW0A <= RW0A
node RW0O_1_0 = bits(mem_1_0.RW0O, 7, 0)
mem_1_0.RW0I <= bits(RW0I, 7, 0)
mem_1_0.RW0M <= cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), bits(RW0M, 0, 0))))))))
mem_1_0.RW0W <= and(RW0W, eq(RW0A_sel, UInt<1>("h1")))
mem_1_0.RW0E <= and(RW0E, eq(RW0A_sel, UInt<1>("h1")))
node RW0O_1 = RW0O_1_0
RW0O <= mux(eq(RW0A_sel, UInt<1>("h0")), RW0O_0, mux(eq(RW0A_sel, UInt<1>("h1")), RW0O_1, UInt<1>("h0")))
extmodule vendor_sram :
input clock : Clock
input RW0A : UInt<10>
input RW0I : UInt<8>
output RW0O : UInt<8>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<8>
defname = vendor_sram
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}
class SplitDepth2048x8_r_mw extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-2048x8-r-mw.json")
val lib = new File(macroDir, "lib-1024x8-r-mw.json")
val v = new File(testDir, "split_depth_2048x8_r_mw.v")
val output =
"""
circuit name_of_sram_module :
module name_of_sram_module :
input clock : Clock
input W0A : UInt<11>
input W0I : UInt<8>
input W0E : UInt<1>
input W0M : UInt<1>
input clock : Clock
input R0A : UInt<11>
output R0O : UInt<8>
node W0A_sel = bits(W0A, 10, 10)
node R0A_sel = bits(R0A, 10, 10)
inst mem_0_0 of vendor_sram
mem_0_0.clock <= clock
mem_0_0.W0A <= W0A
mem_0_0.W0I <= bits(W0I, 7, 0)
mem_0_0.W0M <= bits(W0M, 0, 0)
mem_0_0.W0W <= and(UInt<1>("h1"), eq(W0A_sel, UInt<1>("h0")))
mem_0_0.W0E <= and(W0E, eq(W0A_sel, UInt<1>("h0")))
mem_0_0.clock <= clock
mem_0_0.R0A <= R0A
node R0O_0_0 = bits(mem_0_0.R0O, 7, 0)
node R0O_0 = R0O_0_0
inst mem_1_0 of vendor_sram
mem_1_0.clock <= clock
mem_1_0.W0A <= W0A
mem_1_0.W0I <= bits(W0I, 7, 0)
mem_1_0.W0M <= bits(W0M, 0, 0)
mem_1_0.W0W <= and(UInt<1>("h1"), eq(W0A_sel, UInt<1>("h1")))
mem_1_0.W0E <= and(W0E, eq(W0A_sel, UInt<1>("h1")))
mem_1_0.clock <= clock
mem_1_0.R0A <= R0A
node R0O_1_0 = bits(mem_1_0.R0O, 7, 0)
node R0O_1 = R0O_1_0
R0O <= mux(eq(R0A_sel, UInt<1>("h0")), R0O_0, mux(eq(R0A_sel, UInt<1>("h1")), R0O_1, UInt<1>("h0")))
extmodule vendor_sram :
input clock : Clock
input R0A : UInt<10>
output R0O : UInt<8>
input clock : Clock
input W0A : UInt<10>
input W0I : UInt<8>
input W0E : UInt<1>
input W0W : UInt<1>
input W0M : UInt<1>
defname = vendor_sram
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}

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package barstools.tapeout.transforms.macros
import java.io.File
class SplitWidth2048x16_mrw extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-2048x16-mrw.json")
val lib = new File(macroDir, "lib-2048x8-mrw.json")
val v = new File(testDir, "split_width_2048x16_mrw.v")
val output =
"""
circuit name_of_sram_module :
module name_of_sram_module :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<16>
output RW0O : UInt<16>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<2>
inst mem_0_0 of vendor_sram
inst mem_0_1 of vendor_sram
mem_0_0.clock <= clock
mem_0_0.RW0A <= RW0A
node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
mem_0_0.RW0I <= bits(RW0I, 7, 0)
mem_0_0.RW0M <= bits(RW0M, 0, 0)
mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_1.clock <= clock
mem_0_1.RW0A <= RW0A
node RW0O_0_1 = bits(mem_0_1.RW0O, 7, 0)
mem_0_1.RW0I <= bits(RW0I, 15, 8)
mem_0_1.RW0M <= bits(RW0M, 1, 1)
mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
extmodule vendor_sram :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<8>
output RW0O : UInt<8>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<1>
defname = vendor_sram
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}
class SplitWidth2048x16_mrw_Uneven extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-2048x16-mrw.json")
val lib = new File(macroDir, "lib-2048x10-rw.json")
val v = new File(testDir, "split_width_2048x16_mrw_uneven.v")
val output =
"""
circuit name_of_sram_module :
module name_of_sram_module :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<16>
output RW0O : UInt<16>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<2>
inst mem_0_0 of vendor_sram
inst mem_0_1 of vendor_sram
mem_0_0.clock <= clock
mem_0_0.RW0A <= RW0A
node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
mem_0_0.RW0I <= bits(RW0I, 7, 0)
mem_0_0.RW0W <= and(and(RW0W, bits(RW0M, 0, 0)), UInt<1>("h1"))
mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_1.clock <= clock
mem_0_1.RW0A <= RW0A
node RW0O_0_1 = bits(mem_0_1.RW0O, 7, 0)
mem_0_1.RW0I <= bits(RW0I, 15, 8)
mem_0_1.RW0W <= and(and(RW0W, bits(RW0M, 1, 1)), UInt<1>("h1"))
mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
extmodule vendor_sram :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<10>
output RW0O : UInt<10>
input RW0E : UInt<1>
input RW0W : UInt<1>
defname = vendor_sram
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}
class SplitWidth2048x16_mrw_VeryUneven extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-2048x16-mrw-2.json")
val lib = new File(macroDir, "lib-2048x10-rw.json")
val v = new File(testDir, "split_width_2048x16_mrw_very_uneven.v")
val output =
"""
circuit name_of_sram_module :
module name_of_sram_module :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<16>
output RW0O : UInt<16>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<8>
inst mem_0_0 of vendor_sram
inst mem_0_1 of vendor_sram
inst mem_0_2 of vendor_sram
inst mem_0_3 of vendor_sram
inst mem_0_4 of vendor_sram
inst mem_0_5 of vendor_sram
inst mem_0_6 of vendor_sram
inst mem_0_7 of vendor_sram
mem_0_0.clock <= clock
mem_0_0.RW0A <= RW0A
node RW0O_0_0 = bits(mem_0_0.RW0O, 1, 0)
mem_0_0.RW0I <= bits(RW0I, 1, 0)
mem_0_0.RW0W <= and(and(RW0W, bits(RW0M, 0, 0)), UInt<1>("h1"))
mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_1.clock <= clock
mem_0_1.RW0A <= RW0A
node RW0O_0_1 = bits(mem_0_1.RW0O, 1, 0)
mem_0_1.RW0I <= bits(RW0I, 3, 2)
mem_0_1.RW0W <= and(and(RW0W, bits(RW0M, 1, 1)), UInt<1>("h1"))
mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_2.clock <= clock
mem_0_2.RW0A <= RW0A
node RW0O_0_2 = bits(mem_0_2.RW0O, 1, 0)
mem_0_2.RW0I <= bits(RW0I, 5, 4)
mem_0_2.RW0W <= and(and(RW0W, bits(RW0M, 2, 2)), UInt<1>("h1"))
mem_0_2.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_3.clock <= clock
mem_0_3.RW0A <= RW0A
node RW0O_0_3 = bits(mem_0_3.RW0O, 1, 0)
mem_0_3.RW0I <= bits(RW0I, 7, 6)
mem_0_3.RW0W <= and(and(RW0W, bits(RW0M, 3, 3)), UInt<1>("h1"))
mem_0_3.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_4.clock <= clock
mem_0_4.RW0A <= RW0A
node RW0O_0_4 = bits(mem_0_4.RW0O, 1, 0)
mem_0_4.RW0I <= bits(RW0I, 9, 8)
mem_0_4.RW0W <= and(and(RW0W, bits(RW0M, 4, 4)), UInt<1>("h1"))
mem_0_4.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_5.clock <= clock
mem_0_5.RW0A <= RW0A
node RW0O_0_5 = bits(mem_0_5.RW0O, 1, 0)
mem_0_5.RW0I <= bits(RW0I, 11, 10)
mem_0_5.RW0W <= and(and(RW0W, bits(RW0M, 5, 5)), UInt<1>("h1"))
mem_0_5.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_6.clock <= clock
mem_0_6.RW0A <= RW0A
node RW0O_0_6 = bits(mem_0_6.RW0O, 1, 0)
mem_0_6.RW0I <= bits(RW0I, 13, 12)
mem_0_6.RW0W <= and(and(RW0W, bits(RW0M, 6, 6)), UInt<1>("h1"))
mem_0_6.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_7.clock <= clock
mem_0_7.RW0A <= RW0A
node RW0O_0_7 = bits(mem_0_7.RW0O, 1, 0)
mem_0_7.RW0I <= bits(RW0I, 15, 14)
mem_0_7.RW0W <= and(and(RW0W, bits(RW0M, 7, 7)), UInt<1>("h1"))
mem_0_7.RW0E <= and(RW0E, UInt<1>("h1"))
node RW0O_0 = cat(RW0O_0_7, cat(RW0O_0_6, cat(RW0O_0_5, cat(RW0O_0_4, cat(RW0O_0_3, cat(RW0O_0_2, cat(RW0O_0_1, RW0O_0_0)))))))
RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
extmodule vendor_sram :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<10>
output RW0O : UInt<10>
input RW0E : UInt<1>
input RW0W : UInt<1>
defname = vendor_sram
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}
class SplitWidth2048x16_mrw_ReadEnable extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-2048x16-mrw.json")
val lib = new File(macroDir, "lib-2048x8-mrw-re.json")
val v = new File(testDir, "split_width_2048x16_mrw_read_enable.v")
val output =
"""
circuit name_of_sram_module :
module name_of_sram_module :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<16>
output RW0O : UInt<16>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<2>
inst mem_0_0 of vendor_sram
inst mem_0_1 of vendor_sram
mem_0_0.clock <= clock
mem_0_0.RW0A <= RW0A
node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
mem_0_0.RW0I <= bits(RW0I, 7, 0)
mem_0_0.RW0R <= not(and(not(RW0W), UInt<1>("h1")))
mem_0_0.RW0M <= bits(RW0M, 0, 0)
mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_1.clock <= clock
mem_0_1.RW0A <= RW0A
node RW0O_0_1 = bits(mem_0_1.RW0O, 7, 0)
mem_0_1.RW0I <= bits(RW0I, 15, 8)
mem_0_1.RW0R <= not(and(not(RW0W), UInt<1>("h1")))
mem_0_1.RW0M <= bits(RW0M, 1, 1)
mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
extmodule vendor_sram :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<8>
output RW0O : UInt<8>
input RW0E : UInt<1>
input RW0R : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<1>
defname = vendor_sram
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}
class SplitWidth2048x16_n28 extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-2048x16-mrw.json")
val lib = new File(macroDir, "lib-2048x16-n28.json")
val v = new File(testDir, "split_width_2048x16_n28.v")
val output =
"""
circuit name_of_sram_module :
module name_of_sram_module :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<16>
output RW0O : UInt<16>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<2>
inst mem_0_0 of vendor_sram_16
mem_0_0.clock <= clock
mem_0_0.RW0A <= RW0A
node RW0O_0_0 = bits(mem_0_0.RW0O, 15, 0)
mem_0_0.RW0I <= bits(RW0I, 15, 0)
mem_0_0.RW0M <= cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), bits(RW0M, 0, 0))))))))))))))))
mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
node RW0O_0 = RW0O_0_0
RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
extmodule vendor_sram_16 :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<16>
output RW0O : UInt<16>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<16>
defname = vendor_sram_16
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}
class SplitWidth2048x20_mrw_UnevenMask extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-2048x20-mrw.json")
val lib = new File(macroDir, "lib-2048x8-mrw.json")
val v = new File(testDir, "split_width_2048x20_mrw_uneven_mask.v")
val output =
"""
circuit name_of_sram_module :
module name_of_sram_module :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<20>
output RW0O : UInt<20>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<2>
inst mem_0_0 of vendor_sram
inst mem_0_1 of vendor_sram
inst mem_0_2 of vendor_sram
inst mem_0_3 of vendor_sram
mem_0_0.clock <= clock
mem_0_0.RW0A <= RW0A
node RW0O_0_0 = bits(mem_0_0.RW0O, 7, 0)
mem_0_0.RW0I <= bits(RW0I, 7, 0)
mem_0_0.RW0M <= bits(RW0M, 0, 0)
mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_1.clock <= clock
mem_0_1.RW0A <= RW0A
node RW0O_0_1 = bits(mem_0_1.RW0O, 1, 0)
mem_0_1.RW0I <= bits(RW0I, 9, 8)
mem_0_1.RW0M <= bits(RW0M, 0, 0)
mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_2.clock <= clock
mem_0_2.RW0A <= RW0A
node RW0O_0_2 = bits(mem_0_2.RW0O, 7, 0)
mem_0_2.RW0I <= bits(RW0I, 17, 10)
mem_0_2.RW0M <= bits(RW0M, 1, 1)
mem_0_2.RW0W <= and(RW0W, UInt<1>("h1"))
mem_0_2.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_3.clock <= clock
mem_0_3.RW0A <= RW0A
node RW0O_0_3 = bits(mem_0_3.RW0O, 1, 0)
mem_0_3.RW0I <= bits(RW0I, 19, 18)
mem_0_3.RW0M <= bits(RW0M, 1, 1)
mem_0_3.RW0W <= and(RW0W, UInt<1>("h1"))
mem_0_3.RW0E <= and(RW0E, UInt<1>("h1"))
node RW0O_0 = cat(RW0O_0_3, cat(RW0O_0_2, cat(RW0O_0_1, RW0O_0_0)))
RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
extmodule vendor_sram :
input clock : Clock
input RW0A : UInt<11>
input RW0I : UInt<8>
output RW0O : UInt<8>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<1>
defname = vendor_sram
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}
class SplitWidth24x52 extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-24x52-r-w.json")
val lib = new File(macroDir, "lib-32x32-2rw.json")
val v = new File(testDir, "split_width_24x52.v")
val output =
"""
circuit entries_info_ext :
module entries_info_ext :
input R0_clk : Clock
input R0_addr : UInt<5>
output R0_data : UInt<52>
input R0_en : UInt<1>
input W0_clk : Clock
input W0_addr : UInt<5>
input W0_data : UInt<52>
input W0_en : UInt<1>
inst mem_0_0 of SRAM2RW32x32
inst mem_0_1 of SRAM2RW32x32
mem_0_0.CE1 <= W0_clk
mem_0_0.A1 <= W0_addr
mem_0_0.I1 <= bits(W0_data, 31, 0)
mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), UInt<1>("h1")), UInt<1>("h1")))
mem_0_0.CSB1 <= not(and(W0_en, UInt<1>("h1")))
mem_0_1.CE1 <= W0_clk
mem_0_1.A1 <= W0_addr
mem_0_1.I1 <= bits(W0_data, 51, 32)
mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1")))
mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), UInt<1>("h1")), UInt<1>("h1")))
mem_0_1.CSB1 <= not(and(W0_en, UInt<1>("h1")))
mem_0_0.CE2 <= R0_clk
mem_0_0.A2 <= R0_addr
node R0_data_0_0 = bits(mem_0_0.O2, 31, 0)
mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
mem_0_0.CSB2 <= not(and(R0_en, UInt<1>("h1")))
mem_0_1.CE2 <= R0_clk
mem_0_1.A2 <= R0_addr
node R0_data_0_1 = bits(mem_0_1.O2, 19, 0)
mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1")))
mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
mem_0_1.CSB2 <= not(and(R0_en, UInt<1>("h1")))
node R0_data_0 = cat(R0_data_0_1, R0_data_0_0)
R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<1>("h0"))
extmodule SRAM2RW32x32 :
input CE1 : Clock
input A1 : UInt<5>
input I1 : UInt<32>
output O1 : UInt<32>
input CSB1 : UInt<1>
input OEB1 : UInt<1>
input WEB1 : UInt<1>
input CE2 : Clock
input A2 : UInt<5>
input I2 : UInt<32>
output O2 : UInt<32>
input CSB2 : UInt<1>
input OEB2 : UInt<1>
input WEB2 : UInt<1>
defname = SRAM2RW32x32
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}
class SplitWidth32x160 extends MacroCompilerSpec {
val mem = new File(macroDir, "mem-32x160-mrw.json")
val lib = new File(macroDir, "lib-32x80-mrw.json")
val v = new File(testDir, "split_width_32x160.v")
val output =
"""
circuit name_of_sram_module :
module name_of_sram_module :
input clock : Clock
input RW0A : UInt<5>
input RW0I : UInt<160>
output RW0O : UInt<160>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<8>
inst mem_0_0 of vendor_sram
inst mem_0_1 of vendor_sram
mem_0_0.clock <= clock
mem_0_0.RW0A <= RW0A
node RW0O_0_0 = bits(mem_0_0.RW0O, 79, 0)
mem_0_0.RW0I <= bits(RW0I, 79, 0)
mem_0_0.RW0M <= cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 3, 3), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 2, 2), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 1, 1), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), cat(bits(RW0M, 0, 0), bits(RW0M, 0, 0))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
mem_0_0.RW0W <= and(RW0W, UInt<1>("h1"))
mem_0_0.RW0E <= and(RW0E, UInt<1>("h1"))
mem_0_1.clock <= clock
mem_0_1.RW0A <= RW0A
node RW0O_0_1 = bits(mem_0_1.RW0O, 79, 0)
mem_0_1.RW0I <= bits(RW0I, 159, 80)
mem_0_1.RW0M <= cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 7, 7), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 6, 6), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 5, 5), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), cat(bits(RW0M, 4, 4), bits(RW0M, 4, 4))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
mem_0_1.RW0W <= and(RW0W, UInt<1>("h1"))
mem_0_1.RW0E <= and(RW0E, UInt<1>("h1"))
node RW0O_0 = cat(RW0O_0_1, RW0O_0_0)
RW0O <= mux(UInt<1>("h1"), RW0O_0, UInt<1>("h0"))
extmodule vendor_sram :
input clock : Clock
input RW0A : UInt<5>
input RW0I : UInt<80>
output RW0O : UInt<80>
input RW0E : UInt<1>
input RW0W : UInt<1>
input RW0M : UInt<80>
defname = vendor_sram
"""
compile(mem, Some(lib), v, false)
execute(Some(mem), Some(lib), false, output)
}