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Code Issues Pull Requests Actions 33 Packages Projects Releases Wiki Activity
144 Commits 8 Branches 0 Tags
1e114d03558089789b5391675dee933e2175c18a
Commit Graph
75 Commits
Author SHA1 Message Date
John WrightandColin Schmidt 82636b3ff4 Upstream MemConf and use it (with some slight tweaks) 2019-05-14 10:10:47 -07:00
Colin SchmidtandColin Schmidt c23b2b6f84 SRAM depth to bigint 
max synflop depth support
Fix annotation mangling on the harness side
 2019-05-14 10:10:47 -07:00
Colin Schmidtandedwardcwang affd033f0a Emit hammer IR from MacroCompiler (#50) 2019-03-25 22:52:39 -07:00
Abraham GonzalezandColin Schmidt 817726ff1f stop exceptions on empty conf files (#43) 
* stop exceptions on empty conf files

* emit empty verilog file | warn users

* put else's on same line as closing bracket
 2019-03-18 10:15:50 -07:00
Colin SchmidtandColin Schmidt 0b9d74ada7 Fix unit tests update cost function once more 
bump mdf to master
 2019-03-18 07:25:04 -07:00
Colin SchmidtandColin Schmidt 44e97826d4 Fix cost metric for non Compiler libs 
Also a small fix from reviewer
 2019-03-18 07:25:04 -07:00
Colin SchmidtandColin Schmidt 98a410812c Filter compiler libraries before mapping 
The filter is always by family and maskability and then by any
integral mappings.
 2019-03-18 07:25:04 -07:00
Colin SchmidtandColin Schmidt a0510e6664 Change cost to double from BigInt and fix default metric 
I don't think it was adding anything and now we can get rid of
the weird +1/-1
 2019-03-18 07:25:04 -07:00
Colin SchmidtandColin Schmidt 45278a6de0 Make SRAM per port clocks optional 
Connects to whatever clock ports are available
 2019-03-18 07:25:04 -07:00
James DunnandJohn Wright 9d505d6063 Fixed index offset in mask port mapping. (#38) 
Fixed index offset in mask port mapping.
 2019-02-13 15:17:12 -08:00
John WrightandJohn Wright 1f58ea1e14 Style/Comments from review of #35 2019-02-13 10:15:51 -08:00
John WrightandJohn Wright efd2f09b21 Naming consistency (memMode -> memFormat) 2019-02-13 10:15:51 -08:00
John WrightandJohn Wright f0c7bab3ea Use the correct 'magic values' for the port names 
Ensure backwards compatiblity by using -m for MDF input and -n for conf
input. Also fix the naming scheme for memory ports.
 2019-02-13 10:15:51 -08:00
John WrightandJohn Wright d861fdd95c Don't run DCE && Profit 2019-02-13 10:15:51 -08:00
John WrightandJohn Wright 12842cb3a7 Add MemConf and change MacroCompiler to use a conf file instead of MDF JSON 2019-02-13 10:15:51 -08:00
Paul RiggeandJohn Wright f310d45381 Refactor barstools for new versions of things. 
- No handlebars (not being published for Scala 2.12)
- Update for new annotations APIs

Bump sbt-dependency-graph to 0.9.2 for this scala version
 2019-02-13 10:15:51 -08:00
Edward Wangandedwardcwang 4727d475c7 Add options to force certain memories to lib or synflops 2019-02-06 12:40:53 -08:00
Edward Wangandedwardcwang d1c1b3fba6 Overhaul CompilerMode parsing 2019-02-06 12:40:53 -08:00
edwardcwangandGitHub 93bf7895be Fix corner case in compiling a small mem using a large lib (#32) 
* Refactor bit pairs calculation into a separate function

* Minor clarifications

* Clarify MacroCompilerSpec helpers

* Add SmallTagArrayTest test

* Fix corner case in compiling a small mem using a large lib
 2018-04-26 10:33:55 -07:00
Adam IzraelevitzandGitHub 79c8c283cc Add memory compiler to macros (#29) 
* Add memory compiler to macros

* Removed weird spacing

* Make sramcompiler width/depth range inclusive

* Added sramcompiler test
 2018-02-16 16:01:10 -08:00
edwardcwangandGitHub 8a30579a3e Support firrtl output in command line for MacroCompiler (#28) 
* Use the given port prefix (fix a bug preventing two unit tests from passing)
* Support firrtl output in addition to Verilog
 2017-12-04 15:12:42 -08:00
edwardcwangandGitHub c884a2fb15 Correct multi-ported memory compilation (#27) 
* Correct multi-ported memory compilation

It was incorrectly splitting multiple times before. Fixed the issue and
added regression tests for this issue.

* Add 1 read 1 write test
 2017-10-06 18:04:49 -07:00
Edward Wangandedwardcwang e1499fcdc0 Update command line help 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang e09f8b1b0d Fix grammar 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang bc26f5eb1a Address review comments 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang d2b105079d Not a scaladoc 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 13d8a0f8f5 Add strict mode 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 43d242707b Enable some more tests 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang af67540a81 Add test from Donggyu 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 5d3bebd2b9 Re-implement parallel mapping 
- Support byte-masked SRAM, yay
- Also nuke a bunch of bugs
 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 676b8e72ba Add rocket-chip inspired tests 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang e89079f2d7 Test for non-empty Verilog 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang f9edbfea27 Move cost metric to its own file 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang df8b5815c6 Trim redundant MDF field 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 4013b1924f Implement command line cost metric selection 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 0f4683700f Add cost function selection test 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 0203aa9e7c Move notes to main file since they apply there as well 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang a25c84f72c Specify cost function from command line 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 923a08dfa1 Fix typo 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 00c99f56b1 Add sbt-assembly for making jar 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang ffd7893d63 Implement cost selection from command line 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 0e474dac5e Add external metric 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 5d14f1995a Start cost function refactor 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 0f2d00e008 Add some documentation 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang f854c6c9f0 Nuke hardcoded JSON tests from orbit 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang a177c895e8 Finish rewriting in new format 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 513da4eb37 Support non-prefixed ports 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 85d18b736e Document 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 519ffef50a Tests aren't that brittle since firrtl reparses the output 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang e47cf92139 Move HasNoLibTestGenerator out of SynFlops 2017-10-03 11:56:30 -07:00