Support non-prefixed ports

2017-07-31 17:03:21 -07:00
parent a0e817b6fb
commit 513da4eb37
1 changed files with 1 additions and 1 deletions
--- a/macros/src/test/scala/MacroCompilerSpec.scala
+++ b/macros/src/test/scala/MacroCompilerSpec.scala
@@ -119,7 +119,7 @@ trait HasSRAMGenerator {
    write: Boolean,
    writeEnable: Boolean = false
  ): MacroPort = {
-    val realPrefix = prefix + "_"
+    val realPrefix = if (prefix == "") "" else prefix + "_"

    MacroPort(
      address=PolarizedPort(name=realPrefix + "addr", polarity=ActiveHigh),