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Nuke hardcoded JSON tests from orbit

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This commit is contained in:
Edward Wang
2017-07-31 17:04:32 -07:00
committed by edwardcwang
parent a177c895e8
commit f854c6c9f0
21 changed files with 2 additions and 819 deletions
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36
macros/src/test/resources/lib-1024x8-mrw.json
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@@ -1,36 +0,0 @@
[
{
"type": "sram",
"name": "vendor_sram",
"depth": 1024,
"width": 8,
"family": "1rw",
"ports": [
{
"clock port name": "clock",
"mask granularity": 8,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
},
{
"type": "metal filler cell",
"name": "vender_dcap"
},
{
"type": "filler cell",
"name": "vender_fill"
}
]

27
macros/src/test/resources/lib-1024x8-n28.json
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@@ -1,27 +0,0 @@
[
{
"type": "sram",
"name": "vendor_sram",
"depth": 1024,
"width": 8,
"ports": [
{
"clock port name": "clock",
"mask granularity": 1,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

34
macros/src/test/resources/lib-1024x8-r-mw.json
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@@ -1,34 +0,0 @@
[
{
"type": "sram",
"name": "vendor_sram",
"depth": 1024,
"width": 8,
"ports": [
{
"clock port name": "clock",
"mask granularity": 8,
"output port name": "R0O",
"address port name": "R0A",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"address port polarity": "active high"
},
{
"clock port name": "clock",
"mask granularity": 8,
"input port name": "W0I",
"address port name": "W0A",
"mask port name": "W0M",
"chip enable port name": "W0E",
"write enable port name": "W0W",
"clock port polarity": "positive edge",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

35
macros/src/test/resources/lib-1024x8-sleep.json
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@@ -1,35 +0,0 @@
[
{
"type": "sram",
"name": "vendor_sram",
"depth": 1024,
"width": 8,
"ports": [
{
"clock port name": "clock",
"mask granularity": 8,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
],
"extra ports": [
{
"name": "sleep",
"type": "constant",
"width": 1,
"value": 0
}
]
}
]

24
macros/src/test/resources/lib-2048x10-rw.json
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@@ -1,24 +0,0 @@
[
{
"type": "sram",
"name": "vendor_sram",
"depth": 2048,
"width": 10,
"ports": [
{
"clock port name": "clock",
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

52
macros/src/test/resources/lib-2048x16-n28.json
View File

@@ -1,52 +0,0 @@
[
{
"type": "sram",
"name": "vendor_sram_16",
"depth": 2048,
"width": 16,
"ports": [
{
"clock port name": "clock",
"mask granularity": 1,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "vendor_sram_4",
"depth": 2048,
"width": 4,
"ports": [
{
"clock port name": "clock",
"mask granularity": 1,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

29
macros/src/test/resources/lib-2048x8-mrw-re.json
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@@ -1,29 +0,0 @@
[
{
"type": "sram",
"name": "vendor_sram",
"depth": 2048,
"width": 8,
"ports": [
{
"clock port name": "clock",
"mask granularity": 8,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"read enable port name": "RW0R",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high",
"read enable port polarity": "active low"
}
]
}
]

27
macros/src/test/resources/lib-2048x8-mrw.json
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@@ -1,27 +0,0 @@
[
{
"type": "sram",
"name": "vendor_sram",
"depth": 2048,
"width": 8,
"ports": [
{
"clock port name": "clock",
"mask granularity": 8,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

43
macros/src/test/resources/lib-32x32-2rw.json
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@@ -1,43 +0,0 @@
[
{
"name": "SRAM2RW32x32",
"type": "sram",
"family": "2rw",
"depth": 32,
"width": 32,
"ports": [
{
"clock port name": "CE1",
"clock port polarity": "positive edge",
"address port name": "A1",
"address port polarity": "active high",
"input port name": "I1",
"input port polarity": "active high",
"output port name": "O1",
"output port polarity": "active high",
"read enable port name": "OEB1",
"read enable port polarity": "active low",
"write enable port name": "WEB1",
"write enable port polarity": "active low",
"chip enable port name": "CSB1",
"chip enable port polarity": "active low"
},
{
"clock port name": "CE2",
"clock port polarity": "positive edge",
"address port name": "A2",
"address port polarity": "active high",
"input port name": "I2",
"input port polarity": "active high",
"output port name": "O2",
"output port polarity": "active high",
"read enable port name": "OEB2",
"read enable port polarity": "active low",
"write enable port name": "WEB2",
"write enable port polarity": "active low",
"chip enable port name": "CSB2",
"chip enable port polarity": "active low"
}
]
}
]

27
macros/src/test/resources/lib-32x80-mrw.json
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@@ -1,27 +0,0 @@
[
{
"type": "sram",
"name": "vendor_sram",
"depth": 32,
"width": 80,
"ports": [
{
"clock port name": "clock",
"mask granularity": 1,
"output port name": "RW0O",
"input port name": "RW0I",
"address port name": "RW0A",
"mask port name": "RW0M",
"chip enable port name": "RW0E",
"write enable port name": "RW0W",
"clock port polarity": "positive edge",
"output port polarity": "active high",
"input port polarity": "active high",
"address port polarity": "active high",
"mask port polarity": "active high",
"chip enable port polarity": "active high",
"write enable port polarity": "active high"
}
]
}
]

27
macros/src/test/resources/mem-2000x8-mrw.json
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@@ -1,27 +0,0 @@
[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2000,
"width": 8,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 8,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

27
macros/src/test/resources/mem-2048x16-mrw-2.json
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@@ -1,27 +0,0 @@
[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2048,
"width": 16,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 2,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

27
macros/src/test/resources/mem-2048x16-mrw.json
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@@ -1,27 +0,0 @@
[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2048,
"width": 16,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 8,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

28
macros/src/test/resources/mem-2048x20-mrw.json
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@@ -1,28 +0,0 @@
[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2048,
"width": 20,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 10,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

28
macros/src/test/resources/mem-2048x8-mrw.json
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@@ -1,28 +0,0 @@
[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2048,
"width": 8,
"family": "1rw",
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 8,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

31
macros/src/test/resources/mem-2048x8-r-mw.json
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@@ -1,31 +0,0 @@
[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2048,
"width": 8,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 8,
"input port name": "W0I",
"input port polarity": "active high",
"address port name": "W0A",
"address port polarity": "active high",
"mask port name": "W0M",
"mask port polarity": "active high",
"chip enable port name": "W0E",
"chip enable port polarity": "active high"
},
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"output port name": "R0O",
"output port polarity": "active high",
"address port name": "R0A",
"address port polarity": "active high"
}
]
}
]

22
macros/src/test/resources/mem-24x52-r-w.json
View File

@@ -1,22 +0,0 @@
[
{
"type": "sram",
"name": "entries_info_ext",
"depth": 24,
"width": 52,
"ports": [
{
"clock port name": "R0_clk",
"output port name": "R0_data",
"address port name": "R0_addr",
"chip enable port name": "R0_en"
},
{
"clock port name": "W0_clk",
"input port name": "W0_data",
"address port name": "W0_addr",
"chip enable port name": "W0_en"
}
]
}
]

27
macros/src/test/resources/mem-32x160-mrw.json
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@@ -1,27 +0,0 @@
[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 32,
"width": 160,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 20,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]

186
macros/src/test/resources/mylib.json
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@@ -1,186 +0,0 @@
[
{
"type": "sram",
"name": "SRAM1RW1024x8",
"width": 8,
"depth": 1024,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW512x32",
"width": 32,
"depth": 512,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW64x128",
"width": 128,
"depth": 64,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW64x32",
"width": 32,
"depth": 64,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW64x8",
"width": 8,
"depth": 64,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM1RW512x8",
"width": 8,
"depth": 512,
"ports": [
{
"address port name": "A",
"address port polarity": "active high",
"clock port name": "CE",
"clock port polarity": "positive edge",
"write enable port name": "WEB",
"write enable port polarity": "active low",
"read enable port name": "OEB",
"read enable port polarity": "active low",
"chip enable port name": "CEB",
"chip enable port polarity": "active low",
"output port name": "O",
"output port polarity": "active high",
"input port name": "I",
"input port polarity": "active high"
}
]
},
{
"type": "sram",
"name": "SRAM2RW64x32",
"width": 32,
"depth": 64,
"ports": [
{
"address port name": "A1",
"address port polarity": "active high",
"clock port name": "CE1",
"clock port polarity": "positive edge",
"write enable port name": "WEB1",
"write enable port polarity": "active low",
"read enable port name": "OEB1",
"read enable port polarity": "active low",
"chip enable port name": "CEB1",
"chip enable port polarity": "active low",
"output port name": "O1",
"output port polarity": "active high",
"input port name": "I1",
"input port polarity": "active high"
},
{
"address port name": "A2",
"address port polarity": "active high",
"clock port name": "CE2",
"clock port polarity": "positive edge",
"write enable port name": "WEB2",
"write enable port polarity": "active low",
"read enable port name": "OEB2",
"read enable port polarity": "active low",
"chip enable port name": "CEB2",
"chip enable port polarity": "active low",
"output port name": "O2",
"output port polarity": "active high",
"input port name": "I2",
"input port polarity": "active high"
}
]
}
]

76
macros/src/test/resources/rocketchip.json
View File

@@ -1,76 +0,0 @@
[
{
"type": "sram",
"name": "tag_array_ext",
"depth": 64,
"width": 80,
"ports": [
{
"clock port name": "RW0_clk",
"mask granularity": 20,
"output port name": "RW0_rdata",
"input port name": "RW0_wdata",
"address port name": "RW0_addr",
"mask port name": "RW0_wmask",
"chip enable port name": "RW0_en",
"write enable port name": "RW0_wmode"
}
]
},
{
"type": "sram",
"name": "T_1090_ext",
"depth": 512,
"width": 64,
"ports": [
{
"clock port name": "RW0_clk",
"output port name": "RW0_rdata",
"input port name": "RW0_wdata",
"address port name": "RW0_addr",
"chip enable port name": "RW0_en",
"write enable port name": "RW0_wmode"
}
]
},
{
"type": "sram",
"name": "T_406_ext",
"depth": 512,
"width": 64,
"ports": [
{
"clock port name": "RW0_clk",
"mask granularity": 8,
"output port name": "RW0_rdata",
"input port name": "RW0_wdata",
"address port name": "RW0_addr",
"mask port name": "RW0_wmask",
"chip enable port name": "RW0_en",
"write enable port name": "RW0_wmode"
}
]
},
{
"type": "sram",
"name": "T_2172_ext",
"depth": 64,
"width": 88,
"ports": [
{
"clock port name": "W0_clk",
"mask granularity": 22,
"input port name": "W0_data",
"address port name": "W0_addr",
"chip enable port name": "W0_en",
"mask port name": "W0_mask"
},
{
"clock port name": "R0_clk",
"output port name": "R0_data",
"address port name": "R0_addr",
"chip enable port name": "R0_en"
}
]
}
]

8
macros/src/test/scala/MacroCompilerSpec.scala
View File

@@ -13,13 +13,12 @@ abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalate
* lib - technology SRAM(s) to use to compile mem
*/
val macroDir: String = "tapeout/src/test/resources/macros"
val testDir: String = "test_run_dir/macros"
new File(testDir).mkdirs // Make sure the testDir exists
// Override these to change the prefixing of macroDir and testDir
val memPrefix: String = macroDir
val libPrefix: String = macroDir
val memPrefix: String = testDir
val libPrefix: String = testDir
val vPrefix: String = testDir
private def args(mem: String, lib: Option[String], v: String, synflops: Boolean) =
@@ -198,9 +197,6 @@ trait HasSimpleTestGenerator {
require (memDepth >= libDepth)
override val memPrefix = testDir
override val libPrefix = testDir
// Convenience variables to check if a mask exists.
val memHasMask = memMaskGran != None
val libHasMask = libMaskGran != None