chipyard/macros/src/test/resources/mylib.json

[
  {
    "type": "sram",
    "name": "SRAM1RW1024x8",
    "width": 8,
    "depth": 1024,
    "ports": [
      {
        "address port name": "A",
        "address port polarity": "active high",
        "clock port name": "CE",
        "clock port polarity": "positive edge",
        "write enable port name": "WEB",
        "write enable port polarity": "active low",
        "read enable port name": "OEB",
        "read enable port polarity": "active low",
        "chip enable port name": "CEB",
        "chip enable port polarity": "active low",
        "output port name": "O",
        "output port polarity": "active high",
        "input port name": "I",
        "input port polarity": "active high"
      }
    ]
  },
  {
    "type": "sram",
    "name": "SRAM1RW512x32",
    "width": 32,
    "depth": 512,
    "ports": [
      {
        "address port name": "A",
        "address port polarity": "active high",
        "clock port name": "CE",
        "clock port polarity": "positive edge",
        "write enable port name": "WEB",
        "write enable port polarity": "active low",
        "read enable port name": "OEB",
        "read enable port polarity": "active low",
        "chip enable port name": "CEB",
        "chip enable port polarity": "active low",
        "output port name": "O",
        "output port polarity": "active high",
        "input port name": "I",
        "input port polarity": "active high"
      }
    ]
  },
  {
    "type": "sram",
    "name": "SRAM1RW64x128",
    "width": 128,
    "depth": 64,
    "ports": [
      {
        "address port name": "A",
        "address port polarity": "active high",
        "clock port name": "CE",
        "clock port polarity": "positive edge",
        "write enable port name": "WEB",
        "write enable port polarity": "active low",
        "read enable port name": "OEB",
        "read enable port polarity": "active low",
        "chip enable port name": "CEB",
        "chip enable port polarity": "active low",
        "output port name": "O",
        "output port polarity": "active high",
        "input port name": "I",
        "input port polarity": "active high"
      }
    ]
  },
  {
    "type": "sram",
    "name": "SRAM1RW64x32",
    "width": 32,
    "depth": 64,
    "ports": [
      {
        "address port name": "A",
        "address port polarity": "active high",
        "clock port name": "CE",
        "clock port polarity": "positive edge",
        "write enable port name": "WEB",
        "write enable port polarity": "active low",
        "read enable port name": "OEB",
        "read enable port polarity": "active low",
        "chip enable port name": "CEB",
        "chip enable port polarity": "active low",
        "output port name": "O",
        "output port polarity": "active high",
        "input port name": "I",
        "input port polarity": "active high"
      }
    ]
  },
  {
    "type": "sram",
    "name": "SRAM1RW64x8",
    "width": 8,
    "depth": 64,
    "ports": [
      {
        "address port name": "A",
        "address port polarity": "active high",
        "clock port name": "CE",
        "clock port polarity": "positive edge",
        "write enable port name": "WEB",
        "write enable port polarity": "active low",
        "read enable port name": "OEB",
        "read enable port polarity": "active low",
        "chip enable port name": "CEB",
        "chip enable port polarity": "active low",
        "output port name": "O",
        "output port polarity": "active high",
        "input port name": "I",
        "input port polarity": "active high"
      }
    ]
  },
  {
    "type": "sram",
    "name": "SRAM1RW512x8",
    "width": 8,
    "depth": 512,
    "ports": [
      {
        "address port name": "A",
        "address port polarity": "active high",
        "clock port name": "CE",
        "clock port polarity": "positive edge",
        "write enable port name": "WEB",
        "write enable port polarity": "active low",
        "read enable port name": "OEB",
        "read enable port polarity": "active low",
        "chip enable port name": "CEB",
        "chip enable port polarity": "active low",
        "output port name": "O",
        "output port polarity": "active high",
        "input port name": "I",
        "input port polarity": "active high"
      }
    ]
  },
  {
    "type": "sram",
    "name": "SRAM2RW64x32",
    "width": 32,
    "depth": 64,
    "ports": [
      {
        "address port name": "A1",
        "address port polarity": "active high",
        "clock port name": "CE1",
        "clock port polarity": "positive edge",
        "write enable port name": "WEB1",
        "write enable port polarity": "active low",
        "read enable port name": "OEB1",
        "read enable port polarity": "active low",
        "chip enable port name": "CEB1",
        "chip enable port polarity": "active low",
        "output port name": "O1",
        "output port polarity": "active high",
        "input port name": "I1",
        "input port polarity": "active high"
      },
      {
        "address port name": "A2",
        "address port polarity": "active high",
        "clock port name": "CE2",
        "clock port polarity": "positive edge",
        "write enable port name": "WEB2",
        "write enable port polarity": "active low",
        "read enable port name": "OEB2",
        "read enable port polarity": "active low",
        "chip enable port name": "CEB2",
        "chip enable port polarity": "active low",
        "output port name": "O2",
        "output port polarity": "active high",
        "input port name": "I2",
        "input port polarity": "active high"
      }
    ]
  }
]