77 lines
1.8 KiB
JSON
77 lines
1.8 KiB
JSON
[
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{
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"type": "sram",
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"name": "tag_array_ext",
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"depth": 64,
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"width": 80,
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"ports": [
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{
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"clock port name": "RW0_clk",
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"mask granularity": 20,
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"output port name": "RW0_rdata",
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"input port name": "RW0_wdata",
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"address port name": "RW0_addr",
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"mask port name": "RW0_wmask",
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"chip enable port name": "RW0_en",
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"write enable port name": "RW0_wmode"
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}
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]
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},
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{
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"type": "sram",
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"name": "T_1090_ext",
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"depth": 512,
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"width": 64,
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"ports": [
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{
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"clock port name": "RW0_clk",
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"output port name": "RW0_rdata",
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"input port name": "RW0_wdata",
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"address port name": "RW0_addr",
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"chip enable port name": "RW0_en",
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"write enable port name": "RW0_wmode"
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}
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]
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},
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{
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"type": "sram",
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"name": "T_406_ext",
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"depth": 512,
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"width": 64,
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"ports": [
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{
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"clock port name": "RW0_clk",
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"mask granularity": 8,
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"output port name": "RW0_rdata",
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"input port name": "RW0_wdata",
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"address port name": "RW0_addr",
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"mask port name": "RW0_wmask",
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"chip enable port name": "RW0_en",
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"write enable port name": "RW0_wmode"
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}
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]
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},
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{
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"type": "sram",
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"name": "T_2172_ext",
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"depth": 64,
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"width": 88,
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"ports": [
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{
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"clock port name": "W0_clk",
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"mask granularity": 22,
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"input port name": "W0_data",
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"address port name": "W0_addr",
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"chip enable port name": "W0_en",
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"mask port name": "W0_mask"
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},
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{
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"clock port name": "R0_clk",
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"output port name": "R0_data",
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"address port name": "R0_addr",
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"chip enable port name": "R0_en"
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}
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]
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}
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]
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