From f854c6c9f0a7816febb1bb7b08f4f5c6355e809c Mon Sep 17 00:00:00 2001 From: Edward Wang Date: Mon, 31 Jul 2017 17:04:32 -0700 Subject: [PATCH] Nuke hardcoded JSON tests from orbit --- macros/src/test/resources/lib-1024x8-mrw.json | 36 ---- macros/src/test/resources/lib-1024x8-n28.json | 27 --- .../src/test/resources/lib-1024x8-r-mw.json | 34 ---- .../src/test/resources/lib-1024x8-sleep.json | 35 ---- macros/src/test/resources/lib-2048x10-rw.json | 24 --- .../src/test/resources/lib-2048x16-n28.json | 52 ----- .../src/test/resources/lib-2048x8-mrw-re.json | 29 --- macros/src/test/resources/lib-2048x8-mrw.json | 27 --- macros/src/test/resources/lib-32x32-2rw.json | 43 ---- macros/src/test/resources/lib-32x80-mrw.json | 27 --- macros/src/test/resources/mem-2000x8-mrw.json | 27 --- .../src/test/resources/mem-2048x16-mrw-2.json | 27 --- .../src/test/resources/mem-2048x16-mrw.json | 27 --- .../src/test/resources/mem-2048x20-mrw.json | 28 --- macros/src/test/resources/mem-2048x8-mrw.json | 28 --- .../src/test/resources/mem-2048x8-r-mw.json | 31 --- macros/src/test/resources/mem-24x52-r-w.json | 22 --- macros/src/test/resources/mem-32x160-mrw.json | 27 --- macros/src/test/resources/mylib.json | 186 ------------------ macros/src/test/resources/rocketchip.json | 76 ------- macros/src/test/scala/MacroCompilerSpec.scala | 8 +- 21 files changed, 2 insertions(+), 819 deletions(-) delete mode 100644 macros/src/test/resources/lib-1024x8-mrw.json delete mode 100644 macros/src/test/resources/lib-1024x8-n28.json delete mode 100644 macros/src/test/resources/lib-1024x8-r-mw.json delete mode 100644 macros/src/test/resources/lib-1024x8-sleep.json delete mode 100644 macros/src/test/resources/lib-2048x10-rw.json delete mode 100644 macros/src/test/resources/lib-2048x16-n28.json delete mode 100644 macros/src/test/resources/lib-2048x8-mrw-re.json delete mode 100644 macros/src/test/resources/lib-2048x8-mrw.json delete mode 100644 macros/src/test/resources/lib-32x32-2rw.json delete mode 100644 macros/src/test/resources/lib-32x80-mrw.json delete mode 100644 macros/src/test/resources/mem-2000x8-mrw.json delete mode 100644 macros/src/test/resources/mem-2048x16-mrw-2.json delete mode 100644 macros/src/test/resources/mem-2048x16-mrw.json delete mode 100644 macros/src/test/resources/mem-2048x20-mrw.json delete mode 100644 macros/src/test/resources/mem-2048x8-mrw.json delete mode 100644 macros/src/test/resources/mem-2048x8-r-mw.json delete mode 100644 macros/src/test/resources/mem-24x52-r-w.json delete mode 100644 macros/src/test/resources/mem-32x160-mrw.json delete mode 100644 macros/src/test/resources/mylib.json delete mode 100644 macros/src/test/resources/rocketchip.json diff --git a/macros/src/test/resources/lib-1024x8-mrw.json b/macros/src/test/resources/lib-1024x8-mrw.json deleted file mode 100644 index e5cfa0c2..00000000 --- a/macros/src/test/resources/lib-1024x8-mrw.json +++ /dev/null @@ -1,36 +0,0 @@ -[ - { - "type": "sram", - "name": "vendor_sram", - "depth": 1024, - "width": 8, - "family": "1rw", - "ports": [ - { - "clock port name": "clock", - "mask granularity": 8, - "output port name": "RW0O", - "input port name": "RW0I", - "address port name": "RW0A", - "mask port name": "RW0M", - "chip enable port name": "RW0E", - "write enable port name": "RW0W", - "clock port polarity": "positive edge", - "output port polarity": "active high", - "input port polarity": "active high", - "address port polarity": "active high", - "mask port polarity": "active high", - "chip enable port polarity": "active high", - "write enable port polarity": "active high" - } - ] - }, - { - "type": "metal filler cell", - "name": "vender_dcap" - }, - { - "type": "filler cell", - "name": "vender_fill" - } -] diff --git a/macros/src/test/resources/lib-1024x8-n28.json b/macros/src/test/resources/lib-1024x8-n28.json deleted file mode 100644 index 7db92ecf..00000000 --- a/macros/src/test/resources/lib-1024x8-n28.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - { - "type": "sram", - "name": "vendor_sram", - "depth": 1024, - "width": 8, - "ports": [ - { - "clock port name": "clock", - "mask granularity": 1, - "output port name": "RW0O", - "input port name": "RW0I", - "address port name": "RW0A", - "mask port name": "RW0M", - "chip enable port name": "RW0E", - "write enable port name": "RW0W", - "clock port polarity": "positive edge", - "output port polarity": "active high", - "input port polarity": "active high", - "address port polarity": "active high", - "mask port polarity": "active high", - "chip enable port polarity": "active high", - "write enable port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/lib-1024x8-r-mw.json b/macros/src/test/resources/lib-1024x8-r-mw.json deleted file mode 100644 index 869468a4..00000000 --- a/macros/src/test/resources/lib-1024x8-r-mw.json +++ /dev/null @@ -1,34 +0,0 @@ -[ - { - "type": "sram", - "name": "vendor_sram", - "depth": 1024, - "width": 8, - "ports": [ - { - "clock port name": "clock", - "mask granularity": 8, - "output port name": "R0O", - "address port name": "R0A", - "clock port polarity": "positive edge", - "output port polarity": "active high", - "address port polarity": "active high" - }, - { - "clock port name": "clock", - "mask granularity": 8, - "input port name": "W0I", - "address port name": "W0A", - "mask port name": "W0M", - "chip enable port name": "W0E", - "write enable port name": "W0W", - "clock port polarity": "positive edge", - "input port polarity": "active high", - "address port polarity": "active high", - "mask port polarity": "active high", - "chip enable port polarity": "active high", - "write enable port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/lib-1024x8-sleep.json b/macros/src/test/resources/lib-1024x8-sleep.json deleted file mode 100644 index 7736590d..00000000 --- a/macros/src/test/resources/lib-1024x8-sleep.json +++ /dev/null @@ -1,35 +0,0 @@ -[ - { - "type": "sram", - "name": "vendor_sram", - "depth": 1024, - "width": 8, - "ports": [ - { - "clock port name": "clock", - "mask granularity": 8, - "output port name": "RW0O", - "input port name": "RW0I", - "address port name": "RW0A", - "mask port name": "RW0M", - "chip enable port name": "RW0E", - "write enable port name": "RW0W", - "clock port polarity": "positive edge", - "output port polarity": "active high", - "input port polarity": "active high", - "address port polarity": "active high", - "mask port polarity": "active high", - "chip enable port polarity": "active high", - "write enable port polarity": "active high" - } - ], - "extra ports": [ - { - "name": "sleep", - "type": "constant", - "width": 1, - "value": 0 - } - ] - } -] diff --git a/macros/src/test/resources/lib-2048x10-rw.json b/macros/src/test/resources/lib-2048x10-rw.json deleted file mode 100644 index 75640ae5..00000000 --- a/macros/src/test/resources/lib-2048x10-rw.json +++ /dev/null @@ -1,24 +0,0 @@ -[ - { - "type": "sram", - "name": "vendor_sram", - "depth": 2048, - "width": 10, - "ports": [ - { - "clock port name": "clock", - "output port name": "RW0O", - "input port name": "RW0I", - "address port name": "RW0A", - "chip enable port name": "RW0E", - "write enable port name": "RW0W", - "clock port polarity": "positive edge", - "output port polarity": "active high", - "input port polarity": "active high", - "address port polarity": "active high", - "chip enable port polarity": "active high", - "write enable port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/lib-2048x16-n28.json b/macros/src/test/resources/lib-2048x16-n28.json deleted file mode 100644 index 2f549a27..00000000 --- a/macros/src/test/resources/lib-2048x16-n28.json +++ /dev/null @@ -1,52 +0,0 @@ -[ - { - "type": "sram", - "name": "vendor_sram_16", - "depth": 2048, - "width": 16, - "ports": [ - { - "clock port name": "clock", - "mask granularity": 1, - "output port name": "RW0O", - "input port name": "RW0I", - "address port name": "RW0A", - "mask port name": "RW0M", - "chip enable port name": "RW0E", - "write enable port name": "RW0W", - "clock port polarity": "positive edge", - "output port polarity": "active high", - "input port polarity": "active high", - "address port polarity": "active high", - "mask port polarity": "active high", - "chip enable port polarity": "active high", - "write enable port polarity": "active high" - } - ] - }, - { - "type": "sram", - "name": "vendor_sram_4", - "depth": 2048, - "width": 4, - "ports": [ - { - "clock port name": "clock", - "mask granularity": 1, - "output port name": "RW0O", - "input port name": "RW0I", - "address port name": "RW0A", - "mask port name": "RW0M", - "chip enable port name": "RW0E", - "write enable port name": "RW0W", - "clock port polarity": "positive edge", - "output port polarity": "active high", - "input port polarity": "active high", - "address port polarity": "active high", - "mask port polarity": "active high", - "chip enable port polarity": "active high", - "write enable port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/lib-2048x8-mrw-re.json b/macros/src/test/resources/lib-2048x8-mrw-re.json deleted file mode 100644 index 5766aa78..00000000 --- a/macros/src/test/resources/lib-2048x8-mrw-re.json +++ /dev/null @@ -1,29 +0,0 @@ -[ - { - "type": "sram", - "name": "vendor_sram", - "depth": 2048, - "width": 8, - "ports": [ - { - "clock port name": "clock", - "mask granularity": 8, - "output port name": "RW0O", - "input port name": "RW0I", - "address port name": "RW0A", - "mask port name": "RW0M", - "chip enable port name": "RW0E", - "write enable port name": "RW0W", - "read enable port name": "RW0R", - "clock port polarity": "positive edge", - "output port polarity": "active high", - "input port polarity": "active high", - "address port polarity": "active high", - "mask port polarity": "active high", - "chip enable port polarity": "active high", - "write enable port polarity": "active high", - "read enable port polarity": "active low" - } - ] - } -] diff --git a/macros/src/test/resources/lib-2048x8-mrw.json b/macros/src/test/resources/lib-2048x8-mrw.json deleted file mode 100644 index 1d4ee508..00000000 --- a/macros/src/test/resources/lib-2048x8-mrw.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - { - "type": "sram", - "name": "vendor_sram", - "depth": 2048, - "width": 8, - "ports": [ - { - "clock port name": "clock", - "mask granularity": 8, - "output port name": "RW0O", - "input port name": "RW0I", - "address port name": "RW0A", - "mask port name": "RW0M", - "chip enable port name": "RW0E", - "write enable port name": "RW0W", - "clock port polarity": "positive edge", - "output port polarity": "active high", - "input port polarity": "active high", - "address port polarity": "active high", - "mask port polarity": "active high", - "chip enable port polarity": "active high", - "write enable port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/lib-32x32-2rw.json b/macros/src/test/resources/lib-32x32-2rw.json deleted file mode 100644 index f90848b2..00000000 --- a/macros/src/test/resources/lib-32x32-2rw.json +++ /dev/null @@ -1,43 +0,0 @@ -[ - { - "name": "SRAM2RW32x32", - "type": "sram", - "family": "2rw", - "depth": 32, - "width": 32, - "ports": [ - { - "clock port name": "CE1", - "clock port polarity": "positive edge", - "address port name": "A1", - "address port polarity": "active high", - "input port name": "I1", - "input port polarity": "active high", - "output port name": "O1", - "output port polarity": "active high", - "read enable port name": "OEB1", - "read enable port polarity": "active low", - "write enable port name": "WEB1", - "write enable port polarity": "active low", - "chip enable port name": "CSB1", - "chip enable port polarity": "active low" - }, - { - "clock port name": "CE2", - "clock port polarity": "positive edge", - "address port name": "A2", - "address port polarity": "active high", - "input port name": "I2", - "input port polarity": "active high", - "output port name": "O2", - "output port polarity": "active high", - "read enable port name": "OEB2", - "read enable port polarity": "active low", - "write enable port name": "WEB2", - "write enable port polarity": "active low", - "chip enable port name": "CSB2", - "chip enable port polarity": "active low" - } - ] - } -] diff --git a/macros/src/test/resources/lib-32x80-mrw.json b/macros/src/test/resources/lib-32x80-mrw.json deleted file mode 100644 index bdf0581b..00000000 --- a/macros/src/test/resources/lib-32x80-mrw.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - { - "type": "sram", - "name": "vendor_sram", - "depth": 32, - "width": 80, - "ports": [ - { - "clock port name": "clock", - "mask granularity": 1, - "output port name": "RW0O", - "input port name": "RW0I", - "address port name": "RW0A", - "mask port name": "RW0M", - "chip enable port name": "RW0E", - "write enable port name": "RW0W", - "clock port polarity": "positive edge", - "output port polarity": "active high", - "input port polarity": "active high", - "address port polarity": "active high", - "mask port polarity": "active high", - "chip enable port polarity": "active high", - "write enable port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/mem-2000x8-mrw.json b/macros/src/test/resources/mem-2000x8-mrw.json deleted file mode 100644 index cbb5887a..00000000 --- a/macros/src/test/resources/mem-2000x8-mrw.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - { - "type": "sram", - "name": "name_of_sram_module", - "depth": 2000, - "width": 8, - "ports": [ - { - "clock port name": "clock", - "clock port polarity": "positive edge", - "mask granularity": 8, - "output port name": "RW0O", - "output port polarity": "active high", - "input port name": "RW0I", - "input port polarity": "active high", - "address port name": "RW0A", - "address port polarity": "active high", - "mask port name": "RW0M", - "mask port polarity": "active high", - "chip enable port name": "RW0E", - "chip enable port polarity": "active high", - "write enable port name": "RW0W", - "write enable port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/mem-2048x16-mrw-2.json b/macros/src/test/resources/mem-2048x16-mrw-2.json deleted file mode 100644 index dcd4aa53..00000000 --- a/macros/src/test/resources/mem-2048x16-mrw-2.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - { - "type": "sram", - "name": "name_of_sram_module", - "depth": 2048, - "width": 16, - "ports": [ - { - "clock port name": "clock", - "clock port polarity": "positive edge", - "mask granularity": 2, - "output port name": "RW0O", - "output port polarity": "active high", - "input port name": "RW0I", - "input port polarity": "active high", - "address port name": "RW0A", - "address port polarity": "active high", - "mask port name": "RW0M", - "mask port polarity": "active high", - "chip enable port name": "RW0E", - "chip enable port polarity": "active high", - "write enable port name": "RW0W", - "write enable port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/mem-2048x16-mrw.json b/macros/src/test/resources/mem-2048x16-mrw.json deleted file mode 100644 index 2bf003fe..00000000 --- a/macros/src/test/resources/mem-2048x16-mrw.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - { - "type": "sram", - "name": "name_of_sram_module", - "depth": 2048, - "width": 16, - "ports": [ - { - "clock port name": "clock", - "clock port polarity": "positive edge", - "mask granularity": 8, - "output port name": "RW0O", - "output port polarity": "active high", - "input port name": "RW0I", - "input port polarity": "active high", - "address port name": "RW0A", - "address port polarity": "active high", - "mask port name": "RW0M", - "mask port polarity": "active high", - "chip enable port name": "RW0E", - "chip enable port polarity": "active high", - "write enable port name": "RW0W", - "write enable port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/mem-2048x20-mrw.json b/macros/src/test/resources/mem-2048x20-mrw.json deleted file mode 100644 index 74032506..00000000 --- a/macros/src/test/resources/mem-2048x20-mrw.json +++ /dev/null @@ -1,28 +0,0 @@ -[ - { - "type": "sram", - "name": "name_of_sram_module", - "depth": 2048, - "width": 20, - "ports": [ - { - "clock port name": "clock", - "clock port polarity": "positive edge", - "mask granularity": 10, - "output port name": "RW0O", - "output port polarity": "active high", - "input port name": "RW0I", - "input port polarity": "active high", - "address port name": "RW0A", - "address port polarity": "active high", - "mask port name": "RW0M", - "mask port polarity": "active high", - "chip enable port name": "RW0E", - "chip enable port polarity": "active high", - "write enable port name": "RW0W", - "write enable port polarity": "active high" - } - ] - } -] - diff --git a/macros/src/test/resources/mem-2048x8-mrw.json b/macros/src/test/resources/mem-2048x8-mrw.json deleted file mode 100644 index 64f6bfd7..00000000 --- a/macros/src/test/resources/mem-2048x8-mrw.json +++ /dev/null @@ -1,28 +0,0 @@ -[ - { - "type": "sram", - "name": "name_of_sram_module", - "depth": 2048, - "width": 8, - "family": "1rw", - "ports": [ - { - "clock port name": "clock", - "clock port polarity": "positive edge", - "mask granularity": 8, - "output port name": "RW0O", - "output port polarity": "active high", - "input port name": "RW0I", - "input port polarity": "active high", - "address port name": "RW0A", - "address port polarity": "active high", - "mask port name": "RW0M", - "mask port polarity": "active high", - "chip enable port name": "RW0E", - "chip enable port polarity": "active high", - "write enable port name": "RW0W", - "write enable port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/mem-2048x8-r-mw.json b/macros/src/test/resources/mem-2048x8-r-mw.json deleted file mode 100644 index e5fd13d1..00000000 --- a/macros/src/test/resources/mem-2048x8-r-mw.json +++ /dev/null @@ -1,31 +0,0 @@ -[ - { - "type": "sram", - "name": "name_of_sram_module", - "depth": 2048, - "width": 8, - "ports": [ - { - "clock port name": "clock", - "clock port polarity": "positive edge", - "mask granularity": 8, - "input port name": "W0I", - "input port polarity": "active high", - "address port name": "W0A", - "address port polarity": "active high", - "mask port name": "W0M", - "mask port polarity": "active high", - "chip enable port name": "W0E", - "chip enable port polarity": "active high" - }, - { - "clock port name": "clock", - "clock port polarity": "positive edge", - "output port name": "R0O", - "output port polarity": "active high", - "address port name": "R0A", - "address port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/mem-24x52-r-w.json b/macros/src/test/resources/mem-24x52-r-w.json deleted file mode 100644 index e4bf6630..00000000 --- a/macros/src/test/resources/mem-24x52-r-w.json +++ /dev/null @@ -1,22 +0,0 @@ -[ - { - "type": "sram", - "name": "entries_info_ext", - "depth": 24, - "width": 52, - "ports": [ - { - "clock port name": "R0_clk", - "output port name": "R0_data", - "address port name": "R0_addr", - "chip enable port name": "R0_en" - }, - { - "clock port name": "W0_clk", - "input port name": "W0_data", - "address port name": "W0_addr", - "chip enable port name": "W0_en" - } - ] - } -] diff --git a/macros/src/test/resources/mem-32x160-mrw.json b/macros/src/test/resources/mem-32x160-mrw.json deleted file mode 100644 index a01a6d6c..00000000 --- a/macros/src/test/resources/mem-32x160-mrw.json +++ /dev/null @@ -1,27 +0,0 @@ -[ - { - "type": "sram", - "name": "name_of_sram_module", - "depth": 32, - "width": 160, - "ports": [ - { - "clock port name": "clock", - "clock port polarity": "positive edge", - "mask granularity": 20, - "output port name": "RW0O", - "output port polarity": "active high", - "input port name": "RW0I", - "input port polarity": "active high", - "address port name": "RW0A", - "address port polarity": "active high", - "mask port name": "RW0M", - "mask port polarity": "active high", - "chip enable port name": "RW0E", - "chip enable port polarity": "active high", - "write enable port name": "RW0W", - "write enable port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/mylib.json b/macros/src/test/resources/mylib.json deleted file mode 100644 index de71d89b..00000000 --- a/macros/src/test/resources/mylib.json +++ /dev/null @@ -1,186 +0,0 @@ -[ - { - "type": "sram", - "name": "SRAM1RW1024x8", - "width": 8, - "depth": 1024, - "ports": [ - { - "address port name": "A", - "address port polarity": "active high", - "clock port name": "CE", - "clock port polarity": "positive edge", - "write enable port name": "WEB", - "write enable port polarity": "active low", - "read enable port name": "OEB", - "read enable port polarity": "active low", - "chip enable port name": "CEB", - "chip enable port polarity": "active low", - "output port name": "O", - "output port polarity": "active high", - "input port name": "I", - "input port polarity": "active high" - } - ] - }, - { - "type": "sram", - "name": "SRAM1RW512x32", - "width": 32, - "depth": 512, - "ports": [ - { - "address port name": "A", - "address port polarity": "active high", - "clock port name": "CE", - "clock port polarity": "positive edge", - "write enable port name": "WEB", - "write enable port polarity": "active low", - "read enable port name": "OEB", - "read enable port polarity": "active low", - "chip enable port name": "CEB", - "chip enable port polarity": "active low", - "output port name": "O", - "output port polarity": "active high", - "input port name": "I", - "input port polarity": "active high" - } - ] - }, - { - "type": "sram", - "name": "SRAM1RW64x128", - "width": 128, - "depth": 64, - "ports": [ - { - "address port name": "A", - "address port polarity": "active high", - "clock port name": "CE", - "clock port polarity": "positive edge", - "write enable port name": "WEB", - "write enable port polarity": "active low", - "read enable port name": "OEB", - "read enable port polarity": "active low", - "chip enable port name": "CEB", - "chip enable port polarity": "active low", - "output port name": "O", - "output port polarity": "active high", - "input port name": "I", - "input port polarity": "active high" - } - ] - }, - { - "type": "sram", - "name": "SRAM1RW64x32", - "width": 32, - "depth": 64, - "ports": [ - { - "address port name": "A", - "address port polarity": "active high", - "clock port name": "CE", - "clock port polarity": "positive edge", - "write enable port name": "WEB", - "write enable port polarity": "active low", - "read enable port name": "OEB", - "read enable port polarity": "active low", - "chip enable port name": "CEB", - "chip enable port polarity": "active low", - "output port name": "O", - "output port polarity": "active high", - "input port name": "I", - "input port polarity": "active high" - } - ] - }, - { - "type": "sram", - "name": "SRAM1RW64x8", - "width": 8, - "depth": 64, - "ports": [ - { - "address port name": "A", - "address port polarity": "active high", - "clock port name": "CE", - "clock port polarity": "positive edge", - "write enable port name": "WEB", - "write enable port polarity": "active low", - "read enable port name": "OEB", - "read enable port polarity": "active low", - "chip enable port name": "CEB", - "chip enable port polarity": "active low", - "output port name": "O", - "output port polarity": "active high", - "input port name": "I", - "input port polarity": "active high" - } - ] - }, - { - "type": "sram", - "name": "SRAM1RW512x8", - "width": 8, - "depth": 512, - "ports": [ - { - "address port name": "A", - "address port polarity": "active high", - "clock port name": "CE", - "clock port polarity": "positive edge", - "write enable port name": "WEB", - "write enable port polarity": "active low", - "read enable port name": "OEB", - "read enable port polarity": "active low", - "chip enable port name": "CEB", - "chip enable port polarity": "active low", - "output port name": "O", - "output port polarity": "active high", - "input port name": "I", - "input port polarity": "active high" - } - ] - }, - { - "type": "sram", - "name": "SRAM2RW64x32", - "width": 32, - "depth": 64, - "ports": [ - { - "address port name": "A1", - "address port polarity": "active high", - "clock port name": "CE1", - "clock port polarity": "positive edge", - "write enable port name": "WEB1", - "write enable port polarity": "active low", - "read enable port name": "OEB1", - "read enable port polarity": "active low", - "chip enable port name": "CEB1", - "chip enable port polarity": "active low", - "output port name": "O1", - "output port polarity": "active high", - "input port name": "I1", - "input port polarity": "active high" - }, - { - "address port name": "A2", - "address port polarity": "active high", - "clock port name": "CE2", - "clock port polarity": "positive edge", - "write enable port name": "WEB2", - "write enable port polarity": "active low", - "read enable port name": "OEB2", - "read enable port polarity": "active low", - "chip enable port name": "CEB2", - "chip enable port polarity": "active low", - "output port name": "O2", - "output port polarity": "active high", - "input port name": "I2", - "input port polarity": "active high" - } - ] - } -] diff --git a/macros/src/test/resources/rocketchip.json b/macros/src/test/resources/rocketchip.json deleted file mode 100644 index 9fe0d2c4..00000000 --- a/macros/src/test/resources/rocketchip.json +++ /dev/null @@ -1,76 +0,0 @@ -[ - { - "type": "sram", - "name": "tag_array_ext", - "depth": 64, - "width": 80, - "ports": [ - { - "clock port name": "RW0_clk", - "mask granularity": 20, - "output port name": "RW0_rdata", - "input port name": "RW0_wdata", - "address port name": "RW0_addr", - "mask port name": "RW0_wmask", - "chip enable port name": "RW0_en", - "write enable port name": "RW0_wmode" - } - ] - }, - { - "type": "sram", - "name": "T_1090_ext", - "depth": 512, - "width": 64, - "ports": [ - { - "clock port name": "RW0_clk", - "output port name": "RW0_rdata", - "input port name": "RW0_wdata", - "address port name": "RW0_addr", - "chip enable port name": "RW0_en", - "write enable port name": "RW0_wmode" - } - ] - }, - { - "type": "sram", - "name": "T_406_ext", - "depth": 512, - "width": 64, - "ports": [ - { - "clock port name": "RW0_clk", - "mask granularity": 8, - "output port name": "RW0_rdata", - "input port name": "RW0_wdata", - "address port name": "RW0_addr", - "mask port name": "RW0_wmask", - "chip enable port name": "RW0_en", - "write enable port name": "RW0_wmode" - } - ] - }, - { - "type": "sram", - "name": "T_2172_ext", - "depth": 64, - "width": 88, - "ports": [ - { - "clock port name": "W0_clk", - "mask granularity": 22, - "input port name": "W0_data", - "address port name": "W0_addr", - "chip enable port name": "W0_en", - "mask port name": "W0_mask" - }, - { - "clock port name": "R0_clk", - "output port name": "R0_data", - "address port name": "R0_addr", - "chip enable port name": "R0_en" - } - ] - } -] diff --git a/macros/src/test/scala/MacroCompilerSpec.scala b/macros/src/test/scala/MacroCompilerSpec.scala index b752f5f2..5253623c 100644 --- a/macros/src/test/scala/MacroCompilerSpec.scala +++ b/macros/src/test/scala/MacroCompilerSpec.scala @@ -13,13 +13,12 @@ abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalate * lib - technology SRAM(s) to use to compile mem */ - val macroDir: String = "tapeout/src/test/resources/macros" val testDir: String = "test_run_dir/macros" new File(testDir).mkdirs // Make sure the testDir exists // Override these to change the prefixing of macroDir and testDir - val memPrefix: String = macroDir - val libPrefix: String = macroDir + val memPrefix: String = testDir + val libPrefix: String = testDir val vPrefix: String = testDir private def args(mem: String, lib: Option[String], v: String, synflops: Boolean) = @@ -198,9 +197,6 @@ trait HasSimpleTestGenerator { require (memDepth >= libDepth) - override val memPrefix = testDir - override val libPrefix = testDir - // Convenience variables to check if a mask exists. val memHasMask = memMaskGran != None val libHasMask = libMaskGran != None