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chipyard/macros/src/test/resources/mem-2048x16-mrw.json
2017-10-03 11:56:30 -07:00

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[
{
"type": "sram",
"name": "name_of_sram_module",
"depth": 2048,
"width": 16,
"ports": [
{
"clock port name": "clock",
"clock port polarity": "positive edge",
"mask granularity": 8,
"output port name": "RW0O",
"output port polarity": "active high",
"input port name": "RW0I",
"input port polarity": "active high",
"address port name": "RW0A",
"address port polarity": "active high",
"mask port name": "RW0M",
"mask port polarity": "active high",
"chip enable port name": "RW0E",
"chip enable port polarity": "active high",
"write enable port name": "RW0W",
"write enable port polarity": "active high"
}
]
}
]