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fix: resolve OoO simulation timeout

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This commit is contained in:
abnerhexu
2026-06-27 03:38:34 +00:00
parent 502803c37f
commit a2e0126199
68 changed files with 78250 additions and 210 deletions
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3
.gitmodules vendored Normal file
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[submodule "riscv-tests"]
path = riscv-tests
url = git@github.com:riscv-software-src/riscv-tests.git

0
generated-ooo/.Core.sv.stamp Normal file
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60
generated-ooo/ALU.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module ALU(
input [4:0] io_fn,
input [63:0] io_a,
io_b,
input io_isWord,
output [63:0] io_out
);
wire [5:0] shamt = io_isWord ? {1'h0, io_b[4:0]} : io_b[5:0];
wire [126:0] _raw_T_4 = {63'h0, io_a} << shamt;
wire [63:0] _GEN = {58'h0, shamt};
wire [64:0] _raw_T_22 =
$unsigned($signed($signed({io_a[63], io_a}) / $signed({io_b[63], io_b})));
wire [63:0] raw =
io_fn == 5'h0
? io_a + io_b
: io_fn == 5'h1
? io_a - io_b
: io_fn == 5'h2
? _raw_T_4[63:0]
: io_fn == 5'h3
? {63'h0, $signed(io_a) < $signed(io_b)}
: io_fn == 5'h4
? {63'h0, io_a < io_b}
: io_fn == 5'h5
? io_a ^ io_b
: io_fn == 5'h6
? io_a >> _GEN
: io_fn == 5'h7
? $signed($signed(io_a) >>> _GEN)
: io_fn == 5'h8
? io_a | io_b
: io_fn == 5'h9
? io_a & io_b
: io_fn == 5'hA
? io_a * io_b
: io_fn == 5'hB
? ((|io_b)
? _raw_T_22[63:0]
: 64'hFFFFFFFFFFFFFFFF)
: io_fn == 5'hC
? ((|io_b)
? io_a / io_b
: 64'hFFFFFFFFFFFFFFFF)
: io_fn == 5'hD
? ((|io_b)
? $signed($signed(io_a)
% $signed(io_b))
: io_a)
: io_fn == 5'hE
? ((|io_b)
? io_a % io_b
: io_a)
: io_fn == 5'hF
? io_b
: 64'h0;
assign io_out = io_isWord ? {{32{raw[31]}}, raw[31:0]} : raw;
endmodule

21
generated-ooo/BranchUnit.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module BranchUnit(
input [2:0] io_funct3,
input [63:0] io_a,
io_b,
output io_taken
);
wire _io_taken_T_11 = io_funct3 == 3'h0 & io_a == io_b;
wire [7:0] _GEN =
{{io_a >= io_b},
{io_a < io_b},
{$signed(io_a) >= $signed(io_b)},
{$signed(io_a) < $signed(io_b)},
{_io_taken_T_11},
{_io_taken_T_11},
{io_a != io_b},
{_io_taken_T_11}};
assign io_taken = _GEN[io_funct3];
endmodule

260
generated-ooo/CSRFile.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module CSRFile(
input clock,
reset,
io_cmd_valid,
input [11:0] io_cmd_addr,
input [2:0] io_cmd_cmd,
input [63:0] io_cmd_rs1,
input [4:0] io_cmd_zimm,
input [11:0] io_readAddr,
output [63:0] io_rdata,
input io_trap,
input [63:0] io_trapPc,
io_trapCause,
output [63:0] io_satp,
io_mtvec,
io_mepc
);
reg [63:0] cycle;
reg [63:0] mstatus;
reg [63:0] mtvecReg;
reg [63:0] mepcReg;
reg [63:0] mcause;
reg [63:0] mtval;
reg [63:0] medeleg;
reg [63:0] mideleg;
reg [63:0] mie;
reg [63:0] mip;
reg [63:0] sstatus;
reg [63:0] stvec;
reg [63:0] sepc;
reg [63:0] scause;
reg [63:0] stval;
reg [63:0] sscratch;
reg [63:0] satpReg;
always @(posedge clock) begin
if (reset) begin
cycle <= 64'h0;
mstatus <= 64'h0;
mtvecReg <= 64'h0;
mepcReg <= 64'h0;
mcause <= 64'h0;
mtval <= 64'h0;
medeleg <= 64'h0;
mideleg <= 64'h0;
mie <= 64'h0;
mip <= 64'h0;
sstatus <= 64'h0;
stvec <= 64'h0;
sepc <= 64'h0;
scause <= 64'h0;
stval <= 64'h0;
sscratch <= 64'h0;
satpReg <= 64'h0;
end
else begin
automatic logic _GEN;
automatic logic _GEN_0;
automatic logic _GEN_1;
automatic logic _GEN_2;
automatic logic _GEN_3;
automatic logic _GEN_4;
automatic logic _GEN_5;
automatic logic _GEN_6 = io_cmd_addr == 12'h343;
automatic logic _GEN_7 = io_cmd_addr == 12'h344;
automatic logic _GEN_8 = io_cmd_addr == 12'h100;
automatic logic _GEN_9 = io_cmd_addr == 12'h105;
automatic logic _GEN_10 = io_cmd_addr == 12'h140;
automatic logic _GEN_11 = io_cmd_addr == 12'h141;
automatic logic _GEN_12 = io_cmd_addr == 12'h142;
automatic logic _GEN_13 = io_cmd_addr == 12'h143;
automatic logic _GEN_14 = io_cmd_addr == 12'h180;
automatic logic [63:0] _GEN_15;
automatic logic [63:0] writeOld;
automatic logic [63:0] operand;
automatic logic [63:0] _next_T_1;
automatic logic [63:0] _next_T_3;
automatic logic [3:0][63:0] _GEN_16;
automatic logic [63:0] next;
automatic logic _GEN_17;
_GEN = io_cmd_addr == 12'h300;
_GEN_0 = io_cmd_addr == 12'h302;
_GEN_1 = io_cmd_addr == 12'h303;
_GEN_2 = io_cmd_addr == 12'h304;
_GEN_3 = io_cmd_addr == 12'h305;
_GEN_4 = io_cmd_addr == 12'h341;
_GEN_5 = io_cmd_addr == 12'h342;
_GEN_15 =
io_cmd_addr == 12'h301
? 64'h800000000014112D
: _GEN_0
? medeleg
: _GEN_1
? mideleg
: _GEN_2
? mie
: _GEN_3
? mtvecReg
: _GEN_4
? mepcReg
: _GEN_5
? mcause
: _GEN_6
? mtval
: _GEN_7
? mip
: _GEN_8
? sstatus
: _GEN_9
? stvec
: _GEN_10
? sscratch
: _GEN_11
? sepc
: _GEN_12
? scause
: _GEN_13
? stval
: _GEN_14
? satpReg
: io_cmd_addr == 12'hF14
| io_cmd_addr != 12'hC00
? 64'h0
: cycle;
writeOld = _GEN ? mstatus : _GEN_15;
operand = io_cmd_cmd[2] ? {59'h0, io_cmd_zimm} : io_cmd_rs1;
_next_T_1 = writeOld | operand;
_next_T_3 = writeOld & ~operand;
_GEN_16 = {{_next_T_3}, {_next_T_1}, {operand}, {writeOld}};
next = _GEN_16[io_cmd_cmd[1:0]];
_GEN_17 = io_cmd_valid & (|io_cmd_cmd);
cycle <= cycle + 64'h1;
if (_GEN_17 & _GEN)
mstatus <= next;
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | ~_GEN_3) begin
end
else
mtvecReg <= next;
if (io_trap) begin
mepcReg <= io_trapPc;
mcause <= io_trapCause;
end
else begin
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | ~_GEN_4) begin
end
else
mepcReg <= next;
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | ~_GEN_5) begin
end
else
mcause <= next;
end
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5
| ~_GEN_6) begin
end
else
mtval <= next;
if (~_GEN_17 | _GEN | ~_GEN_0) begin
end
else begin
automatic logic [3:0][63:0] _GEN_18;
_GEN_18 = {{_next_T_3}, {_next_T_1}, {operand}, {_GEN_15}};
medeleg <= _GEN_18[io_cmd_cmd[1:0]];
end
if (~_GEN_17 | _GEN | _GEN_0 | ~_GEN_1) begin
end
else
mideleg <= next;
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | ~_GEN_2) begin
end
else
mie <= next;
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
| ~_GEN_7) begin
end
else
mip <= next;
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
| _GEN_7 | ~_GEN_8) begin
end
else
sstatus <= next;
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
| _GEN_7 | _GEN_8 | ~_GEN_9) begin
end
else
stvec <= next;
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | ~_GEN_11) begin
end
else
sepc <= next;
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | ~_GEN_12) begin
end
else
scause <= next;
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | _GEN_12 | ~_GEN_13) begin
end
else
stval <= next;
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
| _GEN_7 | _GEN_8 | _GEN_9 | ~_GEN_10) begin
end
else
sscratch <= next;
if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | _GEN_12 | _GEN_13
| ~_GEN_14) begin
end
else
satpReg <= next;
end
end // always @(posedge)
assign io_rdata =
io_readAddr == 12'h300
? mstatus
: io_readAddr == 12'h301
? 64'h800000000014112D
: io_readAddr == 12'h302
? medeleg
: io_readAddr == 12'h303
? mideleg
: io_readAddr == 12'h304
? mie
: io_readAddr == 12'h305
? mtvecReg
: io_readAddr == 12'h341
? mepcReg
: io_readAddr == 12'h342
? mcause
: io_readAddr == 12'h343
? mtval
: io_readAddr == 12'h344
? mip
: io_readAddr == 12'h100
? sstatus
: io_readAddr == 12'h105
? stvec
: io_readAddr == 12'h140
? sscratch
: io_readAddr == 12'h141
? sepc
: io_readAddr == 12'h142
? scause
: io_readAddr == 12'h143
? stval
: io_readAddr == 12'h180
? satpReg
: io_readAddr == 12'hF14
| io_readAddr != 12'hC00
? 64'h0
: cycle;
assign io_satp = satpReg;
assign io_mtvec = mtvecReg;
assign io_mepc = mepcReg;
endmodule

83
generated-ooo/CommitStage.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module CommitStage(
input io_robValid_0,
io_robValid_1,
input [4:0] io_robEntry_0_archDest,
input io_robEntry_0_writesDest,
input [3:0] io_robEntry_0_opClass,
input [5:0] io_robEntry_0_dest,
io_robEntry_0_oldDest,
input io_robEntry_0_exception,
input [63:0] io_robEntry_0_exceptionCause,
io_robEntry_0_badAddr,
input io_robEntry_0_branchMispredict,
input [63:0] io_robEntry_0_redirectPc,
input io_robEntry_0_csrValid,
input [4:0] io_robEntry_1_archDest,
input io_robEntry_1_writesDest,
input [5:0] io_robEntry_1_dest,
io_robEntry_1_oldDest,
input io_robEntry_1_exception,
input [63:0] io_robEntry_1_exceptionCause,
io_robEntry_1_badAddr,
input io_robEntry_1_branchMispredict,
input [63:0] io_robEntry_1_redirectPc,
input io_robEntry_1_csrValid,
output io_commitReady_0,
io_commitReady_1,
io_freeOldPhys_0,
io_freeOldPhys_1,
output [5:0] io_oldPhys_0,
io_oldPhys_1,
output io_commitMapValid_0,
io_commitMapValid_1,
output [4:0] io_commitArch_0,
io_commitArch_1,
output [5:0] io_commitPhys_0,
io_commitPhys_1,
output io_flush,
output [63:0] io_redirectPc,
output io_exception,
output [63:0] io_exceptionCause,
io_badAddr
);
wire firstTrap =
io_robValid_0 & (io_robEntry_0_exception | io_robEntry_0_branchMispredict);
wire secondTrap =
io_robValid_1 & (io_robEntry_1_exception | io_robEntry_1_branchMispredict);
wire io_commitReady_1_0 =
io_robValid_1 & ~firstTrap & ~secondTrap
& ~(io_robValid_0 & io_robValid_1 & io_robEntry_0_csrValid & io_robEntry_1_csrValid)
& ~(io_robValid_0 & io_robEntry_0_opClass == 4'h4);
wire _io_commitMapValid_0_T = io_robValid_0 & io_robEntry_0_writesDest;
wire _io_commitMapValid_1_T = io_commitReady_1_0 & io_robEntry_1_writesDest;
wire secondTrapSelected = ~io_robValid_0 & secondTrap;
assign io_commitReady_0 = io_robValid_0;
assign io_commitReady_1 = io_commitReady_1_0;
assign io_freeOldPhys_0 =
_io_commitMapValid_0_T & io_robEntry_0_oldDest != io_robEntry_0_dest;
assign io_freeOldPhys_1 =
_io_commitMapValid_1_T & io_robEntry_1_oldDest != io_robEntry_1_dest;
assign io_oldPhys_0 = io_robEntry_0_oldDest;
assign io_oldPhys_1 = io_robEntry_1_oldDest;
assign io_commitMapValid_0 = _io_commitMapValid_0_T & (|io_robEntry_0_archDest);
assign io_commitMapValid_1 = _io_commitMapValid_1_T & (|io_robEntry_1_archDest);
assign io_commitArch_0 = io_robEntry_0_archDest;
assign io_commitArch_1 = io_robEntry_1_archDest;
assign io_commitPhys_0 = io_robEntry_0_dest;
assign io_commitPhys_1 = io_robEntry_1_dest;
assign io_flush = firstTrap | secondTrapSelected;
assign io_redirectPc = firstTrap ? io_robEntry_0_redirectPc : io_robEntry_1_redirectPc;
assign io_exception =
firstTrap ? io_robEntry_0_exception : secondTrapSelected & io_robEntry_1_exception;
assign io_exceptionCause =
firstTrap
? io_robEntry_0_exceptionCause
: secondTrapSelected ? io_robEntry_1_exceptionCause : 64'h0;
assign io_badAddr =
firstTrap
? io_robEntry_0_badAddr
: secondTrapSelected ? io_robEntry_1_badAddr : 64'h0;
endmodule

254
generated-ooo/Core.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module Core(
input clock,
reset,
output io_imem_req_valid,
output [63:0] io_imem_req_bits,
input io_imem_resp_valid,
input [31:0] io_imem_resp_bits_0,
io_imem_resp_bits_1,
output io_dmem_req_valid,
output [63:0] io_dmem_req_bits_addr,
io_dmem_req_bits_data,
output io_dmem_req_bits_isStore,
output [2:0] io_dmem_req_bits_size,
input io_dmem_resp_valid,
input [63:0] io_dmem_resp_bits
);
wire _backend_io_decodeReady;
wire _backend_io_flush;
wire [63:0] _backend_io_redirectPc;
wire _id_io_outValid_0;
wire _id_io_outValid_1;
wire [63:0] _id_io_out_0_pc;
wire [31:0] _id_io_out_0_inst;
wire [4:0] _id_io_out_0_rs1;
wire [4:0] _id_io_out_0_rs2;
wire [4:0] _id_io_out_0_rd;
wire [2:0] _id_io_out_0_funct3;
wire [63:0] _id_io_out_0_immI;
wire [63:0] _id_io_out_0_immS;
wire [63:0] _id_io_out_0_immB;
wire [63:0] _id_io_out_0_immU;
wire [63:0] _id_io_out_0_immJ;
wire [3:0] _id_io_out_0_opClass;
wire [4:0] _id_io_out_0_aluFn;
wire [2:0] _id_io_out_0_memWidth;
wire _id_io_out_0_isLoad;
wire _id_io_out_0_isStore;
wire _id_io_out_0_isBranch;
wire _id_io_out_0_isJal;
wire _id_io_out_0_isJalr;
wire _id_io_out_0_isLui;
wire _id_io_out_0_isAuipc;
wire _id_io_out_0_isOpImm;
wire _id_io_out_0_isWord;
wire _id_io_out_0_isSystem;
wire _id_io_out_0_writesRd;
wire _id_io_out_0_illegal;
wire [63:0] _id_io_out_1_pc;
wire [31:0] _id_io_out_1_inst;
wire [4:0] _id_io_out_1_rs1;
wire [4:0] _id_io_out_1_rs2;
wire [4:0] _id_io_out_1_rd;
wire [2:0] _id_io_out_1_funct3;
wire [63:0] _id_io_out_1_immI;
wire [63:0] _id_io_out_1_immS;
wire [63:0] _id_io_out_1_immB;
wire [63:0] _id_io_out_1_immU;
wire [63:0] _id_io_out_1_immJ;
wire [3:0] _id_io_out_1_opClass;
wire [4:0] _id_io_out_1_aluFn;
wire [2:0] _id_io_out_1_memWidth;
wire _id_io_out_1_isLoad;
wire _id_io_out_1_isStore;
wire _id_io_out_1_isBranch;
wire _id_io_out_1_isJal;
wire _id_io_out_1_isJalr;
wire _id_io_out_1_isLui;
wire _id_io_out_1_isAuipc;
wire _id_io_out_1_isOpImm;
wire _id_io_out_1_isWord;
wire _id_io_out_1_isSystem;
wire _id_io_out_1_writesRd;
wire _id_io_out_1_illegal;
wire _frontend_io_outValid;
wire [63:0] _frontend_io_out_pc;
wire [31:0] _frontend_io_out_inst_0;
wire [31:0] _frontend_io_out_inst_1;
wire _frontend_io_out_laneValid_0;
wire _frontend_io_out_laneValid_1;
reg fetchValid;
reg [63:0] fetchReg_pc;
reg [31:0] fetchReg_inst_0;
reg [31:0] fetchReg_inst_1;
reg fetchReg_laneValid_0;
reg fetchReg_laneValid_1;
wire fetchReady = ~fetchValid | _backend_io_decodeReady;
always @(posedge clock) begin
if (reset)
fetchValid <= 1'h0;
else
fetchValid <=
~_backend_io_flush & (fetchReady ? _frontend_io_outValid : fetchValid);
if (_backend_io_flush | ~fetchReady) begin
end
else begin
fetchReg_pc <= _frontend_io_out_pc;
fetchReg_inst_0 <= _frontend_io_out_inst_0;
fetchReg_inst_1 <= _frontend_io_out_inst_1;
fetchReg_laneValid_0 <= _frontend_io_out_laneValid_0;
fetchReg_laneValid_1 <= _frontend_io_out_laneValid_1;
end
end // always @(posedge)
Frontend frontend (
.clock (clock),
.reset (reset),
.io_redirectValid (_backend_io_flush),
.io_redirectPc (_backend_io_redirectPc),
.io_imemReqValid (io_imem_req_valid),
.io_imemReqAddr (io_imem_req_bits),
.io_imemRespValid (io_imem_resp_valid),
.io_imemRespBits_0 (io_imem_resp_bits_0),
.io_imemRespBits_1 (io_imem_resp_bits_1),
.io_outReady (fetchReady),
.io_outValid (_frontend_io_outValid),
.io_out_pc (_frontend_io_out_pc),
.io_out_inst_0 (_frontend_io_out_inst_0),
.io_out_inst_1 (_frontend_io_out_inst_1),
.io_out_laneValid_0 (_frontend_io_out_laneValid_0),
.io_out_laneValid_1 (_frontend_io_out_laneValid_1)
);
IDStage id (
.io_inValid (fetchValid),
.io_in_pc (fetchReg_pc),
.io_in_inst_0 (fetchReg_inst_0),
.io_in_inst_1 (fetchReg_inst_1),
.io_in_laneValid_0 (fetchReg_laneValid_0),
.io_in_laneValid_1 (fetchReg_laneValid_1),
.io_outValid_0 (_id_io_outValid_0),
.io_outValid_1 (_id_io_outValid_1),
.io_out_0_pc (_id_io_out_0_pc),
.io_out_0_inst (_id_io_out_0_inst),
.io_out_0_rs1 (_id_io_out_0_rs1),
.io_out_0_rs2 (_id_io_out_0_rs2),
.io_out_0_rd (_id_io_out_0_rd),
.io_out_0_funct3 (_id_io_out_0_funct3),
.io_out_0_immI (_id_io_out_0_immI),
.io_out_0_immS (_id_io_out_0_immS),
.io_out_0_immB (_id_io_out_0_immB),
.io_out_0_immU (_id_io_out_0_immU),
.io_out_0_immJ (_id_io_out_0_immJ),
.io_out_0_opClass (_id_io_out_0_opClass),
.io_out_0_aluFn (_id_io_out_0_aluFn),
.io_out_0_memWidth (_id_io_out_0_memWidth),
.io_out_0_isLoad (_id_io_out_0_isLoad),
.io_out_0_isStore (_id_io_out_0_isStore),
.io_out_0_isBranch (_id_io_out_0_isBranch),
.io_out_0_isJal (_id_io_out_0_isJal),
.io_out_0_isJalr (_id_io_out_0_isJalr),
.io_out_0_isLui (_id_io_out_0_isLui),
.io_out_0_isAuipc (_id_io_out_0_isAuipc),
.io_out_0_isOpImm (_id_io_out_0_isOpImm),
.io_out_0_isWord (_id_io_out_0_isWord),
.io_out_0_isSystem (_id_io_out_0_isSystem),
.io_out_0_writesRd (_id_io_out_0_writesRd),
.io_out_0_illegal (_id_io_out_0_illegal),
.io_out_1_pc (_id_io_out_1_pc),
.io_out_1_inst (_id_io_out_1_inst),
.io_out_1_rs1 (_id_io_out_1_rs1),
.io_out_1_rs2 (_id_io_out_1_rs2),
.io_out_1_rd (_id_io_out_1_rd),
.io_out_1_funct3 (_id_io_out_1_funct3),
.io_out_1_immI (_id_io_out_1_immI),
.io_out_1_immS (_id_io_out_1_immS),
.io_out_1_immB (_id_io_out_1_immB),
.io_out_1_immU (_id_io_out_1_immU),
.io_out_1_immJ (_id_io_out_1_immJ),
.io_out_1_opClass (_id_io_out_1_opClass),
.io_out_1_aluFn (_id_io_out_1_aluFn),
.io_out_1_memWidth (_id_io_out_1_memWidth),
.io_out_1_isLoad (_id_io_out_1_isLoad),
.io_out_1_isStore (_id_io_out_1_isStore),
.io_out_1_isBranch (_id_io_out_1_isBranch),
.io_out_1_isJal (_id_io_out_1_isJal),
.io_out_1_isJalr (_id_io_out_1_isJalr),
.io_out_1_isLui (_id_io_out_1_isLui),
.io_out_1_isAuipc (_id_io_out_1_isAuipc),
.io_out_1_isOpImm (_id_io_out_1_isOpImm),
.io_out_1_isWord (_id_io_out_1_isWord),
.io_out_1_isSystem (_id_io_out_1_isSystem),
.io_out_1_writesRd (_id_io_out_1_writesRd),
.io_out_1_illegal (_id_io_out_1_illegal)
);
OoOBackend backend (
.clock (clock),
.reset (reset),
.io_decodeValid_0 (_id_io_outValid_0),
.io_decodeValid_1 (_id_io_outValid_1),
.io_decode_0_pc (_id_io_out_0_pc),
.io_decode_0_inst (_id_io_out_0_inst),
.io_decode_0_rs1 (_id_io_out_0_rs1),
.io_decode_0_rs2 (_id_io_out_0_rs2),
.io_decode_0_rd (_id_io_out_0_rd),
.io_decode_0_funct3 (_id_io_out_0_funct3),
.io_decode_0_immI (_id_io_out_0_immI),
.io_decode_0_immS (_id_io_out_0_immS),
.io_decode_0_immB (_id_io_out_0_immB),
.io_decode_0_immU (_id_io_out_0_immU),
.io_decode_0_immJ (_id_io_out_0_immJ),
.io_decode_0_opClass (_id_io_out_0_opClass),
.io_decode_0_aluFn (_id_io_out_0_aluFn),
.io_decode_0_memWidth (_id_io_out_0_memWidth),
.io_decode_0_isLoad (_id_io_out_0_isLoad),
.io_decode_0_isStore (_id_io_out_0_isStore),
.io_decode_0_isBranch (_id_io_out_0_isBranch),
.io_decode_0_isJal (_id_io_out_0_isJal),
.io_decode_0_isJalr (_id_io_out_0_isJalr),
.io_decode_0_isLui (_id_io_out_0_isLui),
.io_decode_0_isAuipc (_id_io_out_0_isAuipc),
.io_decode_0_isOpImm (_id_io_out_0_isOpImm),
.io_decode_0_isWord (_id_io_out_0_isWord),
.io_decode_0_isSystem (_id_io_out_0_isSystem),
.io_decode_0_writesRd (_id_io_out_0_writesRd),
.io_decode_0_illegal (_id_io_out_0_illegal),
.io_decode_1_pc (_id_io_out_1_pc),
.io_decode_1_inst (_id_io_out_1_inst),
.io_decode_1_rs1 (_id_io_out_1_rs1),
.io_decode_1_rs2 (_id_io_out_1_rs2),
.io_decode_1_rd (_id_io_out_1_rd),
.io_decode_1_funct3 (_id_io_out_1_funct3),
.io_decode_1_immI (_id_io_out_1_immI),
.io_decode_1_immS (_id_io_out_1_immS),
.io_decode_1_immB (_id_io_out_1_immB),
.io_decode_1_immU (_id_io_out_1_immU),
.io_decode_1_immJ (_id_io_out_1_immJ),
.io_decode_1_opClass (_id_io_out_1_opClass),
.io_decode_1_aluFn (_id_io_out_1_aluFn),
.io_decode_1_memWidth (_id_io_out_1_memWidth),
.io_decode_1_isLoad (_id_io_out_1_isLoad),
.io_decode_1_isStore (_id_io_out_1_isStore),
.io_decode_1_isBranch (_id_io_out_1_isBranch),
.io_decode_1_isJal (_id_io_out_1_isJal),
.io_decode_1_isJalr (_id_io_out_1_isJalr),
.io_decode_1_isLui (_id_io_out_1_isLui),
.io_decode_1_isAuipc (_id_io_out_1_isAuipc),
.io_decode_1_isOpImm (_id_io_out_1_isOpImm),
.io_decode_1_isWord (_id_io_out_1_isWord),
.io_decode_1_isSystem (_id_io_out_1_isSystem),
.io_decode_1_writesRd (_id_io_out_1_writesRd),
.io_decode_1_illegal (_id_io_out_1_illegal),
.io_decodeReady (_backend_io_decodeReady),
.io_flush (_backend_io_flush),
.io_redirectPc (_backend_io_redirectPc),
.io_dmemReqValid (io_dmem_req_valid),
.io_dmemReq_addr (io_dmem_req_bits_addr),
.io_dmemReq_data (io_dmem_req_bits_data),
.io_dmemReq_isStore (io_dmem_req_bits_isStore),
.io_dmemReq_size (io_dmem_req_bits_size),
.io_dmemRespValid (io_dmem_resp_valid),
.io_dmemRespData (io_dmem_resp_bits)
);
endmodule

4352
generated-ooo/DCache.sv Normal file
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636
generated-ooo/DTLB.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module DTLB(
input clock,
reset,
io_req_valid,
input [63:0] io_req_vaddr,
input io_req_isStore,
output io_resp_hit,
io_resp_miss,
output [63:0] io_resp_paddr,
output io_resp_pageFault,
input io_refill_valid,
input [26:0] io_refill_vpn,
input [43:0] io_refill_ppn,
input [7:0] io_refill_flags
);
reg valid_0;
reg valid_1;
reg valid_2;
reg valid_3;
reg valid_4;
reg valid_5;
reg valid_6;
reg valid_7;
reg valid_8;
reg valid_9;
reg valid_10;
reg valid_11;
reg valid_12;
reg valid_13;
reg valid_14;
reg valid_15;
reg valid_16;
reg valid_17;
reg valid_18;
reg valid_19;
reg valid_20;
reg valid_21;
reg valid_22;
reg valid_23;
reg valid_24;
reg valid_25;
reg valid_26;
reg valid_27;
reg valid_28;
reg valid_29;
reg valid_30;
reg valid_31;
reg [26:0] vpn_0;
reg [26:0] vpn_1;
reg [26:0] vpn_2;
reg [26:0] vpn_3;
reg [26:0] vpn_4;
reg [26:0] vpn_5;
reg [26:0] vpn_6;
reg [26:0] vpn_7;
reg [26:0] vpn_8;
reg [26:0] vpn_9;
reg [26:0] vpn_10;
reg [26:0] vpn_11;
reg [26:0] vpn_12;
reg [26:0] vpn_13;
reg [26:0] vpn_14;
reg [26:0] vpn_15;
reg [26:0] vpn_16;
reg [26:0] vpn_17;
reg [26:0] vpn_18;
reg [26:0] vpn_19;
reg [26:0] vpn_20;
reg [26:0] vpn_21;
reg [26:0] vpn_22;
reg [26:0] vpn_23;
reg [26:0] vpn_24;
reg [26:0] vpn_25;
reg [26:0] vpn_26;
reg [26:0] vpn_27;
reg [26:0] vpn_28;
reg [26:0] vpn_29;
reg [26:0] vpn_30;
reg [26:0] vpn_31;
reg [43:0] ppn_0;
reg [43:0] ppn_1;
reg [43:0] ppn_2;
reg [43:0] ppn_3;
reg [43:0] ppn_4;
reg [43:0] ppn_5;
reg [43:0] ppn_6;
reg [43:0] ppn_7;
reg [43:0] ppn_8;
reg [43:0] ppn_9;
reg [43:0] ppn_10;
reg [43:0] ppn_11;
reg [43:0] ppn_12;
reg [43:0] ppn_13;
reg [43:0] ppn_14;
reg [43:0] ppn_15;
reg [43:0] ppn_16;
reg [43:0] ppn_17;
reg [43:0] ppn_18;
reg [43:0] ppn_19;
reg [43:0] ppn_20;
reg [43:0] ppn_21;
reg [43:0] ppn_22;
reg [43:0] ppn_23;
reg [43:0] ppn_24;
reg [43:0] ppn_25;
reg [43:0] ppn_26;
reg [43:0] ppn_27;
reg [43:0] ppn_28;
reg [43:0] ppn_29;
reg [43:0] ppn_30;
reg [43:0] ppn_31;
reg [7:0] flags_0;
reg [7:0] flags_1;
reg [7:0] flags_2;
reg [7:0] flags_3;
reg [7:0] flags_4;
reg [7:0] flags_5;
reg [7:0] flags_6;
reg [7:0] flags_7;
reg [7:0] flags_8;
reg [7:0] flags_9;
reg [7:0] flags_10;
reg [7:0] flags_11;
reg [7:0] flags_12;
reg [7:0] flags_13;
reg [7:0] flags_14;
reg [7:0] flags_15;
reg [7:0] flags_16;
reg [7:0] flags_17;
reg [7:0] flags_18;
reg [7:0] flags_19;
reg [7:0] flags_20;
reg [7:0] flags_21;
reg [7:0] flags_22;
reg [7:0] flags_23;
reg [7:0] flags_24;
reg [7:0] flags_25;
reg [7:0] flags_26;
reg [7:0] flags_27;
reg [7:0] flags_28;
reg [7:0] flags_29;
reg [7:0] flags_30;
reg [7:0] flags_31;
reg [4:0] repl;
wire hitVec_1 = valid_1 & vpn_1 == io_req_vaddr[38:12];
wire hitVec_2 = valid_2 & vpn_2 == io_req_vaddr[38:12];
wire hitVec_3 = valid_3 & vpn_3 == io_req_vaddr[38:12];
wire hitVec_4 = valid_4 & vpn_4 == io_req_vaddr[38:12];
wire hitVec_5 = valid_5 & vpn_5 == io_req_vaddr[38:12];
wire hitVec_6 = valid_6 & vpn_6 == io_req_vaddr[38:12];
wire hitVec_7 = valid_7 & vpn_7 == io_req_vaddr[38:12];
wire hitVec_8 = valid_8 & vpn_8 == io_req_vaddr[38:12];
wire hitVec_9 = valid_9 & vpn_9 == io_req_vaddr[38:12];
wire hitVec_10 = valid_10 & vpn_10 == io_req_vaddr[38:12];
wire hitVec_11 = valid_11 & vpn_11 == io_req_vaddr[38:12];
wire hitVec_12 = valid_12 & vpn_12 == io_req_vaddr[38:12];
wire hitVec_13 = valid_13 & vpn_13 == io_req_vaddr[38:12];
wire hitVec_14 = valid_14 & vpn_14 == io_req_vaddr[38:12];
wire hitVec_15 = valid_15 & vpn_15 == io_req_vaddr[38:12];
wire hitVec_16 = valid_16 & vpn_16 == io_req_vaddr[38:12];
wire hitVec_17 = valid_17 & vpn_17 == io_req_vaddr[38:12];
wire hitVec_18 = valid_18 & vpn_18 == io_req_vaddr[38:12];
wire hitVec_19 = valid_19 & vpn_19 == io_req_vaddr[38:12];
wire hitVec_20 = valid_20 & vpn_20 == io_req_vaddr[38:12];
wire hitVec_21 = valid_21 & vpn_21 == io_req_vaddr[38:12];
wire hitVec_22 = valid_22 & vpn_22 == io_req_vaddr[38:12];
wire hitVec_23 = valid_23 & vpn_23 == io_req_vaddr[38:12];
wire hitVec_24 = valid_24 & vpn_24 == io_req_vaddr[38:12];
wire hitVec_25 = valid_25 & vpn_25 == io_req_vaddr[38:12];
wire hitVec_26 = valid_26 & vpn_26 == io_req_vaddr[38:12];
wire hitVec_27 = valid_27 & vpn_27 == io_req_vaddr[38:12];
wire hitVec_28 = valid_28 & vpn_28 == io_req_vaddr[38:12];
wire hitVec_29 = valid_29 & vpn_29 == io_req_vaddr[38:12];
wire hitVec_30 = valid_30 & vpn_30 == io_req_vaddr[38:12];
wire hitVec_31 = valid_31 & vpn_31 == io_req_vaddr[38:12];
wire hit =
io_req_valid
& (|{hitVec_31,
hitVec_30,
hitVec_29,
hitVec_28,
hitVec_27,
hitVec_26,
hitVec_25,
hitVec_24,
hitVec_23,
hitVec_22,
hitVec_21,
hitVec_20,
hitVec_19,
hitVec_18,
hitVec_17,
hitVec_16,
hitVec_15,
hitVec_14,
hitVec_13,
hitVec_12,
hitVec_11,
hitVec_10,
hitVec_9,
hitVec_8,
hitVec_7,
hitVec_6,
hitVec_5,
hitVec_4,
hitVec_3,
hitVec_2,
hitVec_1,
valid_0 & vpn_0 == io_req_vaddr[38:12]});
wire [14:0] _hitIdx_T_2 =
{hitVec_31,
hitVec_30,
hitVec_29,
hitVec_28,
hitVec_27,
hitVec_26,
hitVec_25,
hitVec_24,
hitVec_23,
hitVec_22,
hitVec_21,
hitVec_20,
hitVec_19,
hitVec_18,
hitVec_17}
| {hitVec_15,
hitVec_14,
hitVec_13,
hitVec_12,
hitVec_11,
hitVec_10,
hitVec_9,
hitVec_8,
hitVec_7,
hitVec_6,
hitVec_5,
hitVec_4,
hitVec_3,
hitVec_2,
hitVec_1};
wire [6:0] _hitIdx_T_4 = _hitIdx_T_2[14:8] | _hitIdx_T_2[6:0];
wire [2:0] _hitIdx_T_6 = _hitIdx_T_4[6:4] | _hitIdx_T_4[2:0];
wire [4:0] hitIdx =
{|{hitVec_31,
hitVec_30,
hitVec_29,
hitVec_28,
hitVec_27,
hitVec_26,
hitVec_25,
hitVec_24,
hitVec_23,
hitVec_22,
hitVec_21,
hitVec_20,
hitVec_19,
hitVec_18,
hitVec_17,
hitVec_16},
|(_hitIdx_T_2[14:7]),
|(_hitIdx_T_4[6:3]),
|(_hitIdx_T_6[2:1]),
_hitIdx_T_6[2] | _hitIdx_T_6[0]};
wire [31:0][7:0] _GEN =
{{flags_31},
{flags_30},
{flags_29},
{flags_28},
{flags_27},
{flags_26},
{flags_25},
{flags_24},
{flags_23},
{flags_22},
{flags_21},
{flags_20},
{flags_19},
{flags_18},
{flags_17},
{flags_16},
{flags_15},
{flags_14},
{flags_13},
{flags_12},
{flags_11},
{flags_10},
{flags_9},
{flags_8},
{flags_7},
{flags_6},
{flags_5},
{flags_4},
{flags_3},
{flags_2},
{flags_1},
{flags_0}};
wire pageFault =
hit & (io_req_isStore ? ~(_GEN[hitIdx][2]) : ~(_GEN[hitIdx][1]));
wire [31:0][43:0] _GEN_0 =
{{ppn_31},
{ppn_30},
{ppn_29},
{ppn_28},
{ppn_27},
{ppn_26},
{ppn_25},
{ppn_24},
{ppn_23},
{ppn_22},
{ppn_21},
{ppn_20},
{ppn_19},
{ppn_18},
{ppn_17},
{ppn_16},
{ppn_15},
{ppn_14},
{ppn_13},
{ppn_12},
{ppn_11},
{ppn_10},
{ppn_9},
{ppn_8},
{ppn_7},
{ppn_6},
{ppn_5},
{ppn_4},
{ppn_3},
{ppn_2},
{ppn_1},
{ppn_0}};
always @(posedge clock) begin
automatic logic _GEN_1;
automatic logic _GEN_2;
automatic logic _GEN_3;
automatic logic _GEN_4;
automatic logic _GEN_5;
automatic logic _GEN_6;
automatic logic _GEN_7;
automatic logic _GEN_8;
automatic logic _GEN_9;
automatic logic _GEN_10;
automatic logic _GEN_11;
automatic logic _GEN_12;
automatic logic _GEN_13;
automatic logic _GEN_14;
automatic logic _GEN_15;
automatic logic _GEN_16;
automatic logic _GEN_17;
automatic logic _GEN_18;
automatic logic _GEN_19;
automatic logic _GEN_20;
automatic logic _GEN_21;
automatic logic _GEN_22;
automatic logic _GEN_23;
automatic logic _GEN_24;
automatic logic _GEN_25;
automatic logic _GEN_26;
automatic logic _GEN_27;
automatic logic _GEN_28;
automatic logic _GEN_29;
automatic logic _GEN_30;
automatic logic _GEN_31;
automatic logic _GEN_32;
_GEN_1 = io_refill_valid & repl == 5'h0;
_GEN_2 = io_refill_valid & repl == 5'h1;
_GEN_3 = io_refill_valid & repl == 5'h2;
_GEN_4 = io_refill_valid & repl == 5'h3;
_GEN_5 = io_refill_valid & repl == 5'h4;
_GEN_6 = io_refill_valid & repl == 5'h5;
_GEN_7 = io_refill_valid & repl == 5'h6;
_GEN_8 = io_refill_valid & repl == 5'h7;
_GEN_9 = io_refill_valid & repl == 5'h8;
_GEN_10 = io_refill_valid & repl == 5'h9;
_GEN_11 = io_refill_valid & repl == 5'hA;
_GEN_12 = io_refill_valid & repl == 5'hB;
_GEN_13 = io_refill_valid & repl == 5'hC;
_GEN_14 = io_refill_valid & repl == 5'hD;
_GEN_15 = io_refill_valid & repl == 5'hE;
_GEN_16 = io_refill_valid & repl == 5'hF;
_GEN_17 = io_refill_valid & repl == 5'h10;
_GEN_18 = io_refill_valid & repl == 5'h11;
_GEN_19 = io_refill_valid & repl == 5'h12;
_GEN_20 = io_refill_valid & repl == 5'h13;
_GEN_21 = io_refill_valid & repl == 5'h14;
_GEN_22 = io_refill_valid & repl == 5'h15;
_GEN_23 = io_refill_valid & repl == 5'h16;
_GEN_24 = io_refill_valid & repl == 5'h17;
_GEN_25 = io_refill_valid & repl == 5'h18;
_GEN_26 = io_refill_valid & repl == 5'h19;
_GEN_27 = io_refill_valid & repl == 5'h1A;
_GEN_28 = io_refill_valid & repl == 5'h1B;
_GEN_29 = io_refill_valid & repl == 5'h1C;
_GEN_30 = io_refill_valid & repl == 5'h1D;
_GEN_31 = io_refill_valid & repl == 5'h1E;
_GEN_32 = io_refill_valid & (&repl);
if (reset) begin
valid_0 <= 1'h0;
valid_1 <= 1'h0;
valid_2 <= 1'h0;
valid_3 <= 1'h0;
valid_4 <= 1'h0;
valid_5 <= 1'h0;
valid_6 <= 1'h0;
valid_7 <= 1'h0;
valid_8 <= 1'h0;
valid_9 <= 1'h0;
valid_10 <= 1'h0;
valid_11 <= 1'h0;
valid_12 <= 1'h0;
valid_13 <= 1'h0;
valid_14 <= 1'h0;
valid_15 <= 1'h0;
valid_16 <= 1'h0;
valid_17 <= 1'h0;
valid_18 <= 1'h0;
valid_19 <= 1'h0;
valid_20 <= 1'h0;
valid_21 <= 1'h0;
valid_22 <= 1'h0;
valid_23 <= 1'h0;
valid_24 <= 1'h0;
valid_25 <= 1'h0;
valid_26 <= 1'h0;
valid_27 <= 1'h0;
valid_28 <= 1'h0;
valid_29 <= 1'h0;
valid_30 <= 1'h0;
valid_31 <= 1'h0;
repl <= 5'h0;
end
else begin
valid_0 <= _GEN_1 | valid_0;
valid_1 <= _GEN_2 | valid_1;
valid_2 <= _GEN_3 | valid_2;
valid_3 <= _GEN_4 | valid_3;
valid_4 <= _GEN_5 | valid_4;
valid_5 <= _GEN_6 | valid_5;
valid_6 <= _GEN_7 | valid_6;
valid_7 <= _GEN_8 | valid_7;
valid_8 <= _GEN_9 | valid_8;
valid_9 <= _GEN_10 | valid_9;
valid_10 <= _GEN_11 | valid_10;
valid_11 <= _GEN_12 | valid_11;
valid_12 <= _GEN_13 | valid_12;
valid_13 <= _GEN_14 | valid_13;
valid_14 <= _GEN_15 | valid_14;
valid_15 <= _GEN_16 | valid_15;
valid_16 <= _GEN_17 | valid_16;
valid_17 <= _GEN_18 | valid_17;
valid_18 <= _GEN_19 | valid_18;
valid_19 <= _GEN_20 | valid_19;
valid_20 <= _GEN_21 | valid_20;
valid_21 <= _GEN_22 | valid_21;
valid_22 <= _GEN_23 | valid_22;
valid_23 <= _GEN_24 | valid_23;
valid_24 <= _GEN_25 | valid_24;
valid_25 <= _GEN_26 | valid_25;
valid_26 <= _GEN_27 | valid_26;
valid_27 <= _GEN_28 | valid_27;
valid_28 <= _GEN_29 | valid_28;
valid_29 <= _GEN_30 | valid_29;
valid_30 <= _GEN_31 | valid_30;
valid_31 <= _GEN_32 | valid_31;
if (io_refill_valid)
repl <= repl + 5'h1;
end
if (_GEN_1) begin
vpn_0 <= io_refill_vpn;
ppn_0 <= io_refill_ppn;
flags_0 <= io_refill_flags;
end
if (_GEN_2) begin
vpn_1 <= io_refill_vpn;
ppn_1 <= io_refill_ppn;
flags_1 <= io_refill_flags;
end
if (_GEN_3) begin
vpn_2 <= io_refill_vpn;
ppn_2 <= io_refill_ppn;
flags_2 <= io_refill_flags;
end
if (_GEN_4) begin
vpn_3 <= io_refill_vpn;
ppn_3 <= io_refill_ppn;
flags_3 <= io_refill_flags;
end
if (_GEN_5) begin
vpn_4 <= io_refill_vpn;
ppn_4 <= io_refill_ppn;
flags_4 <= io_refill_flags;
end
if (_GEN_6) begin
vpn_5 <= io_refill_vpn;
ppn_5 <= io_refill_ppn;
flags_5 <= io_refill_flags;
end
if (_GEN_7) begin
vpn_6 <= io_refill_vpn;
ppn_6 <= io_refill_ppn;
flags_6 <= io_refill_flags;
end
if (_GEN_8) begin
vpn_7 <= io_refill_vpn;
ppn_7 <= io_refill_ppn;
flags_7 <= io_refill_flags;
end
if (_GEN_9) begin
vpn_8 <= io_refill_vpn;
ppn_8 <= io_refill_ppn;
flags_8 <= io_refill_flags;
end
if (_GEN_10) begin
vpn_9 <= io_refill_vpn;
ppn_9 <= io_refill_ppn;
flags_9 <= io_refill_flags;
end
if (_GEN_11) begin
vpn_10 <= io_refill_vpn;
ppn_10 <= io_refill_ppn;
flags_10 <= io_refill_flags;
end
if (_GEN_12) begin
vpn_11 <= io_refill_vpn;
ppn_11 <= io_refill_ppn;
flags_11 <= io_refill_flags;
end
if (_GEN_13) begin
vpn_12 <= io_refill_vpn;
ppn_12 <= io_refill_ppn;
flags_12 <= io_refill_flags;
end
if (_GEN_14) begin
vpn_13 <= io_refill_vpn;
ppn_13 <= io_refill_ppn;
flags_13 <= io_refill_flags;
end
if (_GEN_15) begin
vpn_14 <= io_refill_vpn;
ppn_14 <= io_refill_ppn;
flags_14 <= io_refill_flags;
end
if (_GEN_16) begin
vpn_15 <= io_refill_vpn;
ppn_15 <= io_refill_ppn;
flags_15 <= io_refill_flags;
end
if (_GEN_17) begin
vpn_16 <= io_refill_vpn;
ppn_16 <= io_refill_ppn;
flags_16 <= io_refill_flags;
end
if (_GEN_18) begin
vpn_17 <= io_refill_vpn;
ppn_17 <= io_refill_ppn;
flags_17 <= io_refill_flags;
end
if (_GEN_19) begin
vpn_18 <= io_refill_vpn;
ppn_18 <= io_refill_ppn;
flags_18 <= io_refill_flags;
end
if (_GEN_20) begin
vpn_19 <= io_refill_vpn;
ppn_19 <= io_refill_ppn;
flags_19 <= io_refill_flags;
end
if (_GEN_21) begin
vpn_20 <= io_refill_vpn;
ppn_20 <= io_refill_ppn;
flags_20 <= io_refill_flags;
end
if (_GEN_22) begin
vpn_21 <= io_refill_vpn;
ppn_21 <= io_refill_ppn;
flags_21 <= io_refill_flags;
end
if (_GEN_23) begin
vpn_22 <= io_refill_vpn;
ppn_22 <= io_refill_ppn;
flags_22 <= io_refill_flags;
end
if (_GEN_24) begin
vpn_23 <= io_refill_vpn;
ppn_23 <= io_refill_ppn;
flags_23 <= io_refill_flags;
end
if (_GEN_25) begin
vpn_24 <= io_refill_vpn;
ppn_24 <= io_refill_ppn;
flags_24 <= io_refill_flags;
end
if (_GEN_26) begin
vpn_25 <= io_refill_vpn;
ppn_25 <= io_refill_ppn;
flags_25 <= io_refill_flags;
end
if (_GEN_27) begin
vpn_26 <= io_refill_vpn;
ppn_26 <= io_refill_ppn;
flags_26 <= io_refill_flags;
end
if (_GEN_28) begin
vpn_27 <= io_refill_vpn;
ppn_27 <= io_refill_ppn;
flags_27 <= io_refill_flags;
end
if (_GEN_29) begin
vpn_28 <= io_refill_vpn;
ppn_28 <= io_refill_ppn;
flags_28 <= io_refill_flags;
end
if (_GEN_30) begin
vpn_29 <= io_refill_vpn;
ppn_29 <= io_refill_ppn;
flags_29 <= io_refill_flags;
end
if (_GEN_31) begin
vpn_30 <= io_refill_vpn;
ppn_30 <= io_refill_ppn;
flags_30 <= io_refill_flags;
end
if (_GEN_32) begin
vpn_31 <= io_refill_vpn;
ppn_31 <= io_refill_ppn;
flags_31 <= io_refill_flags;
end
end // always @(posedge)
assign io_resp_hit = hit & ~pageFault;
assign io_resp_miss = io_req_valid & ~hit;
assign io_resp_paddr = {8'h0, _GEN_0[hitIdx], io_req_vaddr[11:0]};
assign io_resp_pageFault = pageFault;
endmodule

161
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// Generated by CIRCT firtool-1.139.0
module Decoder(
input [63:0] io_pc,
input [31:0] io_inst,
output [63:0] io_out_pc,
output [31:0] io_out_inst,
output [4:0] io_out_rs1,
io_out_rs2,
io_out_rd,
output [2:0] io_out_funct3,
output [63:0] io_out_immI,
io_out_immS,
io_out_immB,
io_out_immU,
io_out_immJ,
output [3:0] io_out_opClass,
output [4:0] io_out_aluFn,
output [2:0] io_out_memWidth,
output io_out_isLoad,
io_out_isStore,
io_out_isBranch,
io_out_isJal,
io_out_isJalr,
io_out_isLui,
io_out_isAuipc,
io_out_isOpImm,
io_out_isWord,
io_out_isSystem,
io_out_writesRd,
io_out_illegal
);
wire [7:0][1:0] _GEN = '{2'h3, 2'h2, 2'h1, 2'h0, 2'h3, 2'h2, 2'h1, 2'h0};
wire d_isLui = io_inst[6:0] == 7'h37;
wire _GEN_0 = io_inst[6:0] == 7'h17;
wire _GEN_1 = io_inst[6:0] == 7'h6F;
wire _GEN_2 = d_isLui | _GEN_0;
wire _GEN_3 = io_inst[6:0] == 7'h67;
wire _GEN_4 = io_inst[6:0] == 7'h63;
wire _GEN_5 = io_inst[6:0] == 7'h3;
wire _GEN_6 = io_inst[6:0] == 7'h23;
wire _d_isWord_T = io_inst[6:0] == 7'h1B;
wire _GEN_7 = io_inst[6:0] == 7'h13 | _d_isWord_T;
wire _GEN_8 = _GEN_0 | _GEN_1 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6;
wire _GEN_9 = d_isLui | _GEN_8;
wire [4:0] _d_aluFn_T_3 = {3'h0, io_inst[14:12] == 3'h1, 1'h0};
wire [7:0][4:0] _GEN_10 =
{{5'h9},
{5'h8},
{{4'h3, io_inst[30]}},
{5'h5},
{5'h4},
{5'h3},
{_d_aluFn_T_3},
{_d_aluFn_T_3}};
wire _d_isWord_T_1 = io_inst[6:0] == 7'h3B;
wire _GEN_11 = io_inst[6:0] == 7'h33 | _d_isWord_T_1;
wire [7:0][4:0] _GEN_12 =
{{5'h9},
{5'h8},
{{4'h3, io_inst[30]}},
{5'h5},
{5'h4},
{5'h3},
{5'h2},
{{4'h0, io_inst[30]}}};
wire _GEN_13 = io_inst[6:0] == 7'hF;
wire _GEN_14 = io_inst[6:0] == 7'h73;
wire _GEN_15 = io_inst[6:0] == 7'h2F;
wire _GEN_16 = _GEN_13 | _GEN_14;
wire _GEN_17 = _GEN_7 | _GEN_11 | _GEN_16;
wire _GEN_18 = _GEN_6 | _GEN_17;
wire _GEN_19 = _GEN_1 | _GEN_3 | _GEN_4;
assign io_out_pc = io_pc;
assign io_out_inst = io_inst;
assign io_out_rs1 = io_inst[19:15];
assign io_out_rs2 = io_inst[24:20];
assign io_out_rd = io_inst[11:7];
assign io_out_funct3 = io_inst[14:12];
assign io_out_immI = {{52{io_inst[31]}}, io_inst[31:20]};
assign io_out_immS = {{52{io_inst[31]}}, io_inst[31:25], io_inst[11:7]};
assign io_out_immB =
{{52{io_inst[31]}}, io_inst[7], io_inst[30:25], io_inst[11:8], 1'h0};
assign io_out_immU = {{32{io_inst[31]}}, io_inst[31:12], 12'h0};
assign io_out_immJ =
{{44{io_inst[31]}}, io_inst[19:12], io_inst[20], io_inst[30:21], 1'h0};
assign io_out_opClass =
_GEN_2
? 4'h1
: _GEN_19
? 4'h2
: _GEN_5
? 4'h3
: _GEN_6
? 4'h4
: _GEN_7 | _GEN_11 ? 4'h1 : _GEN_16 ? 4'h5 : _GEN_15 ? 4'h3 : 4'h0;
assign io_out_aluFn =
d_isLui
? 5'hF
: _GEN_8
? 5'h0
: _GEN_7
? _GEN_10[io_inst[14:12]]
: _GEN_11
? (io_inst[31:25] == 7'h1
? ((&(io_inst[14:12]))
? 5'hE
: io_inst[14:12] == 3'h6
? 5'hD
: io_inst[14:12] == 3'h5
? 5'hC
: {4'h5, io_inst[14:12] == 3'h4})
: _GEN_12[io_inst[14:12]])
: 5'h0;
assign io_out_memWidth =
d_isLui | _GEN_0 | _GEN_1 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_18 | ~_GEN_15
? {1'h0, _GEN[io_inst[14:12]]}
: {2'h1, io_inst[14:12] != 3'h2};
assign io_out_isLoad = ~(d_isLui | _GEN_0 | _GEN_19) & (_GEN_5 | ~_GEN_18 & _GEN_15);
assign io_out_isStore =
~(d_isLui | _GEN_0 | _GEN_1 | _GEN_3 | _GEN_4 | _GEN_5)
& (_GEN_6 | ~_GEN_17 & _GEN_15);
assign io_out_isBranch = ~(d_isLui | _GEN_0 | _GEN_1 | _GEN_3) & _GEN_4;
assign io_out_isJal = ~_GEN_2 & _GEN_1;
assign io_out_isJalr = ~(d_isLui | _GEN_0 | _GEN_1) & _GEN_3;
assign io_out_isLui = d_isLui;
assign io_out_isAuipc = ~d_isLui & _GEN_0;
assign io_out_isOpImm = ~_GEN_9 & _GEN_7;
assign io_out_isWord = ~_GEN_9 & (_GEN_7 ? _d_isWord_T : _GEN_11 & _d_isWord_T_1);
assign io_out_isSystem =
~(d_isLui | _GEN_0 | _GEN_1 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_11
| _GEN_13) & _GEN_14;
assign io_out_writesRd =
d_isLui
? (|(io_inst[11:7]))
: _GEN_0
? (|(io_inst[11:7]))
: _GEN_1
? (|(io_inst[11:7]))
: _GEN_3
? (|(io_inst[11:7]))
: ~_GEN_4
& (_GEN_5
? (|(io_inst[11:7]))
: ~_GEN_6
& (_GEN_7
? (|(io_inst[11:7]))
: _GEN_11
? (|(io_inst[11:7]))
: ~_GEN_13
& (_GEN_14
? (|(io_inst[11:7])) & (|(io_inst[14:12]))
: _GEN_15 & (|(io_inst[11:7])))));
assign io_out_illegal =
io_inst[6:0] != 7'h37 & io_inst[6:0] != 7'h17 & io_inst[6:0] != 7'h6F
& io_inst[6:0] != 7'h67 & io_inst[6:0] != 7'h63 & io_inst[6:0] != 7'h3
& io_inst[6:0] != 7'h23 & io_inst[6:0] != 7'h13 & io_inst[6:0] != 7'h1B
& io_inst[6:0] != 7'h33 & io_inst[6:0] != 7'h3B & io_inst[6:0] != 7'hF
& io_inst[6:0] != 7'h73 & io_inst[6:0] != 7'h2F;
endmodule

29
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// Generated by CIRCT firtool-1.139.0
module ExecStage(
input io_inValid,
input [2:0] io_in_funct3,
input [4:0] io_in_aluFn,
input io_in_isWord,
input [63:0] io_src1,
io_src2,
output io_outValid,
output [63:0] io_result,
output io_branchTaken
);
ALU alu (
.io_fn (io_in_aluFn),
.io_a (io_src1),
.io_b (io_src2),
.io_isWord (io_in_isWord),
.io_out (io_result)
);
BranchUnit branch (
.io_funct3 (io_in_funct3),
.io_a (io_src1),
.io_b (io_src2),
.io_taken (io_branchTaken)
);
assign io_outValid = io_inValid;
endmodule

2245
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62
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// Generated by CIRCT firtool-1.139.0
module Frontend(
input clock,
reset,
io_redirectValid,
input [63:0] io_redirectPc,
output io_imemReqValid,
output [63:0] io_imemReqAddr,
input io_imemRespValid,
input [31:0] io_imemRespBits_0,
io_imemRespBits_1,
input io_outReady,
output io_outValid,
output [63:0] io_out_pc,
output [31:0] io_out_inst_0,
io_out_inst_1,
output io_out_laneValid_0,
io_out_laneValid_1
);
wire _icache_io_respValid;
wire [63:0] _icache_io_resp_pc;
wire _icache_io_resp_laneValid_0;
wire _icache_io_resp_laneValid_1;
reg [63:0] pc;
always @(posedge clock) begin
if (reset)
pc <= 64'h80000000;
else if (io_redirectValid)
pc <= io_redirectPc;
else if (_icache_io_respValid & io_outReady)
pc <=
_icache_io_resp_pc
+ {60'h0,
{1'h0, _icache_io_resp_laneValid_0} + {1'h0, _icache_io_resp_laneValid_1},
2'h0};
end // always @(posedge)
ICache icache (
.clock (clock),
.reset (reset),
.io_reqAddr (pc),
.io_reqPc (pc),
.io_flush (io_redirectValid),
.io_respReady (io_outReady),
.io_memReqValid (io_imemReqValid),
.io_memReqAddr (io_imemReqAddr),
.io_memRespValid (io_imemRespValid),
.io_memRespBits_0 (io_imemRespBits_0),
.io_memRespBits_1 (io_imemRespBits_1),
.io_respValid (_icache_io_respValid),
.io_resp_pc (_icache_io_resp_pc),
.io_resp_inst_0 (io_out_inst_0),
.io_resp_inst_1 (io_out_inst_1),
.io_resp_laneValid_0 (_icache_io_resp_laneValid_0),
.io_resp_laneValid_1 (_icache_io_resp_laneValid_1)
);
assign io_outValid = _icache_io_respValid;
assign io_out_pc = _icache_io_resp_pc;
assign io_out_laneValid_0 = _icache_io_resp_laneValid_0;
assign io_out_laneValid_1 = _icache_io_resp_laneValid_1;
endmodule

49536
generated-ooo/ICache.sv Normal file
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128
generated-ooo/IDStage.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module IDStage(
input io_inValid,
input [63:0] io_in_pc,
input [31:0] io_in_inst_0,
io_in_inst_1,
input io_in_laneValid_0,
io_in_laneValid_1,
output io_outValid_0,
io_outValid_1,
output [63:0] io_out_0_pc,
output [31:0] io_out_0_inst,
output [4:0] io_out_0_rs1,
io_out_0_rs2,
io_out_0_rd,
output [2:0] io_out_0_funct3,
output [63:0] io_out_0_immI,
io_out_0_immS,
io_out_0_immB,
io_out_0_immU,
io_out_0_immJ,
output [3:0] io_out_0_opClass,
output [4:0] io_out_0_aluFn,
output [2:0] io_out_0_memWidth,
output io_out_0_isLoad,
io_out_0_isStore,
io_out_0_isBranch,
io_out_0_isJal,
io_out_0_isJalr,
io_out_0_isLui,
io_out_0_isAuipc,
io_out_0_isOpImm,
io_out_0_isWord,
io_out_0_isSystem,
io_out_0_writesRd,
io_out_0_illegal,
output [63:0] io_out_1_pc,
output [31:0] io_out_1_inst,
output [4:0] io_out_1_rs1,
io_out_1_rs2,
io_out_1_rd,
output [2:0] io_out_1_funct3,
output [63:0] io_out_1_immI,
io_out_1_immS,
io_out_1_immB,
io_out_1_immU,
io_out_1_immJ,
output [3:0] io_out_1_opClass,
output [4:0] io_out_1_aluFn,
output [2:0] io_out_1_memWidth,
output io_out_1_isLoad,
io_out_1_isStore,
io_out_1_isBranch,
io_out_1_isJal,
io_out_1_isJalr,
io_out_1_isLui,
io_out_1_isAuipc,
io_out_1_isOpImm,
io_out_1_isWord,
io_out_1_isSystem,
io_out_1_writesRd,
io_out_1_illegal
);
Decoder decoders_0 (
.io_pc (io_in_pc),
.io_inst (io_in_inst_0),
.io_out_pc (io_out_0_pc),
.io_out_inst (io_out_0_inst),
.io_out_rs1 (io_out_0_rs1),
.io_out_rs2 (io_out_0_rs2),
.io_out_rd (io_out_0_rd),
.io_out_funct3 (io_out_0_funct3),
.io_out_immI (io_out_0_immI),
.io_out_immS (io_out_0_immS),
.io_out_immB (io_out_0_immB),
.io_out_immU (io_out_0_immU),
.io_out_immJ (io_out_0_immJ),
.io_out_opClass (io_out_0_opClass),
.io_out_aluFn (io_out_0_aluFn),
.io_out_memWidth (io_out_0_memWidth),
.io_out_isLoad (io_out_0_isLoad),
.io_out_isStore (io_out_0_isStore),
.io_out_isBranch (io_out_0_isBranch),
.io_out_isJal (io_out_0_isJal),
.io_out_isJalr (io_out_0_isJalr),
.io_out_isLui (io_out_0_isLui),
.io_out_isAuipc (io_out_0_isAuipc),
.io_out_isOpImm (io_out_0_isOpImm),
.io_out_isWord (io_out_0_isWord),
.io_out_isSystem (io_out_0_isSystem),
.io_out_writesRd (io_out_0_writesRd),
.io_out_illegal (io_out_0_illegal)
);
Decoder decoders_1 (
.io_pc (io_in_pc + 64'h4),
.io_inst (io_in_inst_1),
.io_out_pc (io_out_1_pc),
.io_out_inst (io_out_1_inst),
.io_out_rs1 (io_out_1_rs1),
.io_out_rs2 (io_out_1_rs2),
.io_out_rd (io_out_1_rd),
.io_out_funct3 (io_out_1_funct3),
.io_out_immI (io_out_1_immI),
.io_out_immS (io_out_1_immS),
.io_out_immB (io_out_1_immB),
.io_out_immU (io_out_1_immU),
.io_out_immJ (io_out_1_immJ),
.io_out_opClass (io_out_1_opClass),
.io_out_aluFn (io_out_1_aluFn),
.io_out_memWidth (io_out_1_memWidth),
.io_out_isLoad (io_out_1_isLoad),
.io_out_isStore (io_out_1_isStore),
.io_out_isBranch (io_out_1_isBranch),
.io_out_isJal (io_out_1_isJal),
.io_out_isJalr (io_out_1_isJalr),
.io_out_isLui (io_out_1_isLui),
.io_out_isAuipc (io_out_1_isAuipc),
.io_out_isOpImm (io_out_1_isOpImm),
.io_out_isWord (io_out_1_isWord),
.io_out_isSystem (io_out_1_isSystem),
.io_out_writesRd (io_out_1_writesRd),
.io_out_illegal (io_out_1_illegal)
);
assign io_outValid_0 = io_inValid & io_in_laneValid_0;
assign io_outValid_1 = io_inValid & io_in_laneValid_1;
endmodule

266
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// Generated by CIRCT firtool-1.139.0
module IssueQueue(
input clock,
reset,
io_enqValid_0,
io_enqValid_1,
input [63:0] io_enq_0_decoded_pc,
input [31:0] io_enq_0_decoded_inst,
input [4:0] io_enq_0_decoded_rs1,
io_enq_0_decoded_rs2,
input [2:0] io_enq_0_decoded_funct3,
input [63:0] io_enq_0_decoded_immI,
io_enq_0_decoded_immS,
io_enq_0_decoded_immB,
io_enq_0_decoded_immU,
io_enq_0_decoded_immJ,
input [4:0] io_enq_0_decoded_aluFn,
input [2:0] io_enq_0_decoded_memWidth,
input io_enq_0_decoded_isLoad,
io_enq_0_decoded_isStore,
io_enq_0_decoded_isBranch,
io_enq_0_decoded_isJal,
io_enq_0_decoded_isJalr,
io_enq_0_decoded_isLui,
io_enq_0_decoded_isAuipc,
io_enq_0_decoded_isOpImm,
io_enq_0_decoded_isWord,
io_enq_0_decoded_isSystem,
io_enq_0_decoded_writesRd,
io_enq_0_decoded_illegal,
input [5:0] io_enq_0_prs1,
io_enq_0_prs2,
input io_enq_0_src1Ready,
io_enq_0_src2Ready,
input [5:0] io_enq_0_prd,
io_enq_0_robIdx,
input [63:0] io_enq_1_decoded_pc,
input [31:0] io_enq_1_decoded_inst,
input [4:0] io_enq_1_decoded_rs1,
io_enq_1_decoded_rs2,
input [2:0] io_enq_1_decoded_funct3,
input [63:0] io_enq_1_decoded_immI,
io_enq_1_decoded_immS,
io_enq_1_decoded_immB,
io_enq_1_decoded_immU,
io_enq_1_decoded_immJ,
input [4:0] io_enq_1_decoded_aluFn,
input [2:0] io_enq_1_decoded_memWidth,
input io_enq_1_decoded_isLoad,
io_enq_1_decoded_isStore,
io_enq_1_decoded_isBranch,
io_enq_1_decoded_isJal,
io_enq_1_decoded_isJalr,
io_enq_1_decoded_isLui,
io_enq_1_decoded_isAuipc,
io_enq_1_decoded_isOpImm,
io_enq_1_decoded_isWord,
io_enq_1_decoded_isSystem,
io_enq_1_decoded_writesRd,
io_enq_1_decoded_illegal,
input [5:0] io_enq_1_prs1,
io_enq_1_prs2,
input io_enq_1_src1Ready,
io_enq_1_src2Ready,
input [5:0] io_enq_1_prd,
io_enq_1_robIdx,
output io_enqReady_0,
io_enqReady_1,
input io_wakeup_0_valid,
input [5:0] io_wakeup_0_phys,
input io_wakeup_1_valid,
input [5:0] io_wakeup_1_phys,
output io_issueValid_0,
io_issueValid_1,
output [63:0] io_issue_0_decoded_pc,
output [31:0] io_issue_0_decoded_inst,
output [4:0] io_issue_0_decoded_rs1,
output [2:0] io_issue_0_decoded_funct3,
output [63:0] io_issue_0_decoded_immI,
io_issue_0_decoded_immS,
io_issue_0_decoded_immB,
io_issue_0_decoded_immU,
io_issue_0_decoded_immJ,
output [4:0] io_issue_0_decoded_aluFn,
output [2:0] io_issue_0_decoded_memWidth,
output io_issue_0_decoded_isLoad,
io_issue_0_decoded_isStore,
io_issue_0_decoded_isBranch,
io_issue_0_decoded_isJal,
io_issue_0_decoded_isJalr,
io_issue_0_decoded_isLui,
io_issue_0_decoded_isAuipc,
io_issue_0_decoded_isOpImm,
io_issue_0_decoded_isWord,
io_issue_0_decoded_isSystem,
io_issue_0_decoded_writesRd,
io_issue_0_decoded_illegal,
output [5:0] io_issue_0_prs1,
io_issue_0_prs2,
io_issue_0_prd,
io_issue_0_robIdx,
output [63:0] io_issue_1_decoded_pc,
output [31:0] io_issue_1_decoded_inst,
output [4:0] io_issue_1_decoded_rs1,
output [2:0] io_issue_1_decoded_funct3,
output [63:0] io_issue_1_decoded_immI,
io_issue_1_decoded_immS,
io_issue_1_decoded_immB,
io_issue_1_decoded_immU,
io_issue_1_decoded_immJ,
output [4:0] io_issue_1_decoded_aluFn,
output [2:0] io_issue_1_decoded_memWidth,
output io_issue_1_decoded_isLoad,
io_issue_1_decoded_isStore,
io_issue_1_decoded_isBranch,
io_issue_1_decoded_isJal,
io_issue_1_decoded_isJalr,
io_issue_1_decoded_isLui,
io_issue_1_decoded_isAuipc,
io_issue_1_decoded_isOpImm,
io_issue_1_decoded_isWord,
io_issue_1_decoded_isSystem,
io_issue_1_decoded_writesRd,
io_issue_1_decoded_illegal,
output [5:0] io_issue_1_prs1,
io_issue_1_prs2,
io_issue_1_prd,
io_issue_1_robIdx,
input io_issueReady_0,
io_issueReady_1,
io_flush
);
ReservationStation intRs (
.clock (clock),
.reset (reset),
.io_enqValid_0 (io_enqValid_0),
.io_enqValid_1 (io_enqValid_1),
.io_enq_0_decoded_pc (io_enq_0_decoded_pc),
.io_enq_0_decoded_inst (io_enq_0_decoded_inst),
.io_enq_0_decoded_rs1 (io_enq_0_decoded_rs1),
.io_enq_0_decoded_rs2 (io_enq_0_decoded_rs2),
.io_enq_0_decoded_funct3 (io_enq_0_decoded_funct3),
.io_enq_0_decoded_immI (io_enq_0_decoded_immI),
.io_enq_0_decoded_immS (io_enq_0_decoded_immS),
.io_enq_0_decoded_immB (io_enq_0_decoded_immB),
.io_enq_0_decoded_immU (io_enq_0_decoded_immU),
.io_enq_0_decoded_immJ (io_enq_0_decoded_immJ),
.io_enq_0_decoded_aluFn (io_enq_0_decoded_aluFn),
.io_enq_0_decoded_memWidth (io_enq_0_decoded_memWidth),
.io_enq_0_decoded_isLoad (io_enq_0_decoded_isLoad),
.io_enq_0_decoded_isStore (io_enq_0_decoded_isStore),
.io_enq_0_decoded_isBranch (io_enq_0_decoded_isBranch),
.io_enq_0_decoded_isJal (io_enq_0_decoded_isJal),
.io_enq_0_decoded_isJalr (io_enq_0_decoded_isJalr),
.io_enq_0_decoded_isLui (io_enq_0_decoded_isLui),
.io_enq_0_decoded_isAuipc (io_enq_0_decoded_isAuipc),
.io_enq_0_decoded_isOpImm (io_enq_0_decoded_isOpImm),
.io_enq_0_decoded_isWord (io_enq_0_decoded_isWord),
.io_enq_0_decoded_isSystem (io_enq_0_decoded_isSystem),
.io_enq_0_decoded_writesRd (io_enq_0_decoded_writesRd),
.io_enq_0_decoded_illegal (io_enq_0_decoded_illegal),
.io_enq_0_prs1 (io_enq_0_prs1),
.io_enq_0_prs2 (io_enq_0_prs2),
.io_enq_0_src1Ready (io_enq_0_src1Ready),
.io_enq_0_src2Ready (io_enq_0_src2Ready),
.io_enq_0_prd (io_enq_0_prd),
.io_enq_0_robIdx (io_enq_0_robIdx),
.io_enq_1_decoded_pc (io_enq_1_decoded_pc),
.io_enq_1_decoded_inst (io_enq_1_decoded_inst),
.io_enq_1_decoded_rs1 (io_enq_1_decoded_rs1),
.io_enq_1_decoded_rs2 (io_enq_1_decoded_rs2),
.io_enq_1_decoded_funct3 (io_enq_1_decoded_funct3),
.io_enq_1_decoded_immI (io_enq_1_decoded_immI),
.io_enq_1_decoded_immS (io_enq_1_decoded_immS),
.io_enq_1_decoded_immB (io_enq_1_decoded_immB),
.io_enq_1_decoded_immU (io_enq_1_decoded_immU),
.io_enq_1_decoded_immJ (io_enq_1_decoded_immJ),
.io_enq_1_decoded_aluFn (io_enq_1_decoded_aluFn),
.io_enq_1_decoded_memWidth (io_enq_1_decoded_memWidth),
.io_enq_1_decoded_isLoad (io_enq_1_decoded_isLoad),
.io_enq_1_decoded_isStore (io_enq_1_decoded_isStore),
.io_enq_1_decoded_isBranch (io_enq_1_decoded_isBranch),
.io_enq_1_decoded_isJal (io_enq_1_decoded_isJal),
.io_enq_1_decoded_isJalr (io_enq_1_decoded_isJalr),
.io_enq_1_decoded_isLui (io_enq_1_decoded_isLui),
.io_enq_1_decoded_isAuipc (io_enq_1_decoded_isAuipc),
.io_enq_1_decoded_isOpImm (io_enq_1_decoded_isOpImm),
.io_enq_1_decoded_isWord (io_enq_1_decoded_isWord),
.io_enq_1_decoded_isSystem (io_enq_1_decoded_isSystem),
.io_enq_1_decoded_writesRd (io_enq_1_decoded_writesRd),
.io_enq_1_decoded_illegal (io_enq_1_decoded_illegal),
.io_enq_1_prs1 (io_enq_1_prs1),
.io_enq_1_prs2 (io_enq_1_prs2),
.io_enq_1_src1Ready (io_enq_1_src1Ready),
.io_enq_1_src2Ready (io_enq_1_src2Ready),
.io_enq_1_prd (io_enq_1_prd),
.io_enq_1_robIdx (io_enq_1_robIdx),
.io_enqReady_0 (io_enqReady_0),
.io_enqReady_1 (io_enqReady_1),
.io_wakeup_0_valid (io_wakeup_0_valid),
.io_wakeup_0_phys (io_wakeup_0_phys),
.io_wakeup_1_valid (io_wakeup_1_valid),
.io_wakeup_1_phys (io_wakeup_1_phys),
.io_issueValid_0 (io_issueValid_0),
.io_issueValid_1 (io_issueValid_1),
.io_issue_0_decoded_pc (io_issue_0_decoded_pc),
.io_issue_0_decoded_inst (io_issue_0_decoded_inst),
.io_issue_0_decoded_rs1 (io_issue_0_decoded_rs1),
.io_issue_0_decoded_funct3 (io_issue_0_decoded_funct3),
.io_issue_0_decoded_immI (io_issue_0_decoded_immI),
.io_issue_0_decoded_immS (io_issue_0_decoded_immS),
.io_issue_0_decoded_immB (io_issue_0_decoded_immB),
.io_issue_0_decoded_immU (io_issue_0_decoded_immU),
.io_issue_0_decoded_immJ (io_issue_0_decoded_immJ),
.io_issue_0_decoded_aluFn (io_issue_0_decoded_aluFn),
.io_issue_0_decoded_memWidth (io_issue_0_decoded_memWidth),
.io_issue_0_decoded_isLoad (io_issue_0_decoded_isLoad),
.io_issue_0_decoded_isStore (io_issue_0_decoded_isStore),
.io_issue_0_decoded_isBranch (io_issue_0_decoded_isBranch),
.io_issue_0_decoded_isJal (io_issue_0_decoded_isJal),
.io_issue_0_decoded_isJalr (io_issue_0_decoded_isJalr),
.io_issue_0_decoded_isLui (io_issue_0_decoded_isLui),
.io_issue_0_decoded_isAuipc (io_issue_0_decoded_isAuipc),
.io_issue_0_decoded_isOpImm (io_issue_0_decoded_isOpImm),
.io_issue_0_decoded_isWord (io_issue_0_decoded_isWord),
.io_issue_0_decoded_isSystem (io_issue_0_decoded_isSystem),
.io_issue_0_decoded_writesRd (io_issue_0_decoded_writesRd),
.io_issue_0_decoded_illegal (io_issue_0_decoded_illegal),
.io_issue_0_prs1 (io_issue_0_prs1),
.io_issue_0_prs2 (io_issue_0_prs2),
.io_issue_0_prd (io_issue_0_prd),
.io_issue_0_robIdx (io_issue_0_robIdx),
.io_issue_1_decoded_pc (io_issue_1_decoded_pc),
.io_issue_1_decoded_inst (io_issue_1_decoded_inst),
.io_issue_1_decoded_rs1 (io_issue_1_decoded_rs1),
.io_issue_1_decoded_funct3 (io_issue_1_decoded_funct3),
.io_issue_1_decoded_immI (io_issue_1_decoded_immI),
.io_issue_1_decoded_immS (io_issue_1_decoded_immS),
.io_issue_1_decoded_immB (io_issue_1_decoded_immB),
.io_issue_1_decoded_immU (io_issue_1_decoded_immU),
.io_issue_1_decoded_immJ (io_issue_1_decoded_immJ),
.io_issue_1_decoded_aluFn (io_issue_1_decoded_aluFn),
.io_issue_1_decoded_memWidth (io_issue_1_decoded_memWidth),
.io_issue_1_decoded_isLoad (io_issue_1_decoded_isLoad),
.io_issue_1_decoded_isStore (io_issue_1_decoded_isStore),
.io_issue_1_decoded_isBranch (io_issue_1_decoded_isBranch),
.io_issue_1_decoded_isJal (io_issue_1_decoded_isJal),
.io_issue_1_decoded_isJalr (io_issue_1_decoded_isJalr),
.io_issue_1_decoded_isLui (io_issue_1_decoded_isLui),
.io_issue_1_decoded_isAuipc (io_issue_1_decoded_isAuipc),
.io_issue_1_decoded_isOpImm (io_issue_1_decoded_isOpImm),
.io_issue_1_decoded_isWord (io_issue_1_decoded_isWord),
.io_issue_1_decoded_isSystem (io_issue_1_decoded_isSystem),
.io_issue_1_decoded_writesRd (io_issue_1_decoded_writesRd),
.io_issue_1_decoded_illegal (io_issue_1_decoded_illegal),
.io_issue_1_prs1 (io_issue_1_prs1),
.io_issue_1_prs2 (io_issue_1_prs2),
.io_issue_1_prd (io_issue_1_prd),
.io_issue_1_robIdx (io_issue_1_robIdx),
.io_issueReady_0 (io_issueReady_0),
.io_issueReady_1 (io_issueReady_1),
.io_flush (io_flush)
);
endmodule

266
generated-ooo/IssueStage.sv Normal file
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@@ -0,0 +1,266 @@
// Generated by CIRCT firtool-1.139.0
module IssueStage(
input clock,
reset,
io_inValid_0,
io_inValid_1,
input [63:0] io_in_0_decoded_pc,
input [31:0] io_in_0_decoded_inst,
input [4:0] io_in_0_decoded_rs1,
io_in_0_decoded_rs2,
input [2:0] io_in_0_decoded_funct3,
input [63:0] io_in_0_decoded_immI,
io_in_0_decoded_immS,
io_in_0_decoded_immB,
io_in_0_decoded_immU,
io_in_0_decoded_immJ,
input [4:0] io_in_0_decoded_aluFn,
input [2:0] io_in_0_decoded_memWidth,
input io_in_0_decoded_isLoad,
io_in_0_decoded_isStore,
io_in_0_decoded_isBranch,
io_in_0_decoded_isJal,
io_in_0_decoded_isJalr,
io_in_0_decoded_isLui,
io_in_0_decoded_isAuipc,
io_in_0_decoded_isOpImm,
io_in_0_decoded_isWord,
io_in_0_decoded_isSystem,
io_in_0_decoded_writesRd,
io_in_0_decoded_illegal,
input [5:0] io_in_0_prs1,
io_in_0_prs2,
input io_in_0_src1Ready,
io_in_0_src2Ready,
input [5:0] io_in_0_prd,
io_in_0_robIdx,
input [63:0] io_in_1_decoded_pc,
input [31:0] io_in_1_decoded_inst,
input [4:0] io_in_1_decoded_rs1,
io_in_1_decoded_rs2,
input [2:0] io_in_1_decoded_funct3,
input [63:0] io_in_1_decoded_immI,
io_in_1_decoded_immS,
io_in_1_decoded_immB,
io_in_1_decoded_immU,
io_in_1_decoded_immJ,
input [4:0] io_in_1_decoded_aluFn,
input [2:0] io_in_1_decoded_memWidth,
input io_in_1_decoded_isLoad,
io_in_1_decoded_isStore,
io_in_1_decoded_isBranch,
io_in_1_decoded_isJal,
io_in_1_decoded_isJalr,
io_in_1_decoded_isLui,
io_in_1_decoded_isAuipc,
io_in_1_decoded_isOpImm,
io_in_1_decoded_isWord,
io_in_1_decoded_isSystem,
io_in_1_decoded_writesRd,
io_in_1_decoded_illegal,
input [5:0] io_in_1_prs1,
io_in_1_prs2,
input io_in_1_src1Ready,
io_in_1_src2Ready,
input [5:0] io_in_1_prd,
io_in_1_robIdx,
output io_inReady_0,
io_inReady_1,
input io_wakeup_0_valid,
input [5:0] io_wakeup_0_phys,
input io_wakeup_1_valid,
input [5:0] io_wakeup_1_phys,
output io_outValid_0,
io_outValid_1,
output [63:0] io_out_0_decoded_pc,
output [31:0] io_out_0_decoded_inst,
output [4:0] io_out_0_decoded_rs1,
output [2:0] io_out_0_decoded_funct3,
output [63:0] io_out_0_decoded_immI,
io_out_0_decoded_immS,
io_out_0_decoded_immB,
io_out_0_decoded_immU,
io_out_0_decoded_immJ,
output [4:0] io_out_0_decoded_aluFn,
output [2:0] io_out_0_decoded_memWidth,
output io_out_0_decoded_isLoad,
io_out_0_decoded_isStore,
io_out_0_decoded_isBranch,
io_out_0_decoded_isJal,
io_out_0_decoded_isJalr,
io_out_0_decoded_isLui,
io_out_0_decoded_isAuipc,
io_out_0_decoded_isOpImm,
io_out_0_decoded_isWord,
io_out_0_decoded_isSystem,
io_out_0_decoded_writesRd,
io_out_0_decoded_illegal,
output [5:0] io_out_0_prs1,
io_out_0_prs2,
io_out_0_prd,
io_out_0_robIdx,
output [63:0] io_out_1_decoded_pc,
output [31:0] io_out_1_decoded_inst,
output [4:0] io_out_1_decoded_rs1,
output [2:0] io_out_1_decoded_funct3,
output [63:0] io_out_1_decoded_immI,
io_out_1_decoded_immS,
io_out_1_decoded_immB,
io_out_1_decoded_immU,
io_out_1_decoded_immJ,
output [4:0] io_out_1_decoded_aluFn,
output [2:0] io_out_1_decoded_memWidth,
output io_out_1_decoded_isLoad,
io_out_1_decoded_isStore,
io_out_1_decoded_isBranch,
io_out_1_decoded_isJal,
io_out_1_decoded_isJalr,
io_out_1_decoded_isLui,
io_out_1_decoded_isAuipc,
io_out_1_decoded_isOpImm,
io_out_1_decoded_isWord,
io_out_1_decoded_isSystem,
io_out_1_decoded_writesRd,
io_out_1_decoded_illegal,
output [5:0] io_out_1_prs1,
io_out_1_prs2,
io_out_1_prd,
io_out_1_robIdx,
input io_outReady_0,
io_outReady_1,
io_flush
);
IssueQueue queue (
.clock (clock),
.reset (reset),
.io_enqValid_0 (io_inValid_0),
.io_enqValid_1 (io_inValid_1),
.io_enq_0_decoded_pc (io_in_0_decoded_pc),
.io_enq_0_decoded_inst (io_in_0_decoded_inst),
.io_enq_0_decoded_rs1 (io_in_0_decoded_rs1),
.io_enq_0_decoded_rs2 (io_in_0_decoded_rs2),
.io_enq_0_decoded_funct3 (io_in_0_decoded_funct3),
.io_enq_0_decoded_immI (io_in_0_decoded_immI),
.io_enq_0_decoded_immS (io_in_0_decoded_immS),
.io_enq_0_decoded_immB (io_in_0_decoded_immB),
.io_enq_0_decoded_immU (io_in_0_decoded_immU),
.io_enq_0_decoded_immJ (io_in_0_decoded_immJ),
.io_enq_0_decoded_aluFn (io_in_0_decoded_aluFn),
.io_enq_0_decoded_memWidth (io_in_0_decoded_memWidth),
.io_enq_0_decoded_isLoad (io_in_0_decoded_isLoad),
.io_enq_0_decoded_isStore (io_in_0_decoded_isStore),
.io_enq_0_decoded_isBranch (io_in_0_decoded_isBranch),
.io_enq_0_decoded_isJal (io_in_0_decoded_isJal),
.io_enq_0_decoded_isJalr (io_in_0_decoded_isJalr),
.io_enq_0_decoded_isLui (io_in_0_decoded_isLui),
.io_enq_0_decoded_isAuipc (io_in_0_decoded_isAuipc),
.io_enq_0_decoded_isOpImm (io_in_0_decoded_isOpImm),
.io_enq_0_decoded_isWord (io_in_0_decoded_isWord),
.io_enq_0_decoded_isSystem (io_in_0_decoded_isSystem),
.io_enq_0_decoded_writesRd (io_in_0_decoded_writesRd),
.io_enq_0_decoded_illegal (io_in_0_decoded_illegal),
.io_enq_0_prs1 (io_in_0_prs1),
.io_enq_0_prs2 (io_in_0_prs2),
.io_enq_0_src1Ready (io_in_0_src1Ready),
.io_enq_0_src2Ready (io_in_0_src2Ready),
.io_enq_0_prd (io_in_0_prd),
.io_enq_0_robIdx (io_in_0_robIdx),
.io_enq_1_decoded_pc (io_in_1_decoded_pc),
.io_enq_1_decoded_inst (io_in_1_decoded_inst),
.io_enq_1_decoded_rs1 (io_in_1_decoded_rs1),
.io_enq_1_decoded_rs2 (io_in_1_decoded_rs2),
.io_enq_1_decoded_funct3 (io_in_1_decoded_funct3),
.io_enq_1_decoded_immI (io_in_1_decoded_immI),
.io_enq_1_decoded_immS (io_in_1_decoded_immS),
.io_enq_1_decoded_immB (io_in_1_decoded_immB),
.io_enq_1_decoded_immU (io_in_1_decoded_immU),
.io_enq_1_decoded_immJ (io_in_1_decoded_immJ),
.io_enq_1_decoded_aluFn (io_in_1_decoded_aluFn),
.io_enq_1_decoded_memWidth (io_in_1_decoded_memWidth),
.io_enq_1_decoded_isLoad (io_in_1_decoded_isLoad),
.io_enq_1_decoded_isStore (io_in_1_decoded_isStore),
.io_enq_1_decoded_isBranch (io_in_1_decoded_isBranch),
.io_enq_1_decoded_isJal (io_in_1_decoded_isJal),
.io_enq_1_decoded_isJalr (io_in_1_decoded_isJalr),
.io_enq_1_decoded_isLui (io_in_1_decoded_isLui),
.io_enq_1_decoded_isAuipc (io_in_1_decoded_isAuipc),
.io_enq_1_decoded_isOpImm (io_in_1_decoded_isOpImm),
.io_enq_1_decoded_isWord (io_in_1_decoded_isWord),
.io_enq_1_decoded_isSystem (io_in_1_decoded_isSystem),
.io_enq_1_decoded_writesRd (io_in_1_decoded_writesRd),
.io_enq_1_decoded_illegal (io_in_1_decoded_illegal),
.io_enq_1_prs1 (io_in_1_prs1),
.io_enq_1_prs2 (io_in_1_prs2),
.io_enq_1_src1Ready (io_in_1_src1Ready),
.io_enq_1_src2Ready (io_in_1_src2Ready),
.io_enq_1_prd (io_in_1_prd),
.io_enq_1_robIdx (io_in_1_robIdx),
.io_enqReady_0 (io_inReady_0),
.io_enqReady_1 (io_inReady_1),
.io_wakeup_0_valid (io_wakeup_0_valid),
.io_wakeup_0_phys (io_wakeup_0_phys),
.io_wakeup_1_valid (io_wakeup_1_valid),
.io_wakeup_1_phys (io_wakeup_1_phys),
.io_issueValid_0 (io_outValid_0),
.io_issueValid_1 (io_outValid_1),
.io_issue_0_decoded_pc (io_out_0_decoded_pc),
.io_issue_0_decoded_inst (io_out_0_decoded_inst),
.io_issue_0_decoded_rs1 (io_out_0_decoded_rs1),
.io_issue_0_decoded_funct3 (io_out_0_decoded_funct3),
.io_issue_0_decoded_immI (io_out_0_decoded_immI),
.io_issue_0_decoded_immS (io_out_0_decoded_immS),
.io_issue_0_decoded_immB (io_out_0_decoded_immB),
.io_issue_0_decoded_immU (io_out_0_decoded_immU),
.io_issue_0_decoded_immJ (io_out_0_decoded_immJ),
.io_issue_0_decoded_aluFn (io_out_0_decoded_aluFn),
.io_issue_0_decoded_memWidth (io_out_0_decoded_memWidth),
.io_issue_0_decoded_isLoad (io_out_0_decoded_isLoad),
.io_issue_0_decoded_isStore (io_out_0_decoded_isStore),
.io_issue_0_decoded_isBranch (io_out_0_decoded_isBranch),
.io_issue_0_decoded_isJal (io_out_0_decoded_isJal),
.io_issue_0_decoded_isJalr (io_out_0_decoded_isJalr),
.io_issue_0_decoded_isLui (io_out_0_decoded_isLui),
.io_issue_0_decoded_isAuipc (io_out_0_decoded_isAuipc),
.io_issue_0_decoded_isOpImm (io_out_0_decoded_isOpImm),
.io_issue_0_decoded_isWord (io_out_0_decoded_isWord),
.io_issue_0_decoded_isSystem (io_out_0_decoded_isSystem),
.io_issue_0_decoded_writesRd (io_out_0_decoded_writesRd),
.io_issue_0_decoded_illegal (io_out_0_decoded_illegal),
.io_issue_0_prs1 (io_out_0_prs1),
.io_issue_0_prs2 (io_out_0_prs2),
.io_issue_0_prd (io_out_0_prd),
.io_issue_0_robIdx (io_out_0_robIdx),
.io_issue_1_decoded_pc (io_out_1_decoded_pc),
.io_issue_1_decoded_inst (io_out_1_decoded_inst),
.io_issue_1_decoded_rs1 (io_out_1_decoded_rs1),
.io_issue_1_decoded_funct3 (io_out_1_decoded_funct3),
.io_issue_1_decoded_immI (io_out_1_decoded_immI),
.io_issue_1_decoded_immS (io_out_1_decoded_immS),
.io_issue_1_decoded_immB (io_out_1_decoded_immB),
.io_issue_1_decoded_immU (io_out_1_decoded_immU),
.io_issue_1_decoded_immJ (io_out_1_decoded_immJ),
.io_issue_1_decoded_aluFn (io_out_1_decoded_aluFn),
.io_issue_1_decoded_memWidth (io_out_1_decoded_memWidth),
.io_issue_1_decoded_isLoad (io_out_1_decoded_isLoad),
.io_issue_1_decoded_isStore (io_out_1_decoded_isStore),
.io_issue_1_decoded_isBranch (io_out_1_decoded_isBranch),
.io_issue_1_decoded_isJal (io_out_1_decoded_isJal),
.io_issue_1_decoded_isJalr (io_out_1_decoded_isJalr),
.io_issue_1_decoded_isLui (io_out_1_decoded_isLui),
.io_issue_1_decoded_isAuipc (io_out_1_decoded_isAuipc),
.io_issue_1_decoded_isOpImm (io_out_1_decoded_isOpImm),
.io_issue_1_decoded_isWord (io_out_1_decoded_isWord),
.io_issue_1_decoded_isSystem (io_out_1_decoded_isSystem),
.io_issue_1_decoded_writesRd (io_out_1_decoded_writesRd),
.io_issue_1_decoded_illegal (io_out_1_decoded_illegal),
.io_issue_1_prs1 (io_out_1_prs1),
.io_issue_1_prs2 (io_out_1_prs2),
.io_issue_1_prd (io_out_1_prd),
.io_issue_1_robIdx (io_out_1_robIdx),
.io_issueReady_0 (io_outReady_0),
.io_issueReady_1 (io_outReady_1),
.io_flush (io_flush)
);
endmodule

113
generated-ooo/LSU.sv Normal file
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@@ -0,0 +1,113 @@
// Generated by CIRCT firtool-1.139.0
module LSU(
input clock,
reset,
io_reqValid,
input [63:0] io_req_addr,
io_req_data,
input io_req_isStore,
input [2:0] io_req_size,
output io_reqReady,
input [63:0] io_satp,
output io_dmemReqValid,
output [63:0] io_dmemReq_addr,
io_dmemReq_data,
output io_dmemReq_isStore,
output [2:0] io_dmemReq_size,
input io_dmemRespValid,
input [63:0] io_dmemRespData,
output io_respValid,
output [63:0] io_respData,
output io_pageFault
);
wire _dcache_io_reqReady;
wire _dcache_io_memReqValid;
wire [63:0] _dcache_io_memReq_addr;
wire [63:0] _dcache_io_memReq_data;
wire _dcache_io_memReq_isStore;
wire [2:0] _dcache_io_memReq_size;
wire _dcache_io_respValid;
wire _mmu_io_resp_pageFault;
wire _mmu_io_ptwMemReq_valid;
wire [63:0] _mmu_io_ptwMemReq_addr;
wire _mmu_io_refill_valid;
wire [26:0] _mmu_io_refill_vpn;
wire [43:0] _mmu_io_refill_ppn;
wire [7:0] _mmu_io_refill_flags;
wire _dtlb_io_resp_hit;
wire _dtlb_io_resp_miss;
wire [63:0] _dtlb_io_resp_paddr;
wire _dtlb_io_resp_pageFault;
reg ptwOutstanding;
wire translationFault = _dtlb_io_resp_pageFault | _mmu_io_resp_pageFault;
always @(posedge clock) begin
if (reset)
ptwOutstanding <= 1'h0;
else
ptwOutstanding <=
_mmu_io_ptwMemReq_valid | ~(io_dmemRespValid & ptwOutstanding) & ptwOutstanding;
end // always @(posedge)
DTLB dtlb (
.clock (clock),
.reset (reset),
.io_req_valid (io_reqValid & (|(io_satp[63:60]))),
.io_req_vaddr (io_req_addr),
.io_req_isStore (io_req_isStore),
.io_resp_hit (_dtlb_io_resp_hit),
.io_resp_miss (_dtlb_io_resp_miss),
.io_resp_paddr (_dtlb_io_resp_paddr),
.io_resp_pageFault (_dtlb_io_resp_pageFault),
.io_refill_valid (_mmu_io_refill_valid),
.io_refill_vpn (_mmu_io_refill_vpn),
.io_refill_ppn (_mmu_io_refill_ppn),
.io_refill_flags (_mmu_io_refill_flags)
);
MMU mmu (
.clock (clock),
.reset (reset),
.io_satp (io_satp),
.io_req_valid (io_reqValid & (|(io_satp[63:60])) & _dtlb_io_resp_miss),
.io_req_vaddr (io_req_addr),
.io_req_isStore (io_req_isStore),
.io_resp_pageFault (_mmu_io_resp_pageFault),
.io_ptwMemReq_valid (_mmu_io_ptwMemReq_valid),
.io_ptwMemReq_addr (_mmu_io_ptwMemReq_addr),
.io_ptwMemResp_valid (io_dmemRespValid & ptwOutstanding),
.io_ptwMemResp_data (io_dmemRespData),
.io_refill_valid (_mmu_io_refill_valid),
.io_refill_vpn (_mmu_io_refill_vpn),
.io_refill_ppn (_mmu_io_refill_ppn),
.io_refill_flags (_mmu_io_refill_flags)
);
DCache dcache (
.clock (clock),
.reset (reset),
.io_reqValid
(io_reqValid & (~(|(io_satp[63:60])) | _dtlb_io_resp_hit) & ~translationFault),
.io_req_addr ((|(io_satp[63:60])) ? _dtlb_io_resp_paddr : io_req_addr),
.io_req_data (io_req_data),
.io_req_isStore (io_req_isStore),
.io_req_size (io_req_size),
.io_reqReady (_dcache_io_reqReady),
.io_memReqValid (_dcache_io_memReqValid),
.io_memReq_addr (_dcache_io_memReq_addr),
.io_memReq_data (_dcache_io_memReq_data),
.io_memReq_isStore (_dcache_io_memReq_isStore),
.io_memReq_size (_dcache_io_memReq_size),
.io_memRespValid (io_dmemRespValid & ~ptwOutstanding),
.io_memRespData (io_dmemRespData),
.io_respValid (_dcache_io_respValid),
.io_respData (io_respData)
);
assign io_reqReady = _dcache_io_reqReady & ~ptwOutstanding;
assign io_dmemReqValid = _mmu_io_ptwMemReq_valid | _dcache_io_memReqValid;
assign io_dmemReq_addr =
_mmu_io_ptwMemReq_valid ? _mmu_io_ptwMemReq_addr : _dcache_io_memReq_addr;
assign io_dmemReq_data = _mmu_io_ptwMemReq_valid ? 64'h0 : _dcache_io_memReq_data;
assign io_dmemReq_isStore = ~_mmu_io_ptwMemReq_valid & _dcache_io_memReq_isStore;
assign io_dmemReq_size = _mmu_io_ptwMemReq_valid ? 3'h3 : _dcache_io_memReq_size;
assign io_respValid = _dcache_io_respValid | translationFault;
assign io_pageFault = translationFault;
endmodule

865
generated-ooo/LoadQueue.sv Normal file
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@@ -0,0 +1,865 @@
// Generated by CIRCT firtool-1.139.0
module LoadQueue(
input clock,
reset,
io_enqValid,
input [5:0] io_enqRobIdx,
output [3:0] io_enqIdx,
input io_addrValid,
input [3:0] io_addrIdx,
input [63:0] io_addr,
input [2:0] io_size,
input io_complete,
input [3:0] io_completeIdx,
input io_storeAddrValid,
input [5:0] io_storeRobIdx,
input [63:0] io_storeAddr,
input [2:0] io_storeSize,
output io_violation,
input io_flush
);
reg entries_0_valid;
reg [5:0] entries_0_robIdx;
reg entries_0_addrValid;
reg [63:0] entries_0_addr;
reg [2:0] entries_0_size;
reg entries_0_completed;
reg entries_1_valid;
reg [5:0] entries_1_robIdx;
reg entries_1_addrValid;
reg [63:0] entries_1_addr;
reg [2:0] entries_1_size;
reg entries_1_completed;
reg entries_2_valid;
reg [5:0] entries_2_robIdx;
reg entries_2_addrValid;
reg [63:0] entries_2_addr;
reg [2:0] entries_2_size;
reg entries_2_completed;
reg entries_3_valid;
reg [5:0] entries_3_robIdx;
reg entries_3_addrValid;
reg [63:0] entries_3_addr;
reg [2:0] entries_3_size;
reg entries_3_completed;
reg entries_4_valid;
reg [5:0] entries_4_robIdx;
reg entries_4_addrValid;
reg [63:0] entries_4_addr;
reg [2:0] entries_4_size;
reg entries_4_completed;
reg entries_5_valid;
reg [5:0] entries_5_robIdx;
reg entries_5_addrValid;
reg [63:0] entries_5_addr;
reg [2:0] entries_5_size;
reg entries_5_completed;
reg entries_6_valid;
reg [5:0] entries_6_robIdx;
reg entries_6_addrValid;
reg [63:0] entries_6_addr;
reg [2:0] entries_6_size;
reg entries_6_completed;
reg entries_7_valid;
reg [5:0] entries_7_robIdx;
reg entries_7_addrValid;
reg [63:0] entries_7_addr;
reg [2:0] entries_7_size;
reg entries_7_completed;
reg entries_8_valid;
reg [5:0] entries_8_robIdx;
reg entries_8_addrValid;
reg [63:0] entries_8_addr;
reg [2:0] entries_8_size;
reg entries_8_completed;
reg entries_9_valid;
reg [5:0] entries_9_robIdx;
reg entries_9_addrValid;
reg [63:0] entries_9_addr;
reg [2:0] entries_9_size;
reg entries_9_completed;
reg entries_10_valid;
reg [5:0] entries_10_robIdx;
reg entries_10_addrValid;
reg [63:0] entries_10_addr;
reg [2:0] entries_10_size;
reg entries_10_completed;
reg entries_11_valid;
reg [5:0] entries_11_robIdx;
reg entries_11_addrValid;
reg [63:0] entries_11_addr;
reg [2:0] entries_11_size;
reg entries_11_completed;
reg entries_12_valid;
reg [5:0] entries_12_robIdx;
reg entries_12_addrValid;
reg [63:0] entries_12_addr;
reg [2:0] entries_12_size;
reg entries_12_completed;
reg entries_13_valid;
reg [5:0] entries_13_robIdx;
reg entries_13_addrValid;
reg [63:0] entries_13_addr;
reg [2:0] entries_13_size;
reg entries_13_completed;
reg entries_14_valid;
reg [5:0] entries_14_robIdx;
reg entries_14_addrValid;
reg [63:0] entries_14_addr;
reg [2:0] entries_14_size;
reg entries_14_completed;
reg entries_15_valid;
reg [5:0] entries_15_robIdx;
reg entries_15_addrValid;
reg [63:0] entries_15_addr;
reg [2:0] entries_15_size;
reg entries_15_completed;
wire [14:0] enqOH =
entries_0_valid
? (entries_1_valid
? (entries_2_valid
? (entries_3_valid
? (entries_4_valid
? (entries_5_valid
? (entries_6_valid
? (entries_7_valid
? (entries_8_valid
? (entries_9_valid
? (entries_10_valid
? (entries_11_valid
? (entries_12_valid
? (entries_13_valid
? (entries_14_valid
? {~entries_15_valid,
14'h0}
: 15'h2000)
: 15'h1000)
: 15'h800)
: 15'h400)
: 15'h200)
: 15'h100)
: 15'h80)
: 15'h40)
: 15'h20)
: 15'h10)
: 15'h8)
: 15'h4)
: 15'h2)
: 15'h1)
: 15'h0;
wire [6:0] _enqIdx_T_1 = enqOH[14:8] | enqOH[6:0];
wire [2:0] _enqIdx_T_3 = _enqIdx_T_1[6:4] | _enqIdx_T_1[2:0];
wire [3:0] enqIdx =
{|(enqOH[14:7]),
|(_enqIdx_T_1[6:3]),
|(_enqIdx_T_3[2:1]),
_enqIdx_T_3[2] | _enqIdx_T_3[0]};
wire _violationVec_15_bm_T = io_storeSize == 3'h0;
wire _violationVec_15_bm_T_2 = io_storeSize == 3'h1;
wire _violationVec_15_bm_T_4 = io_storeSize == 3'h2;
wire _violationVec_15_bm_T_6 = io_storeSize == 3'h3;
wire [15:0] _io_violation_T =
{io_storeAddrValid & entries_15_valid & entries_15_completed & entries_15_addrValid
& entries_15_robIdx > io_storeRobIdx & entries_15_addr[63:3] == io_storeAddr[63:3]
& (entries_15_addr[2:0]
| (entries_15_size == 3'h3
? 3'h7
: entries_15_size == 3'h2
? 3'h3
: entries_15_size == 3'h1
? 3'h1
: entries_15_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_15_addr[2:0],
io_storeAddrValid & entries_14_valid & entries_14_completed & entries_14_addrValid
& entries_14_robIdx > io_storeRobIdx & entries_14_addr[63:3] == io_storeAddr[63:3]
& (entries_14_addr[2:0]
| (entries_14_size == 3'h3
? 3'h7
: entries_14_size == 3'h2
? 3'h3
: entries_14_size == 3'h1
? 3'h1
: entries_14_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_14_addr[2:0],
io_storeAddrValid & entries_13_valid & entries_13_completed & entries_13_addrValid
& entries_13_robIdx > io_storeRobIdx & entries_13_addr[63:3] == io_storeAddr[63:3]
& (entries_13_addr[2:0]
| (entries_13_size == 3'h3
? 3'h7
: entries_13_size == 3'h2
? 3'h3
: entries_13_size == 3'h1
? 3'h1
: entries_13_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_13_addr[2:0],
io_storeAddrValid & entries_12_valid & entries_12_completed & entries_12_addrValid
& entries_12_robIdx > io_storeRobIdx & entries_12_addr[63:3] == io_storeAddr[63:3]
& (entries_12_addr[2:0]
| (entries_12_size == 3'h3
? 3'h7
: entries_12_size == 3'h2
? 3'h3
: entries_12_size == 3'h1
? 3'h1
: entries_12_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_12_addr[2:0],
io_storeAddrValid & entries_11_valid & entries_11_completed & entries_11_addrValid
& entries_11_robIdx > io_storeRobIdx & entries_11_addr[63:3] == io_storeAddr[63:3]
& (entries_11_addr[2:0]
| (entries_11_size == 3'h3
? 3'h7
: entries_11_size == 3'h2
? 3'h3
: entries_11_size == 3'h1
? 3'h1
: entries_11_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_11_addr[2:0],
io_storeAddrValid & entries_10_valid & entries_10_completed & entries_10_addrValid
& entries_10_robIdx > io_storeRobIdx & entries_10_addr[63:3] == io_storeAddr[63:3]
& (entries_10_addr[2:0]
| (entries_10_size == 3'h3
? 3'h7
: entries_10_size == 3'h2
? 3'h3
: entries_10_size == 3'h1
? 3'h1
: entries_10_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_10_addr[2:0],
io_storeAddrValid & entries_9_valid & entries_9_completed & entries_9_addrValid
& entries_9_robIdx > io_storeRobIdx & entries_9_addr[63:3] == io_storeAddr[63:3]
& (entries_9_addr[2:0]
| (entries_9_size == 3'h3
? 3'h7
: entries_9_size == 3'h2
? 3'h3
: entries_9_size == 3'h1
? 3'h1
: entries_9_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_9_addr[2:0],
io_storeAddrValid & entries_8_valid & entries_8_completed & entries_8_addrValid
& entries_8_robIdx > io_storeRobIdx & entries_8_addr[63:3] == io_storeAddr[63:3]
& (entries_8_addr[2:0]
| (entries_8_size == 3'h3
? 3'h7
: entries_8_size == 3'h2
? 3'h3
: entries_8_size == 3'h1
? 3'h1
: entries_8_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_8_addr[2:0],
io_storeAddrValid & entries_7_valid & entries_7_completed & entries_7_addrValid
& entries_7_robIdx > io_storeRobIdx & entries_7_addr[63:3] == io_storeAddr[63:3]
& (entries_7_addr[2:0]
| (entries_7_size == 3'h3
? 3'h7
: entries_7_size == 3'h2
? 3'h3
: entries_7_size == 3'h1
? 3'h1
: entries_7_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_7_addr[2:0],
io_storeAddrValid & entries_6_valid & entries_6_completed & entries_6_addrValid
& entries_6_robIdx > io_storeRobIdx & entries_6_addr[63:3] == io_storeAddr[63:3]
& (entries_6_addr[2:0]
| (entries_6_size == 3'h3
? 3'h7
: entries_6_size == 3'h2
? 3'h3
: entries_6_size == 3'h1
? 3'h1
: entries_6_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_6_addr[2:0],
io_storeAddrValid & entries_5_valid & entries_5_completed & entries_5_addrValid
& entries_5_robIdx > io_storeRobIdx & entries_5_addr[63:3] == io_storeAddr[63:3]
& (entries_5_addr[2:0]
| (entries_5_size == 3'h3
? 3'h7
: entries_5_size == 3'h2
? 3'h3
: entries_5_size == 3'h1
? 3'h1
: entries_5_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_5_addr[2:0],
io_storeAddrValid & entries_4_valid & entries_4_completed & entries_4_addrValid
& entries_4_robIdx > io_storeRobIdx & entries_4_addr[63:3] == io_storeAddr[63:3]
& (entries_4_addr[2:0]
| (entries_4_size == 3'h3
? 3'h7
: entries_4_size == 3'h2
? 3'h3
: entries_4_size == 3'h1
? 3'h1
: entries_4_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_4_addr[2:0],
io_storeAddrValid & entries_3_valid & entries_3_completed & entries_3_addrValid
& entries_3_robIdx > io_storeRobIdx & entries_3_addr[63:3] == io_storeAddr[63:3]
& (entries_3_addr[2:0]
| (entries_3_size == 3'h3
? 3'h7
: entries_3_size == 3'h2
? 3'h3
: entries_3_size == 3'h1
? 3'h1
: entries_3_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_3_addr[2:0],
io_storeAddrValid & entries_2_valid & entries_2_completed & entries_2_addrValid
& entries_2_robIdx > io_storeRobIdx & entries_2_addr[63:3] == io_storeAddr[63:3]
& (entries_2_addr[2:0]
| (entries_2_size == 3'h3
? 3'h7
: entries_2_size == 3'h2
? 3'h3
: entries_2_size == 3'h1
? 3'h1
: entries_2_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_2_addr[2:0],
io_storeAddrValid & entries_1_valid & entries_1_completed & entries_1_addrValid
& entries_1_robIdx > io_storeRobIdx & entries_1_addr[63:3] == io_storeAddr[63:3]
& (entries_1_addr[2:0]
| (entries_1_size == 3'h3
? 3'h7
: entries_1_size == 3'h2
? 3'h3
: entries_1_size == 3'h1
? 3'h1
: entries_1_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_1_addr[2:0],
io_storeAddrValid & entries_0_valid & entries_0_completed & entries_0_addrValid
& entries_0_robIdx > io_storeRobIdx & entries_0_addr[63:3] == io_storeAddr[63:3]
& (entries_0_addr[2:0]
| (entries_0_size == 3'h3
? 3'h7
: entries_0_size == 3'h2
? 3'h3
: entries_0_size == 3'h1
? 3'h1
: entries_0_size == 3'h0 ? 3'h0 : 3'h7)) >= io_storeAddr[2:0]
& (io_storeAddr[2:0]
| (_violationVec_15_bm_T_6
? 3'h7
: _violationVec_15_bm_T_4
? 3'h3
: _violationVec_15_bm_T_2
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_0_addr[2:0]};
always @(posedge clock) begin
if (reset) begin
entries_0_valid <= 1'h0;
entries_0_robIdx <= 6'h0;
entries_0_addrValid <= 1'h0;
entries_0_addr <= 64'h0;
entries_0_size <= 3'h0;
entries_0_completed <= 1'h0;
entries_1_valid <= 1'h0;
entries_1_robIdx <= 6'h0;
entries_1_addrValid <= 1'h0;
entries_1_addr <= 64'h0;
entries_1_size <= 3'h0;
entries_1_completed <= 1'h0;
entries_2_valid <= 1'h0;
entries_2_robIdx <= 6'h0;
entries_2_addrValid <= 1'h0;
entries_2_addr <= 64'h0;
entries_2_size <= 3'h0;
entries_2_completed <= 1'h0;
entries_3_valid <= 1'h0;
entries_3_robIdx <= 6'h0;
entries_3_addrValid <= 1'h0;
entries_3_addr <= 64'h0;
entries_3_size <= 3'h0;
entries_3_completed <= 1'h0;
entries_4_valid <= 1'h0;
entries_4_robIdx <= 6'h0;
entries_4_addrValid <= 1'h0;
entries_4_addr <= 64'h0;
entries_4_size <= 3'h0;
entries_4_completed <= 1'h0;
entries_5_valid <= 1'h0;
entries_5_robIdx <= 6'h0;
entries_5_addrValid <= 1'h0;
entries_5_addr <= 64'h0;
entries_5_size <= 3'h0;
entries_5_completed <= 1'h0;
entries_6_valid <= 1'h0;
entries_6_robIdx <= 6'h0;
entries_6_addrValid <= 1'h0;
entries_6_addr <= 64'h0;
entries_6_size <= 3'h0;
entries_6_completed <= 1'h0;
entries_7_valid <= 1'h0;
entries_7_robIdx <= 6'h0;
entries_7_addrValid <= 1'h0;
entries_7_addr <= 64'h0;
entries_7_size <= 3'h0;
entries_7_completed <= 1'h0;
entries_8_valid <= 1'h0;
entries_8_robIdx <= 6'h0;
entries_8_addrValid <= 1'h0;
entries_8_addr <= 64'h0;
entries_8_size <= 3'h0;
entries_8_completed <= 1'h0;
entries_9_valid <= 1'h0;
entries_9_robIdx <= 6'h0;
entries_9_addrValid <= 1'h0;
entries_9_addr <= 64'h0;
entries_9_size <= 3'h0;
entries_9_completed <= 1'h0;
entries_10_valid <= 1'h0;
entries_10_robIdx <= 6'h0;
entries_10_addrValid <= 1'h0;
entries_10_addr <= 64'h0;
entries_10_size <= 3'h0;
entries_10_completed <= 1'h0;
entries_11_valid <= 1'h0;
entries_11_robIdx <= 6'h0;
entries_11_addrValid <= 1'h0;
entries_11_addr <= 64'h0;
entries_11_size <= 3'h0;
entries_11_completed <= 1'h0;
entries_12_valid <= 1'h0;
entries_12_robIdx <= 6'h0;
entries_12_addrValid <= 1'h0;
entries_12_addr <= 64'h0;
entries_12_size <= 3'h0;
entries_12_completed <= 1'h0;
entries_13_valid <= 1'h0;
entries_13_robIdx <= 6'h0;
entries_13_addrValid <= 1'h0;
entries_13_addr <= 64'h0;
entries_13_size <= 3'h0;
entries_13_completed <= 1'h0;
entries_14_valid <= 1'h0;
entries_14_robIdx <= 6'h0;
entries_14_addrValid <= 1'h0;
entries_14_addr <= 64'h0;
entries_14_size <= 3'h0;
entries_14_completed <= 1'h0;
entries_15_valid <= 1'h0;
entries_15_robIdx <= 6'h0;
entries_15_addrValid <= 1'h0;
entries_15_addr <= 64'h0;
entries_15_size <= 3'h0;
entries_15_completed <= 1'h0;
end
else begin
automatic logic _GEN =
io_enqValid
& (|{~entries_15_valid,
~entries_14_valid,
~entries_13_valid,
~entries_12_valid,
~entries_11_valid,
~entries_10_valid,
~entries_9_valid,
~entries_8_valid,
~entries_7_valid,
~entries_6_valid,
~entries_5_valid,
~entries_4_valid,
~entries_3_valid,
~entries_2_valid,
~entries_1_valid,
~entries_0_valid});
automatic logic _GEN_0;
automatic logic _GEN_1;
automatic logic _GEN_2;
automatic logic _GEN_3;
automatic logic _GEN_4;
automatic logic _GEN_5;
automatic logic _GEN_6;
automatic logic _GEN_7;
automatic logic _GEN_8;
automatic logic _GEN_9;
automatic logic _GEN_10;
automatic logic _GEN_11;
automatic logic _GEN_12;
automatic logic _GEN_13;
automatic logic _GEN_14;
automatic logic _GEN_15;
automatic logic _GEN_16;
automatic logic _GEN_17;
automatic logic _GEN_18;
automatic logic _GEN_19;
automatic logic _GEN_20;
automatic logic _GEN_21;
automatic logic _GEN_22;
automatic logic _GEN_23;
automatic logic _GEN_24;
automatic logic _GEN_25;
automatic logic _GEN_26;
automatic logic _GEN_27;
automatic logic _GEN_28;
automatic logic _GEN_29;
automatic logic _GEN_30;
automatic logic _GEN_31;
_GEN_0 = _GEN & enqIdx == 4'h0;
_GEN_1 = _GEN & enqIdx == 4'h1;
_GEN_2 = _GEN & enqIdx == 4'h2;
_GEN_3 = _GEN & enqIdx == 4'h3;
_GEN_4 = _GEN & enqIdx == 4'h4;
_GEN_5 = _GEN & enqIdx == 4'h5;
_GEN_6 = _GEN & enqIdx == 4'h6;
_GEN_7 = _GEN & enqIdx == 4'h7;
_GEN_8 = _GEN & enqIdx == 4'h8;
_GEN_9 = _GEN & enqIdx == 4'h9;
_GEN_10 = _GEN & enqIdx == 4'hA;
_GEN_11 = _GEN & enqIdx == 4'hB;
_GEN_12 = _GEN & enqIdx == 4'hC;
_GEN_13 = _GEN & enqIdx == 4'hD;
_GEN_14 = _GEN & enqIdx == 4'hE;
_GEN_15 = _GEN & (&enqIdx);
_GEN_16 = io_addrValid & io_addrIdx == 4'h0;
_GEN_17 = io_addrValid & io_addrIdx == 4'h1;
_GEN_18 = io_addrValid & io_addrIdx == 4'h2;
_GEN_19 = io_addrValid & io_addrIdx == 4'h3;
_GEN_20 = io_addrValid & io_addrIdx == 4'h4;
_GEN_21 = io_addrValid & io_addrIdx == 4'h5;
_GEN_22 = io_addrValid & io_addrIdx == 4'h6;
_GEN_23 = io_addrValid & io_addrIdx == 4'h7;
_GEN_24 = io_addrValid & io_addrIdx == 4'h8;
_GEN_25 = io_addrValid & io_addrIdx == 4'h9;
_GEN_26 = io_addrValid & io_addrIdx == 4'hA;
_GEN_27 = io_addrValid & io_addrIdx == 4'hB;
_GEN_28 = io_addrValid & io_addrIdx == 4'hC;
_GEN_29 = io_addrValid & io_addrIdx == 4'hD;
_GEN_30 = io_addrValid & io_addrIdx == 4'hE;
_GEN_31 = io_addrValid & (&io_addrIdx);
entries_0_valid <= ~io_flush & (_GEN_0 | entries_0_valid);
if (io_flush) begin
entries_0_robIdx <= 6'h0;
entries_0_addr <= 64'h0;
entries_0_size <= 3'h0;
entries_1_robIdx <= 6'h0;
entries_1_addr <= 64'h0;
entries_1_size <= 3'h0;
entries_2_robIdx <= 6'h0;
entries_2_addr <= 64'h0;
entries_2_size <= 3'h0;
entries_3_robIdx <= 6'h0;
entries_3_addr <= 64'h0;
entries_3_size <= 3'h0;
entries_4_robIdx <= 6'h0;
entries_4_addr <= 64'h0;
entries_4_size <= 3'h0;
entries_5_robIdx <= 6'h0;
entries_5_addr <= 64'h0;
entries_5_size <= 3'h0;
entries_6_robIdx <= 6'h0;
entries_6_addr <= 64'h0;
entries_6_size <= 3'h0;
entries_7_robIdx <= 6'h0;
entries_7_addr <= 64'h0;
entries_7_size <= 3'h0;
entries_8_robIdx <= 6'h0;
entries_8_addr <= 64'h0;
entries_8_size <= 3'h0;
entries_9_robIdx <= 6'h0;
entries_9_addr <= 64'h0;
entries_9_size <= 3'h0;
entries_10_robIdx <= 6'h0;
entries_10_addr <= 64'h0;
entries_10_size <= 3'h0;
entries_11_robIdx <= 6'h0;
entries_11_addr <= 64'h0;
entries_11_size <= 3'h0;
entries_12_robIdx <= 6'h0;
entries_12_addr <= 64'h0;
entries_12_size <= 3'h0;
entries_13_robIdx <= 6'h0;
entries_13_addr <= 64'h0;
entries_13_size <= 3'h0;
entries_14_robIdx <= 6'h0;
entries_14_addr <= 64'h0;
entries_14_size <= 3'h0;
entries_15_robIdx <= 6'h0;
entries_15_addr <= 64'h0;
entries_15_size <= 3'h0;
end
else begin
if (_GEN_0)
entries_0_robIdx <= io_enqRobIdx;
if (_GEN_16) begin
entries_0_addr <= io_addr;
entries_0_size <= io_size;
end
if (_GEN_1)
entries_1_robIdx <= io_enqRobIdx;
if (_GEN_17) begin
entries_1_addr <= io_addr;
entries_1_size <= io_size;
end
if (_GEN_2)
entries_2_robIdx <= io_enqRobIdx;
if (_GEN_18) begin
entries_2_addr <= io_addr;
entries_2_size <= io_size;
end
if (_GEN_3)
entries_3_robIdx <= io_enqRobIdx;
if (_GEN_19) begin
entries_3_addr <= io_addr;
entries_3_size <= io_size;
end
if (_GEN_4)
entries_4_robIdx <= io_enqRobIdx;
if (_GEN_20) begin
entries_4_addr <= io_addr;
entries_4_size <= io_size;
end
if (_GEN_5)
entries_5_robIdx <= io_enqRobIdx;
if (_GEN_21) begin
entries_5_addr <= io_addr;
entries_5_size <= io_size;
end
if (_GEN_6)
entries_6_robIdx <= io_enqRobIdx;
if (_GEN_22) begin
entries_6_addr <= io_addr;
entries_6_size <= io_size;
end
if (_GEN_7)
entries_7_robIdx <= io_enqRobIdx;
if (_GEN_23) begin
entries_7_addr <= io_addr;
entries_7_size <= io_size;
end
if (_GEN_8)
entries_8_robIdx <= io_enqRobIdx;
if (_GEN_24) begin
entries_8_addr <= io_addr;
entries_8_size <= io_size;
end
if (_GEN_9)
entries_9_robIdx <= io_enqRobIdx;
if (_GEN_25) begin
entries_9_addr <= io_addr;
entries_9_size <= io_size;
end
if (_GEN_10)
entries_10_robIdx <= io_enqRobIdx;
if (_GEN_26) begin
entries_10_addr <= io_addr;
entries_10_size <= io_size;
end
if (_GEN_11)
entries_11_robIdx <= io_enqRobIdx;
if (_GEN_27) begin
entries_11_addr <= io_addr;
entries_11_size <= io_size;
end
if (_GEN_12)
entries_12_robIdx <= io_enqRobIdx;
if (_GEN_28) begin
entries_12_addr <= io_addr;
entries_12_size <= io_size;
end
if (_GEN_13)
entries_13_robIdx <= io_enqRobIdx;
if (_GEN_29) begin
entries_13_addr <= io_addr;
entries_13_size <= io_size;
end
if (_GEN_14)
entries_14_robIdx <= io_enqRobIdx;
if (_GEN_30) begin
entries_14_addr <= io_addr;
entries_14_size <= io_size;
end
if (_GEN_15)
entries_15_robIdx <= io_enqRobIdx;
if (_GEN_31) begin
entries_15_addr <= io_addr;
entries_15_size <= io_size;
end
end
entries_0_addrValid <= ~io_flush & (_GEN_16 | ~_GEN_0 & entries_0_addrValid);
entries_0_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h0 | ~_GEN_0 & entries_0_completed);
entries_1_valid <= ~io_flush & (_GEN_1 | entries_1_valid);
entries_1_addrValid <= ~io_flush & (_GEN_17 | ~_GEN_1 & entries_1_addrValid);
entries_1_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h1 | ~_GEN_1 & entries_1_completed);
entries_2_valid <= ~io_flush & (_GEN_2 | entries_2_valid);
entries_2_addrValid <= ~io_flush & (_GEN_18 | ~_GEN_2 & entries_2_addrValid);
entries_2_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h2 | ~_GEN_2 & entries_2_completed);
entries_3_valid <= ~io_flush & (_GEN_3 | entries_3_valid);
entries_3_addrValid <= ~io_flush & (_GEN_19 | ~_GEN_3 & entries_3_addrValid);
entries_3_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h3 | ~_GEN_3 & entries_3_completed);
entries_4_valid <= ~io_flush & (_GEN_4 | entries_4_valid);
entries_4_addrValid <= ~io_flush & (_GEN_20 | ~_GEN_4 & entries_4_addrValid);
entries_4_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h4 | ~_GEN_4 & entries_4_completed);
entries_5_valid <= ~io_flush & (_GEN_5 | entries_5_valid);
entries_5_addrValid <= ~io_flush & (_GEN_21 | ~_GEN_5 & entries_5_addrValid);
entries_5_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h5 | ~_GEN_5 & entries_5_completed);
entries_6_valid <= ~io_flush & (_GEN_6 | entries_6_valid);
entries_6_addrValid <= ~io_flush & (_GEN_22 | ~_GEN_6 & entries_6_addrValid);
entries_6_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h6 | ~_GEN_6 & entries_6_completed);
entries_7_valid <= ~io_flush & (_GEN_7 | entries_7_valid);
entries_7_addrValid <= ~io_flush & (_GEN_23 | ~_GEN_7 & entries_7_addrValid);
entries_7_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h7 | ~_GEN_7 & entries_7_completed);
entries_8_valid <= ~io_flush & (_GEN_8 | entries_8_valid);
entries_8_addrValid <= ~io_flush & (_GEN_24 | ~_GEN_8 & entries_8_addrValid);
entries_8_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h8 | ~_GEN_8 & entries_8_completed);
entries_9_valid <= ~io_flush & (_GEN_9 | entries_9_valid);
entries_9_addrValid <= ~io_flush & (_GEN_25 | ~_GEN_9 & entries_9_addrValid);
entries_9_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h9 | ~_GEN_9 & entries_9_completed);
entries_10_valid <= ~io_flush & (_GEN_10 | entries_10_valid);
entries_10_addrValid <= ~io_flush & (_GEN_26 | ~_GEN_10 & entries_10_addrValid);
entries_10_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'hA | ~_GEN_10 & entries_10_completed);
entries_11_valid <= ~io_flush & (_GEN_11 | entries_11_valid);
entries_11_addrValid <= ~io_flush & (_GEN_27 | ~_GEN_11 & entries_11_addrValid);
entries_11_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'hB | ~_GEN_11 & entries_11_completed);
entries_12_valid <= ~io_flush & (_GEN_12 | entries_12_valid);
entries_12_addrValid <= ~io_flush & (_GEN_28 | ~_GEN_12 & entries_12_addrValid);
entries_12_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'hC | ~_GEN_12 & entries_12_completed);
entries_13_valid <= ~io_flush & (_GEN_13 | entries_13_valid);
entries_13_addrValid <= ~io_flush & (_GEN_29 | ~_GEN_13 & entries_13_addrValid);
entries_13_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'hD | ~_GEN_13 & entries_13_completed);
entries_14_valid <= ~io_flush & (_GEN_14 | entries_14_valid);
entries_14_addrValid <= ~io_flush & (_GEN_30 | ~_GEN_14 & entries_14_addrValid);
entries_14_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'hE | ~_GEN_14 & entries_14_completed);
entries_15_valid <= ~io_flush & (_GEN_15 | entries_15_valid);
entries_15_addrValid <= ~io_flush & (_GEN_31 | ~_GEN_15 & entries_15_addrValid);
entries_15_completed <=
~io_flush & (io_complete & (&io_completeIdx) | ~_GEN_15 & entries_15_completed);
end
end // always @(posedge)
assign io_enqIdx = enqIdx;
assign io_violation = |_io_violation_T;
endmodule

42
generated-ooo/MMU.sv Normal file
View File

@@ -0,0 +1,42 @@
// Generated by CIRCT firtool-1.139.0
module MMU(
input clock,
reset,
input [63:0] io_satp,
input io_req_valid,
input [63:0] io_req_vaddr,
input io_req_isStore,
output io_resp_pageFault,
io_ptwMemReq_valid,
output [63:0] io_ptwMemReq_addr,
input io_ptwMemResp_valid,
input [63:0] io_ptwMemResp_data,
output io_refill_valid,
output [26:0] io_refill_vpn,
output [43:0] io_refill_ppn,
output [7:0] io_refill_flags
);
wire _walker_io_respValid;
wire _walker_io_pageFault;
PageTableWalker walker (
.clock (clock),
.reset (reset),
.io_reqValid (io_req_valid & (|(io_satp[63:60]))),
.io_reqVpn (io_req_vaddr[38:12]),
.io_isStore (io_req_isStore),
.io_satp (io_satp),
.io_memReq_valid (io_ptwMemReq_valid),
.io_memReq_addr (io_ptwMemReq_addr),
.io_memResp_valid (io_ptwMemResp_valid),
.io_memResp_data (io_ptwMemResp_data),
.io_respValid (_walker_io_respValid),
.io_refill_valid (io_refill_valid),
.io_refill_vpn (io_refill_vpn),
.io_refill_ppn (io_refill_ppn),
.io_refill_flags (io_refill_flags),
.io_pageFault (_walker_io_pageFault)
);
assign io_resp_pageFault = _walker_io_respValid & _walker_io_pageFault;
endmodule

969
generated-ooo/OoOBackend.sv Normal file
View File

@@ -0,0 +1,969 @@
// Generated by CIRCT firtool-1.139.0
module OoOBackend(
input clock,
reset,
io_decodeValid_0,
io_decodeValid_1,
input [63:0] io_decode_0_pc,
input [31:0] io_decode_0_inst,
input [4:0] io_decode_0_rs1,
io_decode_0_rs2,
io_decode_0_rd,
input [2:0] io_decode_0_funct3,
input [63:0] io_decode_0_immI,
io_decode_0_immS,
io_decode_0_immB,
io_decode_0_immU,
io_decode_0_immJ,
input [3:0] io_decode_0_opClass,
input [4:0] io_decode_0_aluFn,
input [2:0] io_decode_0_memWidth,
input io_decode_0_isLoad,
io_decode_0_isStore,
io_decode_0_isBranch,
io_decode_0_isJal,
io_decode_0_isJalr,
io_decode_0_isLui,
io_decode_0_isAuipc,
io_decode_0_isOpImm,
io_decode_0_isWord,
io_decode_0_isSystem,
io_decode_0_writesRd,
io_decode_0_illegal,
input [63:0] io_decode_1_pc,
input [31:0] io_decode_1_inst,
input [4:0] io_decode_1_rs1,
io_decode_1_rs2,
io_decode_1_rd,
input [2:0] io_decode_1_funct3,
input [63:0] io_decode_1_immI,
io_decode_1_immS,
io_decode_1_immB,
io_decode_1_immU,
io_decode_1_immJ,
input [3:0] io_decode_1_opClass,
input [4:0] io_decode_1_aluFn,
input [2:0] io_decode_1_memWidth,
input io_decode_1_isLoad,
io_decode_1_isStore,
io_decode_1_isBranch,
io_decode_1_isJal,
io_decode_1_isJalr,
io_decode_1_isLui,
io_decode_1_isAuipc,
io_decode_1_isOpImm,
io_decode_1_isWord,
io_decode_1_isSystem,
io_decode_1_writesRd,
io_decode_1_illegal,
output io_decodeReady,
io_flush,
output [63:0] io_redirectPc,
output io_dmemReqValid,
output [63:0] io_dmemReq_addr,
io_dmemReq_data,
output io_dmemReq_isStore,
output [2:0] io_dmemReq_size,
input io_dmemRespValid,
input [63:0] io_dmemRespData
);
wire [63:0] _csr_io_rdata;
wire [63:0] _csr_io_satp;
wire [63:0] _csr_io_mtvec;
wire [63:0] _csr_io_mepc;
wire _lsu_io_reqReady;
wire _lsu_io_respValid;
wire [63:0] _lsu_io_respData;
wire _lsu_io_pageFault;
wire [3:0] _sq_io_enqIdx;
wire _sq_io_forwardValid;
wire _sq_io_drainValid;
wire [63:0] _sq_io_drain_addr;
wire [63:0] _sq_io_drain_data;
wire [2:0] _sq_io_drain_size;
wire [3:0] _lq_io_enqIdx;
wire _lq_io_violation;
wire _commit_io_commitReady_0;
wire _commit_io_commitReady_1;
wire _commit_io_freeOldPhys_0;
wire _commit_io_freeOldPhys_1;
wire [5:0] _commit_io_oldPhys_0;
wire [5:0] _commit_io_oldPhys_1;
wire _commit_io_commitMapValid_0;
wire _commit_io_commitMapValid_1;
wire [4:0] _commit_io_commitArch_0;
wire [4:0] _commit_io_commitArch_1;
wire [5:0] _commit_io_commitPhys_0;
wire [5:0] _commit_io_commitPhys_1;
wire _commit_io_flush;
wire [63:0] _commit_io_redirectPc;
wire _commit_io_exception;
wire [63:0] _commit_io_exceptionCause;
wire [63:0] _commit_io_badAddr;
wire _wb_1_io_wen;
wire [5:0] _wb_1_io_waddr;
wire [63:0] _wb_1_io_wdata;
wire _wb_0_io_wen;
wire [5:0] _wb_0_io_waddr;
wire [63:0] _wb_0_io_wdata;
wire _exec_1_io_outValid;
wire [63:0] _exec_1_io_result;
wire _exec_1_io_branchTaken;
wire _exec_0_io_outValid;
wire [63:0] _exec_0_io_result;
wire _exec_0_io_branchTaken;
wire [63:0] _prf_io_rdata_0;
wire [63:0] _prf_io_rdata_1;
wire [63:0] _prf_io_rdata_2;
wire [63:0] _prf_io_rdata_3;
wire _issue_io_inReady_0;
wire _issue_io_inReady_1;
wire _issue_io_outValid_0;
wire _issue_io_outValid_1;
wire [63:0] _issue_io_out_0_decoded_pc;
wire [31:0] _issue_io_out_0_decoded_inst;
wire [4:0] _issue_io_out_0_decoded_rs1;
wire [2:0] _issue_io_out_0_decoded_funct3;
wire [63:0] _issue_io_out_0_decoded_immI;
wire [63:0] _issue_io_out_0_decoded_immS;
wire [63:0] _issue_io_out_0_decoded_immB;
wire [63:0] _issue_io_out_0_decoded_immU;
wire [63:0] _issue_io_out_0_decoded_immJ;
wire [4:0] _issue_io_out_0_decoded_aluFn;
wire [2:0] _issue_io_out_0_decoded_memWidth;
wire _issue_io_out_0_decoded_isLoad;
wire _issue_io_out_0_decoded_isStore;
wire _issue_io_out_0_decoded_isBranch;
wire _issue_io_out_0_decoded_isJal;
wire _issue_io_out_0_decoded_isJalr;
wire _issue_io_out_0_decoded_isLui;
wire _issue_io_out_0_decoded_isAuipc;
wire _issue_io_out_0_decoded_isOpImm;
wire _issue_io_out_0_decoded_isWord;
wire _issue_io_out_0_decoded_isSystem;
wire _issue_io_out_0_decoded_writesRd;
wire _issue_io_out_0_decoded_illegal;
wire [5:0] _issue_io_out_0_prs1;
wire [5:0] _issue_io_out_0_prs2;
wire [5:0] _issue_io_out_0_prd;
wire [5:0] _issue_io_out_0_robIdx;
wire [63:0] _issue_io_out_1_decoded_pc;
wire [31:0] _issue_io_out_1_decoded_inst;
wire [4:0] _issue_io_out_1_decoded_rs1;
wire [2:0] _issue_io_out_1_decoded_funct3;
wire [63:0] _issue_io_out_1_decoded_immI;
wire [63:0] _issue_io_out_1_decoded_immS;
wire [63:0] _issue_io_out_1_decoded_immB;
wire [63:0] _issue_io_out_1_decoded_immU;
wire [63:0] _issue_io_out_1_decoded_immJ;
wire [4:0] _issue_io_out_1_decoded_aluFn;
wire [2:0] _issue_io_out_1_decoded_memWidth;
wire _issue_io_out_1_decoded_isLoad;
wire _issue_io_out_1_decoded_isStore;
wire _issue_io_out_1_decoded_isBranch;
wire _issue_io_out_1_decoded_isJal;
wire _issue_io_out_1_decoded_isJalr;
wire _issue_io_out_1_decoded_isLui;
wire _issue_io_out_1_decoded_isAuipc;
wire _issue_io_out_1_decoded_isOpImm;
wire _issue_io_out_1_decoded_isWord;
wire _issue_io_out_1_decoded_isSystem;
wire _issue_io_out_1_decoded_writesRd;
wire _issue_io_out_1_decoded_illegal;
wire [5:0] _issue_io_out_1_prs1;
wire [5:0] _issue_io_out_1_prs2;
wire [5:0] _issue_io_out_1_prd;
wire [5:0] _issue_io_out_1_robIdx;
wire _rename_io_outValid_0;
wire _rename_io_outValid_1;
wire [63:0] _rename_io_out_0_decoded_pc;
wire [31:0] _rename_io_out_0_decoded_inst;
wire [4:0] _rename_io_out_0_decoded_rs1;
wire [4:0] _rename_io_out_0_decoded_rs2;
wire [2:0] _rename_io_out_0_decoded_funct3;
wire [63:0] _rename_io_out_0_decoded_immI;
wire [63:0] _rename_io_out_0_decoded_immS;
wire [63:0] _rename_io_out_0_decoded_immB;
wire [63:0] _rename_io_out_0_decoded_immU;
wire [63:0] _rename_io_out_0_decoded_immJ;
wire [4:0] _rename_io_out_0_decoded_aluFn;
wire [2:0] _rename_io_out_0_decoded_memWidth;
wire _rename_io_out_0_decoded_isLoad;
wire _rename_io_out_0_decoded_isStore;
wire _rename_io_out_0_decoded_isBranch;
wire _rename_io_out_0_decoded_isJal;
wire _rename_io_out_0_decoded_isJalr;
wire _rename_io_out_0_decoded_isLui;
wire _rename_io_out_0_decoded_isAuipc;
wire _rename_io_out_0_decoded_isOpImm;
wire _rename_io_out_0_decoded_isWord;
wire _rename_io_out_0_decoded_isSystem;
wire _rename_io_out_0_decoded_writesRd;
wire _rename_io_out_0_decoded_illegal;
wire [5:0] _rename_io_out_0_prs1;
wire [5:0] _rename_io_out_0_prs2;
wire _rename_io_out_0_src1Ready;
wire _rename_io_out_0_src2Ready;
wire [5:0] _rename_io_out_0_prd;
wire [5:0] _rename_io_out_0_robIdx;
wire [63:0] _rename_io_out_1_decoded_pc;
wire [31:0] _rename_io_out_1_decoded_inst;
wire [4:0] _rename_io_out_1_decoded_rs1;
wire [4:0] _rename_io_out_1_decoded_rs2;
wire [2:0] _rename_io_out_1_decoded_funct3;
wire [63:0] _rename_io_out_1_decoded_immI;
wire [63:0] _rename_io_out_1_decoded_immS;
wire [63:0] _rename_io_out_1_decoded_immB;
wire [63:0] _rename_io_out_1_decoded_immU;
wire [63:0] _rename_io_out_1_decoded_immJ;
wire [4:0] _rename_io_out_1_decoded_aluFn;
wire [2:0] _rename_io_out_1_decoded_memWidth;
wire _rename_io_out_1_decoded_isLoad;
wire _rename_io_out_1_decoded_isStore;
wire _rename_io_out_1_decoded_isBranch;
wire _rename_io_out_1_decoded_isJal;
wire _rename_io_out_1_decoded_isJalr;
wire _rename_io_out_1_decoded_isLui;
wire _rename_io_out_1_decoded_isAuipc;
wire _rename_io_out_1_decoded_isOpImm;
wire _rename_io_out_1_decoded_isWord;
wire _rename_io_out_1_decoded_isSystem;
wire _rename_io_out_1_decoded_writesRd;
wire _rename_io_out_1_decoded_illegal;
wire [5:0] _rename_io_out_1_prs1;
wire [5:0] _rename_io_out_1_prs2;
wire _rename_io_out_1_src1Ready;
wire _rename_io_out_1_src2Ready;
wire [5:0] _rename_io_out_1_prd;
wire [5:0] _rename_io_out_1_robIdx;
wire _rename_io_canAccept;
wire _rename_io_commitValid_0;
wire _rename_io_commitValid_1;
wire [5:0] _rename_io_commitEntry_0_robIdx;
wire [4:0] _rename_io_commitEntry_0_archDest;
wire _rename_io_commitEntry_0_writesDest;
wire [3:0] _rename_io_commitEntry_0_opClass;
wire [5:0] _rename_io_commitEntry_0_dest;
wire [5:0] _rename_io_commitEntry_0_oldDest;
wire _rename_io_commitEntry_0_exception;
wire [63:0] _rename_io_commitEntry_0_exceptionCause;
wire [63:0] _rename_io_commitEntry_0_badAddr;
wire _rename_io_commitEntry_0_branchMispredict;
wire [63:0] _rename_io_commitEntry_0_redirectPc;
wire _rename_io_commitEntry_0_csrValid;
wire [11:0] _rename_io_commitEntry_0_csrAddr;
wire [2:0] _rename_io_commitEntry_0_csrCmd;
wire [63:0] _rename_io_commitEntry_0_csrRs1;
wire [4:0] _rename_io_commitEntry_0_csrZimm;
wire [5:0] _rename_io_commitEntry_1_robIdx;
wire [4:0] _rename_io_commitEntry_1_archDest;
wire _rename_io_commitEntry_1_writesDest;
wire [3:0] _rename_io_commitEntry_1_opClass;
wire [5:0] _rename_io_commitEntry_1_dest;
wire [5:0] _rename_io_commitEntry_1_oldDest;
wire _rename_io_commitEntry_1_exception;
wire [63:0] _rename_io_commitEntry_1_exceptionCause;
wire [63:0] _rename_io_commitEntry_1_badAddr;
wire _rename_io_commitEntry_1_branchMispredict;
wire [63:0] _rename_io_commitEntry_1_redirectPc;
wire _rename_io_commitEntry_1_csrValid;
wire [11:0] _rename_io_commitEntry_1_csrAddr;
wire [2:0] _rename_io_commitEntry_1_csrCmd;
wire [63:0] _rename_io_commitEntry_1_csrRs1;
wire [4:0] _rename_io_commitEntry_1_csrZimm;
reg wakeupReg_0_valid;
reg [5:0] wakeupReg_0_phys;
reg wakeupReg_1_valid;
reg [5:0] wakeupReg_1_phys;
reg loadPending;
reg [5:0] loadPendingRob;
reg [5:0] loadPendingPhys;
reg [3:0] loadPendingLq;
wire loadRespValid = _lsu_io_respValid & loadPending;
wire isMem0 = _issue_io_out_0_decoded_isLoad | _issue_io_out_0_decoded_isStore;
wire memIssue_0 = _issue_io_outValid_0 & isMem0;
wire isMem1 = _issue_io_out_1_decoded_isLoad | _issue_io_out_1_decoded_isStore;
wire csrReadReq_0 =
_issue_io_outValid_0 & _issue_io_out_0_decoded_isSystem
& (|_issue_io_out_0_decoded_funct3);
wire _memReady1_T_1 = _lsu_io_reqReady & ~loadPending;
wire issue_io_outReady_0 = ~isMem0 | _memReady1_T_1;
wire issue_io_outReady_1 =
(~isMem1 | _memReady1_T_1 & ~memIssue_0)
& ~(csrReadReq_0 & _issue_io_outValid_1 & _issue_io_out_1_decoded_isSystem
& (|_issue_io_out_1_decoded_funct3));
wire issueFire_0 = _issue_io_outValid_0 & issue_io_outReady_0;
wire issueFire_1 = _issue_io_outValid_1 & issue_io_outReady_1;
wire [2:0] sq_io_size =
memIssue_0 ? _issue_io_out_0_decoded_memWidth : _issue_io_out_1_decoded_memWidth;
wire _GEN =
memIssue_0 ? _issue_io_out_0_decoded_isStore : _issue_io_out_1_decoded_isStore;
wire [5:0] sq_io_enqRobIdx =
memIssue_0 ? _issue_io_out_0_robIdx : _issue_io_out_1_robIdx;
wire [63:0] _memAddr_T_1 =
(memIssue_0 ? _prf_io_rdata_0 : _prf_io_rdata_2)
+ (_GEN
? (memIssue_0 ? _issue_io_out_0_decoded_immS : _issue_io_out_1_decoded_immS)
: memIssue_0 ? _issue_io_out_0_decoded_immI : _issue_io_out_1_decoded_immI);
wire _storeEnq_T = memIssue_0 | ~memIssue_0 & _issue_io_outValid_1 & isMem1;
wire _GEN_0 = memIssue_0 ? issue_io_outReady_0 : issue_io_outReady_1;
wire loadEnq =
_storeEnq_T
& (memIssue_0 ? _issue_io_out_0_decoded_isLoad : _issue_io_out_1_decoded_isLoad)
& _GEN_0;
wire storeEnq = _storeEnq_T & _GEN & _GEN_0;
wire lsuLoadReq = loadEnq & ~_sq_io_forwardValid;
wire _commitCsr0_T = _commit_io_commitReady_0 & _rename_io_commitValid_0;
wire commitStore0 = _commitCsr0_T & _rename_io_commitEntry_0_opClass == 4'h4;
wire _commitCsr1_T = _commit_io_commitReady_1 & _rename_io_commitValid_1;
wire commitCsr0 = _commitCsr0_T & _rename_io_commitEntry_0_csrValid;
wire _completeMispredict_0_T =
_issue_io_out_0_decoded_isJal | _issue_io_out_0_decoded_isJalr;
wire [63:0] _branchRedirect_T_1 = _issue_io_out_0_decoded_pc + 64'h4;
wire [63:0] _jalrTarget_T = _prf_io_rdata_0 + _issue_io_out_0_decoded_immI;
wire _completeMispredict_0_T_2 =
_issue_io_out_0_decoded_isBranch & _exec_0_io_branchTaken;
wire isEcall = _issue_io_out_0_decoded_inst == 32'h73;
wire isEbreak = _issue_io_out_0_decoded_inst == 32'h100073;
wire isMret = _issue_io_out_0_decoded_inst == 32'h30200073;
wire _completeCause_0_T = loadRespValid & _lsu_io_pageFault;
wire _completeMispredict_1_T =
_issue_io_out_1_decoded_isJal | _issue_io_out_1_decoded_isJalr;
wire [63:0] _branchRedirect_T_6 = _issue_io_out_1_decoded_pc + 64'h4;
wire [63:0] _jalrTarget_T_3 = _prf_io_rdata_2 + _issue_io_out_1_decoded_immI;
wire _completeMispredict_1_T_2 =
_issue_io_out_1_decoded_isBranch & _exec_1_io_branchTaken;
wire isEcall_1 = _issue_io_out_1_decoded_inst == 32'h73;
wire isEbreak_1 = _issue_io_out_1_decoded_inst == 32'h100073;
wire isMret_1 = _issue_io_out_1_decoded_inst == 32'h30200073;
always @(posedge clock) begin
automatic logic _GEN_1;
_GEN_1 = loadEnq & ~_sq_io_forwardValid;
if (reset) begin
wakeupReg_0_valid <= 1'h0;
wakeupReg_0_phys <= 6'h0;
wakeupReg_1_valid <= 1'h0;
wakeupReg_1_phys <= 6'h0;
loadPending <= 1'h0;
end
else begin
wakeupReg_0_valid <= _wb_0_io_wen;
wakeupReg_0_phys <= _wb_0_io_waddr;
wakeupReg_1_valid <= _wb_1_io_wen;
wakeupReg_1_phys <= _wb_1_io_waddr;
loadPending <= ~_commit_io_flush & (_GEN_1 | ~loadRespValid & loadPending);
end
if (_commit_io_flush | ~_GEN_1) begin
end
else begin
loadPendingRob <= sq_io_enqRobIdx;
loadPendingPhys <= memIssue_0 ? _issue_io_out_0_prd : _issue_io_out_1_prd;
loadPendingLq <= _lq_io_enqIdx;
end
end // always @(posedge)
RenameStage rename (
.clock (clock),
.reset (reset),
.io_inValid_0 (io_decodeValid_0 & _issue_io_inReady_0),
.io_inValid_1 (io_decodeValid_1 & _issue_io_inReady_1),
.io_in_0_pc (io_decode_0_pc),
.io_in_0_inst (io_decode_0_inst),
.io_in_0_rs1 (io_decode_0_rs1),
.io_in_0_rs2 (io_decode_0_rs2),
.io_in_0_rd (io_decode_0_rd),
.io_in_0_funct3 (io_decode_0_funct3),
.io_in_0_immI (io_decode_0_immI),
.io_in_0_immS (io_decode_0_immS),
.io_in_0_immB (io_decode_0_immB),
.io_in_0_immU (io_decode_0_immU),
.io_in_0_immJ (io_decode_0_immJ),
.io_in_0_opClass (io_decode_0_opClass),
.io_in_0_aluFn (io_decode_0_aluFn),
.io_in_0_memWidth (io_decode_0_memWidth),
.io_in_0_isLoad (io_decode_0_isLoad),
.io_in_0_isStore (io_decode_0_isStore),
.io_in_0_isBranch (io_decode_0_isBranch),
.io_in_0_isJal (io_decode_0_isJal),
.io_in_0_isJalr (io_decode_0_isJalr),
.io_in_0_isLui (io_decode_0_isLui),
.io_in_0_isAuipc (io_decode_0_isAuipc),
.io_in_0_isOpImm (io_decode_0_isOpImm),
.io_in_0_isWord (io_decode_0_isWord),
.io_in_0_isSystem (io_decode_0_isSystem),
.io_in_0_writesRd (io_decode_0_writesRd),
.io_in_0_illegal (io_decode_0_illegal),
.io_in_1_pc (io_decode_1_pc),
.io_in_1_inst (io_decode_1_inst),
.io_in_1_rs1 (io_decode_1_rs1),
.io_in_1_rs2 (io_decode_1_rs2),
.io_in_1_rd (io_decode_1_rd),
.io_in_1_funct3 (io_decode_1_funct3),
.io_in_1_immI (io_decode_1_immI),
.io_in_1_immS (io_decode_1_immS),
.io_in_1_immB (io_decode_1_immB),
.io_in_1_immU (io_decode_1_immU),
.io_in_1_immJ (io_decode_1_immJ),
.io_in_1_opClass (io_decode_1_opClass),
.io_in_1_aluFn (io_decode_1_aluFn),
.io_in_1_memWidth (io_decode_1_memWidth),
.io_in_1_isLoad (io_decode_1_isLoad),
.io_in_1_isStore (io_decode_1_isStore),
.io_in_1_isBranch (io_decode_1_isBranch),
.io_in_1_isJal (io_decode_1_isJal),
.io_in_1_isJalr (io_decode_1_isJalr),
.io_in_1_isLui (io_decode_1_isLui),
.io_in_1_isAuipc (io_decode_1_isAuipc),
.io_in_1_isOpImm (io_decode_1_isOpImm),
.io_in_1_isWord (io_decode_1_isWord),
.io_in_1_isSystem (io_decode_1_isSystem),
.io_in_1_writesRd (io_decode_1_writesRd),
.io_in_1_illegal (io_decode_1_illegal),
.io_outValid_0 (_rename_io_outValid_0),
.io_outValid_1 (_rename_io_outValid_1),
.io_out_0_decoded_pc (_rename_io_out_0_decoded_pc),
.io_out_0_decoded_inst (_rename_io_out_0_decoded_inst),
.io_out_0_decoded_rs1 (_rename_io_out_0_decoded_rs1),
.io_out_0_decoded_rs2 (_rename_io_out_0_decoded_rs2),
.io_out_0_decoded_funct3 (_rename_io_out_0_decoded_funct3),
.io_out_0_decoded_immI (_rename_io_out_0_decoded_immI),
.io_out_0_decoded_immS (_rename_io_out_0_decoded_immS),
.io_out_0_decoded_immB (_rename_io_out_0_decoded_immB),
.io_out_0_decoded_immU (_rename_io_out_0_decoded_immU),
.io_out_0_decoded_immJ (_rename_io_out_0_decoded_immJ),
.io_out_0_decoded_aluFn (_rename_io_out_0_decoded_aluFn),
.io_out_0_decoded_memWidth (_rename_io_out_0_decoded_memWidth),
.io_out_0_decoded_isLoad (_rename_io_out_0_decoded_isLoad),
.io_out_0_decoded_isStore (_rename_io_out_0_decoded_isStore),
.io_out_0_decoded_isBranch (_rename_io_out_0_decoded_isBranch),
.io_out_0_decoded_isJal (_rename_io_out_0_decoded_isJal),
.io_out_0_decoded_isJalr (_rename_io_out_0_decoded_isJalr),
.io_out_0_decoded_isLui (_rename_io_out_0_decoded_isLui),
.io_out_0_decoded_isAuipc (_rename_io_out_0_decoded_isAuipc),
.io_out_0_decoded_isOpImm (_rename_io_out_0_decoded_isOpImm),
.io_out_0_decoded_isWord (_rename_io_out_0_decoded_isWord),
.io_out_0_decoded_isSystem (_rename_io_out_0_decoded_isSystem),
.io_out_0_decoded_writesRd (_rename_io_out_0_decoded_writesRd),
.io_out_0_decoded_illegal (_rename_io_out_0_decoded_illegal),
.io_out_0_prs1 (_rename_io_out_0_prs1),
.io_out_0_prs2 (_rename_io_out_0_prs2),
.io_out_0_src1Ready (_rename_io_out_0_src1Ready),
.io_out_0_src2Ready (_rename_io_out_0_src2Ready),
.io_out_0_prd (_rename_io_out_0_prd),
.io_out_0_robIdx (_rename_io_out_0_robIdx),
.io_out_1_decoded_pc (_rename_io_out_1_decoded_pc),
.io_out_1_decoded_inst (_rename_io_out_1_decoded_inst),
.io_out_1_decoded_rs1 (_rename_io_out_1_decoded_rs1),
.io_out_1_decoded_rs2 (_rename_io_out_1_decoded_rs2),
.io_out_1_decoded_funct3 (_rename_io_out_1_decoded_funct3),
.io_out_1_decoded_immI (_rename_io_out_1_decoded_immI),
.io_out_1_decoded_immS (_rename_io_out_1_decoded_immS),
.io_out_1_decoded_immB (_rename_io_out_1_decoded_immB),
.io_out_1_decoded_immU (_rename_io_out_1_decoded_immU),
.io_out_1_decoded_immJ (_rename_io_out_1_decoded_immJ),
.io_out_1_decoded_aluFn (_rename_io_out_1_decoded_aluFn),
.io_out_1_decoded_memWidth (_rename_io_out_1_decoded_memWidth),
.io_out_1_decoded_isLoad (_rename_io_out_1_decoded_isLoad),
.io_out_1_decoded_isStore (_rename_io_out_1_decoded_isStore),
.io_out_1_decoded_isBranch (_rename_io_out_1_decoded_isBranch),
.io_out_1_decoded_isJal (_rename_io_out_1_decoded_isJal),
.io_out_1_decoded_isJalr (_rename_io_out_1_decoded_isJalr),
.io_out_1_decoded_isLui (_rename_io_out_1_decoded_isLui),
.io_out_1_decoded_isAuipc (_rename_io_out_1_decoded_isAuipc),
.io_out_1_decoded_isOpImm (_rename_io_out_1_decoded_isOpImm),
.io_out_1_decoded_isWord (_rename_io_out_1_decoded_isWord),
.io_out_1_decoded_isSystem (_rename_io_out_1_decoded_isSystem),
.io_out_1_decoded_writesRd (_rename_io_out_1_decoded_writesRd),
.io_out_1_decoded_illegal (_rename_io_out_1_decoded_illegal),
.io_out_1_prs1 (_rename_io_out_1_prs1),
.io_out_1_prs2 (_rename_io_out_1_prs2),
.io_out_1_src1Ready (_rename_io_out_1_src1Ready),
.io_out_1_src2Ready (_rename_io_out_1_src2Ready),
.io_out_1_prd (_rename_io_out_1_prd),
.io_out_1_robIdx (_rename_io_out_1_robIdx),
.io_canAccept (_rename_io_canAccept),
.io_wbValid_0 (_wb_0_io_wen),
.io_wbValid_1 (_wb_1_io_wen),
.io_wbPhys_0 (_wb_0_io_waddr),
.io_wbPhys_1 (_wb_1_io_waddr),
.io_completeValid_0
(issueFire_0 & ~_issue_io_out_0_decoded_isLoad | loadRespValid),
.io_completeValid_1 (issueFire_1 & ~_issue_io_out_1_decoded_isLoad),
.io_completeIdx_0
(loadRespValid ? loadPendingRob : _issue_io_out_0_robIdx),
.io_completeIdx_1 (_issue_io_out_1_robIdx),
.io_completeException_0
(issueFire_0
& (_issue_io_out_0_decoded_illegal | isEcall | isEbreak | _lq_io_violation)
| _completeCause_0_T),
.io_completeException_1
(issueFire_1
& (_issue_io_out_1_decoded_illegal | isEcall_1 | isEbreak_1 | _lq_io_violation)),
.io_completeCause_0
({60'h0,
_completeCause_0_T
? 4'hD
: issueFire_0 & isEbreak
? 4'h3
: issueFire_0 & isEcall
? 4'hB
: {2'h0, issueFire_0 & _issue_io_out_0_decoded_illegal, 1'h0}}),
.io_completeCause_1
({60'h0,
issueFire_1 & isEbreak_1
? 4'h3
: issueFire_1 & isEcall_1
? 4'hB
: {2'h0, issueFire_1 & _issue_io_out_1_decoded_illegal, 1'h0}}),
.io_completeBadAddr_0 (_issue_io_out_0_decoded_pc),
.io_completeBadAddr_1 (_issue_io_out_1_decoded_pc),
.io_completeMispredict_0
(issueFire_0 & (_completeMispredict_0_T | isMret | _completeMispredict_0_T_2)),
.io_completeMispredict_1
(issueFire_1 & (_completeMispredict_1_T | isMret_1 | _completeMispredict_1_T_2)),
.io_completeRedirectPc_0
(isEcall | isEbreak
? _csr_io_mtvec
: isMret
? _csr_io_mepc
: _issue_io_out_0_decoded_isJal
? _issue_io_out_0_decoded_pc + _issue_io_out_0_decoded_immJ
: _issue_io_out_0_decoded_isJalr
? {_jalrTarget_T[63:1], 1'h0}
: _completeMispredict_0_T_2
? _issue_io_out_0_decoded_pc + _issue_io_out_0_decoded_immB
: _branchRedirect_T_1),
.io_completeRedirectPc_1
(isEcall_1 | isEbreak_1
? _csr_io_mtvec
: isMret_1
? _csr_io_mepc
: _issue_io_out_1_decoded_isJal
? _issue_io_out_1_decoded_pc + _issue_io_out_1_decoded_immJ
: _issue_io_out_1_decoded_isJalr
? {_jalrTarget_T_3[63:1], 1'h0}
: _completeMispredict_1_T_2
? _issue_io_out_1_decoded_pc + _issue_io_out_1_decoded_immB
: _branchRedirect_T_6),
.io_completeCsrValid_0
(issueFire_0 & _issue_io_out_0_decoded_isSystem & (|_issue_io_out_0_decoded_funct3)
& ~(_issue_io_out_0_decoded_funct3[1] & _issue_io_out_0_decoded_rs1 == 5'h0)),
.io_completeCsrValid_1
(issueFire_1 & _issue_io_out_1_decoded_isSystem & (|_issue_io_out_1_decoded_funct3)
& ~(_issue_io_out_1_decoded_funct3[1] & _issue_io_out_1_decoded_rs1 == 5'h0)),
.io_completeCsrAddr_0 (_issue_io_out_0_decoded_inst[31:20]),
.io_completeCsrAddr_1 (_issue_io_out_1_decoded_inst[31:20]),
.io_completeCsrCmd_0 (_issue_io_out_0_decoded_funct3),
.io_completeCsrCmd_1 (_issue_io_out_1_decoded_funct3),
.io_completeCsrRs1_0 (_prf_io_rdata_0),
.io_completeCsrRs1_1 (_prf_io_rdata_2),
.io_completeCsrZimm_0 (_issue_io_out_0_decoded_rs1),
.io_completeCsrZimm_1 (_issue_io_out_1_decoded_rs1),
.io_commitReady_0 (_commit_io_commitReady_0),
.io_commitReady_1 (_commit_io_commitReady_1),
.io_commitValid_0 (_rename_io_commitValid_0),
.io_commitValid_1 (_rename_io_commitValid_1),
.io_commitEntry_0_robIdx (_rename_io_commitEntry_0_robIdx),
.io_commitEntry_0_archDest (_rename_io_commitEntry_0_archDest),
.io_commitEntry_0_writesDest (_rename_io_commitEntry_0_writesDest),
.io_commitEntry_0_opClass (_rename_io_commitEntry_0_opClass),
.io_commitEntry_0_dest (_rename_io_commitEntry_0_dest),
.io_commitEntry_0_oldDest (_rename_io_commitEntry_0_oldDest),
.io_commitEntry_0_exception (_rename_io_commitEntry_0_exception),
.io_commitEntry_0_exceptionCause (_rename_io_commitEntry_0_exceptionCause),
.io_commitEntry_0_badAddr (_rename_io_commitEntry_0_badAddr),
.io_commitEntry_0_branchMispredict (_rename_io_commitEntry_0_branchMispredict),
.io_commitEntry_0_redirectPc (_rename_io_commitEntry_0_redirectPc),
.io_commitEntry_0_csrValid (_rename_io_commitEntry_0_csrValid),
.io_commitEntry_0_csrAddr (_rename_io_commitEntry_0_csrAddr),
.io_commitEntry_0_csrCmd (_rename_io_commitEntry_0_csrCmd),
.io_commitEntry_0_csrRs1 (_rename_io_commitEntry_0_csrRs1),
.io_commitEntry_0_csrZimm (_rename_io_commitEntry_0_csrZimm),
.io_commitEntry_1_robIdx (_rename_io_commitEntry_1_robIdx),
.io_commitEntry_1_archDest (_rename_io_commitEntry_1_archDest),
.io_commitEntry_1_writesDest (_rename_io_commitEntry_1_writesDest),
.io_commitEntry_1_opClass (_rename_io_commitEntry_1_opClass),
.io_commitEntry_1_dest (_rename_io_commitEntry_1_dest),
.io_commitEntry_1_oldDest (_rename_io_commitEntry_1_oldDest),
.io_commitEntry_1_exception (_rename_io_commitEntry_1_exception),
.io_commitEntry_1_exceptionCause (_rename_io_commitEntry_1_exceptionCause),
.io_commitEntry_1_badAddr (_rename_io_commitEntry_1_badAddr),
.io_commitEntry_1_branchMispredict (_rename_io_commitEntry_1_branchMispredict),
.io_commitEntry_1_redirectPc (_rename_io_commitEntry_1_redirectPc),
.io_commitEntry_1_csrValid (_rename_io_commitEntry_1_csrValid),
.io_commitEntry_1_csrAddr (_rename_io_commitEntry_1_csrAddr),
.io_commitEntry_1_csrCmd (_rename_io_commitEntry_1_csrCmd),
.io_commitEntry_1_csrRs1 (_rename_io_commitEntry_1_csrRs1),
.io_commitEntry_1_csrZimm (_rename_io_commitEntry_1_csrZimm),
.io_commitMapValid_0 (_commit_io_commitMapValid_0),
.io_commitMapValid_1 (_commit_io_commitMapValid_1),
.io_commitArch_0 (_commit_io_commitArch_0),
.io_commitArch_1 (_commit_io_commitArch_1),
.io_commitPhys_0 (_commit_io_commitPhys_0),
.io_commitPhys_1 (_commit_io_commitPhys_1),
.io_commitFreeOld_0 (_commit_io_freeOldPhys_0),
.io_commitFreeOld_1 (_commit_io_freeOldPhys_1),
.io_commitOldPhys_0 (_commit_io_oldPhys_0),
.io_commitOldPhys_1 (_commit_io_oldPhys_1),
.io_flush (_commit_io_flush)
);
IssueStage issue (
.clock (clock),
.reset (reset),
.io_inValid_0 (_rename_io_outValid_0),
.io_inValid_1 (_rename_io_outValid_1),
.io_in_0_decoded_pc (_rename_io_out_0_decoded_pc),
.io_in_0_decoded_inst (_rename_io_out_0_decoded_inst),
.io_in_0_decoded_rs1 (_rename_io_out_0_decoded_rs1),
.io_in_0_decoded_rs2 (_rename_io_out_0_decoded_rs2),
.io_in_0_decoded_funct3 (_rename_io_out_0_decoded_funct3),
.io_in_0_decoded_immI (_rename_io_out_0_decoded_immI),
.io_in_0_decoded_immS (_rename_io_out_0_decoded_immS),
.io_in_0_decoded_immB (_rename_io_out_0_decoded_immB),
.io_in_0_decoded_immU (_rename_io_out_0_decoded_immU),
.io_in_0_decoded_immJ (_rename_io_out_0_decoded_immJ),
.io_in_0_decoded_aluFn (_rename_io_out_0_decoded_aluFn),
.io_in_0_decoded_memWidth (_rename_io_out_0_decoded_memWidth),
.io_in_0_decoded_isLoad (_rename_io_out_0_decoded_isLoad),
.io_in_0_decoded_isStore (_rename_io_out_0_decoded_isStore),
.io_in_0_decoded_isBranch (_rename_io_out_0_decoded_isBranch),
.io_in_0_decoded_isJal (_rename_io_out_0_decoded_isJal),
.io_in_0_decoded_isJalr (_rename_io_out_0_decoded_isJalr),
.io_in_0_decoded_isLui (_rename_io_out_0_decoded_isLui),
.io_in_0_decoded_isAuipc (_rename_io_out_0_decoded_isAuipc),
.io_in_0_decoded_isOpImm (_rename_io_out_0_decoded_isOpImm),
.io_in_0_decoded_isWord (_rename_io_out_0_decoded_isWord),
.io_in_0_decoded_isSystem (_rename_io_out_0_decoded_isSystem),
.io_in_0_decoded_writesRd (_rename_io_out_0_decoded_writesRd),
.io_in_0_decoded_illegal (_rename_io_out_0_decoded_illegal),
.io_in_0_prs1 (_rename_io_out_0_prs1),
.io_in_0_prs2 (_rename_io_out_0_prs2),
.io_in_0_src1Ready (_rename_io_out_0_src1Ready),
.io_in_0_src2Ready (_rename_io_out_0_src2Ready),
.io_in_0_prd (_rename_io_out_0_prd),
.io_in_0_robIdx (_rename_io_out_0_robIdx),
.io_in_1_decoded_pc (_rename_io_out_1_decoded_pc),
.io_in_1_decoded_inst (_rename_io_out_1_decoded_inst),
.io_in_1_decoded_rs1 (_rename_io_out_1_decoded_rs1),
.io_in_1_decoded_rs2 (_rename_io_out_1_decoded_rs2),
.io_in_1_decoded_funct3 (_rename_io_out_1_decoded_funct3),
.io_in_1_decoded_immI (_rename_io_out_1_decoded_immI),
.io_in_1_decoded_immS (_rename_io_out_1_decoded_immS),
.io_in_1_decoded_immB (_rename_io_out_1_decoded_immB),
.io_in_1_decoded_immU (_rename_io_out_1_decoded_immU),
.io_in_1_decoded_immJ (_rename_io_out_1_decoded_immJ),
.io_in_1_decoded_aluFn (_rename_io_out_1_decoded_aluFn),
.io_in_1_decoded_memWidth (_rename_io_out_1_decoded_memWidth),
.io_in_1_decoded_isLoad (_rename_io_out_1_decoded_isLoad),
.io_in_1_decoded_isStore (_rename_io_out_1_decoded_isStore),
.io_in_1_decoded_isBranch (_rename_io_out_1_decoded_isBranch),
.io_in_1_decoded_isJal (_rename_io_out_1_decoded_isJal),
.io_in_1_decoded_isJalr (_rename_io_out_1_decoded_isJalr),
.io_in_1_decoded_isLui (_rename_io_out_1_decoded_isLui),
.io_in_1_decoded_isAuipc (_rename_io_out_1_decoded_isAuipc),
.io_in_1_decoded_isOpImm (_rename_io_out_1_decoded_isOpImm),
.io_in_1_decoded_isWord (_rename_io_out_1_decoded_isWord),
.io_in_1_decoded_isSystem (_rename_io_out_1_decoded_isSystem),
.io_in_1_decoded_writesRd (_rename_io_out_1_decoded_writesRd),
.io_in_1_decoded_illegal (_rename_io_out_1_decoded_illegal),
.io_in_1_prs1 (_rename_io_out_1_prs1),
.io_in_1_prs2 (_rename_io_out_1_prs2),
.io_in_1_src1Ready (_rename_io_out_1_src1Ready),
.io_in_1_src2Ready (_rename_io_out_1_src2Ready),
.io_in_1_prd (_rename_io_out_1_prd),
.io_in_1_robIdx (_rename_io_out_1_robIdx),
.io_inReady_0 (_issue_io_inReady_0),
.io_inReady_1 (_issue_io_inReady_1),
.io_wakeup_0_valid (wakeupReg_0_valid),
.io_wakeup_0_phys (wakeupReg_0_phys),
.io_wakeup_1_valid (wakeupReg_1_valid),
.io_wakeup_1_phys (wakeupReg_1_phys),
.io_outValid_0 (_issue_io_outValid_0),
.io_outValid_1 (_issue_io_outValid_1),
.io_out_0_decoded_pc (_issue_io_out_0_decoded_pc),
.io_out_0_decoded_inst (_issue_io_out_0_decoded_inst),
.io_out_0_decoded_rs1 (_issue_io_out_0_decoded_rs1),
.io_out_0_decoded_funct3 (_issue_io_out_0_decoded_funct3),
.io_out_0_decoded_immI (_issue_io_out_0_decoded_immI),
.io_out_0_decoded_immS (_issue_io_out_0_decoded_immS),
.io_out_0_decoded_immB (_issue_io_out_0_decoded_immB),
.io_out_0_decoded_immU (_issue_io_out_0_decoded_immU),
.io_out_0_decoded_immJ (_issue_io_out_0_decoded_immJ),
.io_out_0_decoded_aluFn (_issue_io_out_0_decoded_aluFn),
.io_out_0_decoded_memWidth (_issue_io_out_0_decoded_memWidth),
.io_out_0_decoded_isLoad (_issue_io_out_0_decoded_isLoad),
.io_out_0_decoded_isStore (_issue_io_out_0_decoded_isStore),
.io_out_0_decoded_isBranch (_issue_io_out_0_decoded_isBranch),
.io_out_0_decoded_isJal (_issue_io_out_0_decoded_isJal),
.io_out_0_decoded_isJalr (_issue_io_out_0_decoded_isJalr),
.io_out_0_decoded_isLui (_issue_io_out_0_decoded_isLui),
.io_out_0_decoded_isAuipc (_issue_io_out_0_decoded_isAuipc),
.io_out_0_decoded_isOpImm (_issue_io_out_0_decoded_isOpImm),
.io_out_0_decoded_isWord (_issue_io_out_0_decoded_isWord),
.io_out_0_decoded_isSystem (_issue_io_out_0_decoded_isSystem),
.io_out_0_decoded_writesRd (_issue_io_out_0_decoded_writesRd),
.io_out_0_decoded_illegal (_issue_io_out_0_decoded_illegal),
.io_out_0_prs1 (_issue_io_out_0_prs1),
.io_out_0_prs2 (_issue_io_out_0_prs2),
.io_out_0_prd (_issue_io_out_0_prd),
.io_out_0_robIdx (_issue_io_out_0_robIdx),
.io_out_1_decoded_pc (_issue_io_out_1_decoded_pc),
.io_out_1_decoded_inst (_issue_io_out_1_decoded_inst),
.io_out_1_decoded_rs1 (_issue_io_out_1_decoded_rs1),
.io_out_1_decoded_funct3 (_issue_io_out_1_decoded_funct3),
.io_out_1_decoded_immI (_issue_io_out_1_decoded_immI),
.io_out_1_decoded_immS (_issue_io_out_1_decoded_immS),
.io_out_1_decoded_immB (_issue_io_out_1_decoded_immB),
.io_out_1_decoded_immU (_issue_io_out_1_decoded_immU),
.io_out_1_decoded_immJ (_issue_io_out_1_decoded_immJ),
.io_out_1_decoded_aluFn (_issue_io_out_1_decoded_aluFn),
.io_out_1_decoded_memWidth (_issue_io_out_1_decoded_memWidth),
.io_out_1_decoded_isLoad (_issue_io_out_1_decoded_isLoad),
.io_out_1_decoded_isStore (_issue_io_out_1_decoded_isStore),
.io_out_1_decoded_isBranch (_issue_io_out_1_decoded_isBranch),
.io_out_1_decoded_isJal (_issue_io_out_1_decoded_isJal),
.io_out_1_decoded_isJalr (_issue_io_out_1_decoded_isJalr),
.io_out_1_decoded_isLui (_issue_io_out_1_decoded_isLui),
.io_out_1_decoded_isAuipc (_issue_io_out_1_decoded_isAuipc),
.io_out_1_decoded_isOpImm (_issue_io_out_1_decoded_isOpImm),
.io_out_1_decoded_isWord (_issue_io_out_1_decoded_isWord),
.io_out_1_decoded_isSystem (_issue_io_out_1_decoded_isSystem),
.io_out_1_decoded_writesRd (_issue_io_out_1_decoded_writesRd),
.io_out_1_decoded_illegal (_issue_io_out_1_decoded_illegal),
.io_out_1_prs1 (_issue_io_out_1_prs1),
.io_out_1_prs2 (_issue_io_out_1_prs2),
.io_out_1_prd (_issue_io_out_1_prd),
.io_out_1_robIdx (_issue_io_out_1_robIdx),
.io_outReady_0 (issue_io_outReady_0),
.io_outReady_1 (issue_io_outReady_1),
.io_flush (_commit_io_flush)
);
PhysicalRegFile prf (
.clock (clock),
.reset (reset),
.io_raddr_0 (_issue_io_out_0_prs1),
.io_raddr_1 (_issue_io_out_0_prs2),
.io_raddr_2 (_issue_io_out_1_prs1),
.io_raddr_3 (_issue_io_out_1_prs2),
.io_rdata_0 (_prf_io_rdata_0),
.io_rdata_1 (_prf_io_rdata_1),
.io_rdata_2 (_prf_io_rdata_2),
.io_rdata_3 (_prf_io_rdata_3),
.io_wen_0 (_wb_0_io_wen),
.io_wen_1 (_wb_1_io_wen),
.io_waddr_0 (_wb_0_io_waddr),
.io_waddr_1 (_wb_1_io_waddr),
.io_wdata_0 (_wb_0_io_wdata),
.io_wdata_1 (_wb_1_io_wdata)
);
ExecStage exec_0 (
.io_inValid (issueFire_0),
.io_in_funct3 (_issue_io_out_0_decoded_funct3),
.io_in_aluFn (_issue_io_out_0_decoded_aluFn),
.io_in_isWord (_issue_io_out_0_decoded_isWord),
.io_src1 (_prf_io_rdata_0),
.io_src2
(_issue_io_out_0_decoded_isOpImm | _issue_io_out_0_decoded_isLoad
| _issue_io_out_0_decoded_isJalr
? _issue_io_out_0_decoded_immI
: _prf_io_rdata_1),
.io_outValid (_exec_0_io_outValid),
.io_result (_exec_0_io_result),
.io_branchTaken (_exec_0_io_branchTaken)
);
ExecStage exec_1 (
.io_inValid (issueFire_1),
.io_in_funct3 (_issue_io_out_1_decoded_funct3),
.io_in_aluFn (_issue_io_out_1_decoded_aluFn),
.io_in_isWord (_issue_io_out_1_decoded_isWord),
.io_src1 (_prf_io_rdata_2),
.io_src2
(_issue_io_out_1_decoded_isOpImm | _issue_io_out_1_decoded_isLoad
| _issue_io_out_1_decoded_isJalr
? _issue_io_out_1_decoded_immI
: _prf_io_rdata_3),
.io_outValid (_exec_1_io_outValid),
.io_result (_exec_1_io_result),
.io_branchTaken (_exec_1_io_branchTaken)
);
WriteBackStage wb_0 (
.io_valid
(_exec_0_io_outValid & _issue_io_out_0_decoded_writesRd
& ~_issue_io_out_0_decoded_isLoad | loadRespValid),
.io_physDest (loadRespValid ? loadPendingPhys : _issue_io_out_0_prd),
.io_data
(loadRespValid
? _lsu_io_respData
: _issue_io_out_0_decoded_isLui
? _issue_io_out_0_decoded_immU
: _issue_io_out_0_decoded_isAuipc
? _issue_io_out_0_decoded_pc + _issue_io_out_0_decoded_immU
: _completeMispredict_0_T
? _branchRedirect_T_1
: _issue_io_out_0_decoded_isSystem
& (|_issue_io_out_0_decoded_funct3)
? _csr_io_rdata
: _exec_0_io_result),
.io_wen (_wb_0_io_wen),
.io_waddr (_wb_0_io_waddr),
.io_wdata (_wb_0_io_wdata)
);
WriteBackStage wb_1 (
.io_valid
(_exec_1_io_outValid & _issue_io_out_1_decoded_writesRd
& ~_issue_io_out_1_decoded_isLoad),
.io_physDest (_issue_io_out_1_prd),
.io_data
(_issue_io_out_1_decoded_isLui
? _issue_io_out_1_decoded_immU
: _issue_io_out_1_decoded_isAuipc
? _issue_io_out_1_decoded_pc + _issue_io_out_1_decoded_immU
: _completeMispredict_1_T
? _branchRedirect_T_6
: _issue_io_out_1_decoded_isSystem & (|_issue_io_out_1_decoded_funct3)
? _csr_io_rdata
: _exec_1_io_result),
.io_wen (_wb_1_io_wen),
.io_waddr (_wb_1_io_waddr),
.io_wdata (_wb_1_io_wdata)
);
CommitStage commit (
.io_robValid_0 (_rename_io_commitValid_0),
.io_robValid_1 (_rename_io_commitValid_1),
.io_robEntry_0_archDest (_rename_io_commitEntry_0_archDest),
.io_robEntry_0_writesDest (_rename_io_commitEntry_0_writesDest),
.io_robEntry_0_opClass (_rename_io_commitEntry_0_opClass),
.io_robEntry_0_dest (_rename_io_commitEntry_0_dest),
.io_robEntry_0_oldDest (_rename_io_commitEntry_0_oldDest),
.io_robEntry_0_exception (_rename_io_commitEntry_0_exception),
.io_robEntry_0_exceptionCause (_rename_io_commitEntry_0_exceptionCause),
.io_robEntry_0_badAddr (_rename_io_commitEntry_0_badAddr),
.io_robEntry_0_branchMispredict (_rename_io_commitEntry_0_branchMispredict),
.io_robEntry_0_redirectPc (_rename_io_commitEntry_0_redirectPc),
.io_robEntry_0_csrValid (_rename_io_commitEntry_0_csrValid),
.io_robEntry_1_archDest (_rename_io_commitEntry_1_archDest),
.io_robEntry_1_writesDest (_rename_io_commitEntry_1_writesDest),
.io_robEntry_1_dest (_rename_io_commitEntry_1_dest),
.io_robEntry_1_oldDest (_rename_io_commitEntry_1_oldDest),
.io_robEntry_1_exception (_rename_io_commitEntry_1_exception),
.io_robEntry_1_exceptionCause (_rename_io_commitEntry_1_exceptionCause),
.io_robEntry_1_badAddr (_rename_io_commitEntry_1_badAddr),
.io_robEntry_1_branchMispredict (_rename_io_commitEntry_1_branchMispredict),
.io_robEntry_1_redirectPc (_rename_io_commitEntry_1_redirectPc),
.io_robEntry_1_csrValid (_rename_io_commitEntry_1_csrValid),
.io_commitReady_0 (_commit_io_commitReady_0),
.io_commitReady_1 (_commit_io_commitReady_1),
.io_freeOldPhys_0 (_commit_io_freeOldPhys_0),
.io_freeOldPhys_1 (_commit_io_freeOldPhys_1),
.io_oldPhys_0 (_commit_io_oldPhys_0),
.io_oldPhys_1 (_commit_io_oldPhys_1),
.io_commitMapValid_0 (_commit_io_commitMapValid_0),
.io_commitMapValid_1 (_commit_io_commitMapValid_1),
.io_commitArch_0 (_commit_io_commitArch_0),
.io_commitArch_1 (_commit_io_commitArch_1),
.io_commitPhys_0 (_commit_io_commitPhys_0),
.io_commitPhys_1 (_commit_io_commitPhys_1),
.io_flush (_commit_io_flush),
.io_redirectPc (_commit_io_redirectPc),
.io_exception (_commit_io_exception),
.io_exceptionCause (_commit_io_exceptionCause),
.io_badAddr (_commit_io_badAddr)
);
LoadQueue lq (
.clock (clock),
.reset (reset),
.io_enqValid (loadEnq),
.io_enqRobIdx (sq_io_enqRobIdx),
.io_enqIdx (_lq_io_enqIdx),
.io_addrValid (loadEnq),
.io_addrIdx (_lq_io_enqIdx),
.io_addr (_memAddr_T_1),
.io_size (sq_io_size),
.io_complete (loadRespValid),
.io_completeIdx (loadPendingLq),
.io_storeAddrValid (storeEnq),
.io_storeRobIdx (sq_io_enqRobIdx),
.io_storeAddr (_memAddr_T_1),
.io_storeSize (sq_io_size),
.io_violation (_lq_io_violation),
.io_flush (_commit_io_flush)
);
StoreQueue sq (
.clock (clock),
.reset (reset),
.io_enqValid (storeEnq),
.io_enqRobIdx (sq_io_enqRobIdx),
.io_enqIdx (_sq_io_enqIdx),
.io_writeAddr (storeEnq),
.io_writeData (storeEnq),
.io_writeIdx (_sq_io_enqIdx),
.io_addr (_memAddr_T_1),
.io_data (memIssue_0 ? _prf_io_rdata_1 : _prf_io_rdata_3),
.io_size (sq_io_size),
.io_loadAddr (_memAddr_T_1),
.io_loadRobIdx (sq_io_enqRobIdx),
.io_forwardValid (_sq_io_forwardValid),
.io_commitValid
(commitStore0 | _commitCsr1_T & _rename_io_commitEntry_1_opClass == 4'h4),
.io_commitRobIdx
(commitStore0 ? _rename_io_commitEntry_0_robIdx : _rename_io_commitEntry_1_robIdx),
.io_drainValid (_sq_io_drainValid),
.io_drain_addr (_sq_io_drain_addr),
.io_drain_data (_sq_io_drain_data),
.io_drain_size (_sq_io_drain_size),
.io_drainReady (~lsuLoadReq & _lsu_io_reqReady),
.io_flush (_commit_io_flush)
);
LSU lsu (
.clock (clock),
.reset (reset),
.io_reqValid (lsuLoadReq | _sq_io_drainValid),
.io_req_addr
(lsuLoadReq ? _memAddr_T_1 : _sq_io_drainValid ? _sq_io_drain_addr : 64'h0),
.io_req_data (lsuLoadReq | ~_sq_io_drainValid ? 64'h0 : _sq_io_drain_data),
.io_req_isStore (~lsuLoadReq & _sq_io_drainValid),
.io_req_size
(lsuLoadReq ? sq_io_size : _sq_io_drainValid ? _sq_io_drain_size : 3'h0),
.io_reqReady (_lsu_io_reqReady),
.io_satp (_csr_io_satp),
.io_dmemReqValid (io_dmemReqValid),
.io_dmemReq_addr (io_dmemReq_addr),
.io_dmemReq_data (io_dmemReq_data),
.io_dmemReq_isStore (io_dmemReq_isStore),
.io_dmemReq_size (io_dmemReq_size),
.io_dmemRespValid (io_dmemRespValid),
.io_dmemRespData (io_dmemRespData),
.io_respValid (_lsu_io_respValid),
.io_respData (_lsu_io_respData),
.io_pageFault (_lsu_io_pageFault)
);
CSRFile csr (
.clock (clock),
.reset (reset),
.io_cmd_valid (commitCsr0 | _commitCsr1_T & _rename_io_commitEntry_1_csrValid),
.io_cmd_addr
(commitCsr0 ? _rename_io_commitEntry_0_csrAddr : _rename_io_commitEntry_1_csrAddr),
.io_cmd_cmd
(commitCsr0 ? _rename_io_commitEntry_0_csrCmd : _rename_io_commitEntry_1_csrCmd),
.io_cmd_rs1
(commitCsr0 ? _rename_io_commitEntry_0_csrRs1 : _rename_io_commitEntry_1_csrRs1),
.io_cmd_zimm
(commitCsr0 ? _rename_io_commitEntry_0_csrZimm : _rename_io_commitEntry_1_csrZimm),
.io_readAddr
(csrReadReq_0 & issue_io_outReady_0
? _issue_io_out_0_decoded_inst[31:20]
: _issue_io_out_1_decoded_inst[31:20]),
.io_rdata (_csr_io_rdata),
.io_trap (_commit_io_flush & _commit_io_exception),
.io_trapPc (_commit_io_badAddr),
.io_trapCause (_commit_io_exceptionCause),
.io_satp (_csr_io_satp),
.io_mtvec (_csr_io_mtvec),
.io_mepc (_csr_io_mepc)
);
assign io_decodeReady =
_rename_io_canAccept & (&{_issue_io_inReady_1, _issue_io_inReady_0});
assign io_flush = _commit_io_flush;
assign io_redirectPc = _commit_io_exception ? _csr_io_mtvec : _commit_io_redirectPc;
endmodule

102
generated-ooo/PageTableWalker.sv Normal file
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// Generated by CIRCT firtool-1.139.0
module PageTableWalker(
input clock,
reset,
io_reqValid,
input [26:0] io_reqVpn,
input io_isStore,
input [63:0] io_satp,
output io_memReq_valid,
output [63:0] io_memReq_addr,
input io_memResp_valid,
input [63:0] io_memResp_data,
output io_respValid,
io_refill_valid,
output [26:0] io_refill_vpn,
output [43:0] io_refill_ppn,
output [7:0] io_refill_flags,
output io_pageFault
);
reg [2:0] state;
reg [26:0] vpnReg;
reg isStoreReg;
reg walkFault;
reg [43:0] nextPpn;
wire _io_memReq_addr_T = state == 3'h1;
wire _io_memReq_addr_T_1 = state == 3'h2;
reg [43:0] curPpn;
wire _io_memReq_valid_T_3 = state == 3'h3;
wire io_respValid_0 = state == 3'h4;
always @(posedge clock) begin
automatic logic pteIsLeaf;
automatic logic invalidPte;
automatic logic _GEN;
automatic logic _GEN_0;
automatic logic _GEN_1;
automatic logic _GEN_2;
pteIsLeaf = io_memResp_data[1] | io_memResp_data[3];
invalidPte = ~(io_memResp_data[0]) | ~(io_memResp_data[1]) & io_memResp_data[2];
_GEN = state == 3'h0;
_GEN_0 = _io_memReq_addr_T | _io_memReq_addr_T_1;
_GEN_1 = (_GEN_0 | _io_memReq_valid_T_3) & io_memResp_valid;
_GEN_2 = invalidPte | pteIsLeaf;
if (reset) begin
state <= 3'h0;
walkFault <= 1'h0;
end
else begin
if (_GEN) begin
if (io_reqValid)
state <= 3'h1;
end
else if (_GEN_1)
state <=
_GEN_2 ? 3'h4 : _io_memReq_addr_T ? 3'h2 : _io_memReq_addr_T_1 ? 3'h3 : 3'h4;
else if (io_respValid_0)
state <= 3'h0;
walkFault <=
~_GEN
& (_GEN_1
? invalidPte
| (pteIsLeaf
? (isStoreReg
? ~(io_memResp_data[2]) | ~(io_memResp_data[7])
: ~(io_memResp_data[1])) | ~(io_memResp_data[6]) | walkFault
: ~_GEN_0 | walkFault)
: walkFault);
end
if (_GEN & io_reqValid) begin
vpnReg <= io_reqVpn;
isStoreReg <= io_isStore;
end
if (_GEN | ~_GEN_1 | invalidPte | ~pteIsLeaf) begin
end
else begin
automatic logic [1:0] level =
_io_memReq_addr_T ? 2'h2 : {1'h0, _io_memReq_addr_T_1};
nextPpn <=
{io_memResp_data[53:28],
level[1] ? vpnReg[17:9] : io_memResp_data[27:19],
level == 2'h0 ? io_memResp_data[18:10] : vpnReg[8:0]};
end
if (_GEN | ~_GEN_1 | _GEN_2) begin
end
else
curPpn <= io_memResp_data[53:10];
end // always @(posedge)
assign io_memReq_valid = _io_memReq_addr_T | _io_memReq_addr_T_1 | _io_memReq_valid_T_3;
assign io_memReq_addr =
{8'h0,
_io_memReq_addr_T
? {io_satp[43:0], vpnReg[26:18]}
: {curPpn, _io_memReq_addr_T_1 ? vpnReg[17:9] : vpnReg[8:0]},
3'h0};
assign io_respValid = io_respValid_0;
assign io_refill_valid = io_respValid_0 & ~walkFault;
assign io_refill_vpn = vpnReg;
assign io_refill_ppn = nextPpn;
assign io_refill_flags = io_memResp_data[7:0];
assign io_pageFault = walkFault;
endmodule

484
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// Generated by CIRCT firtool-1.139.0
module PhysicalRegFile(
input clock,
reset,
input [5:0] io_raddr_0,
io_raddr_1,
io_raddr_2,
io_raddr_3,
output [63:0] io_rdata_0,
io_rdata_1,
io_rdata_2,
io_rdata_3,
input io_wen_0,
io_wen_1,
input [5:0] io_waddr_0,
io_waddr_1,
input [63:0] io_wdata_0,
io_wdata_1
);
reg [63:0] regs_0;
reg [63:0] regs_1;
reg [63:0] regs_2;
reg [63:0] regs_3;
reg [63:0] regs_4;
reg [63:0] regs_5;
reg [63:0] regs_6;
reg [63:0] regs_7;
reg [63:0] regs_8;
reg [63:0] regs_9;
reg [63:0] regs_10;
reg [63:0] regs_11;
reg [63:0] regs_12;
reg [63:0] regs_13;
reg [63:0] regs_14;
reg [63:0] regs_15;
reg [63:0] regs_16;
reg [63:0] regs_17;
reg [63:0] regs_18;
reg [63:0] regs_19;
reg [63:0] regs_20;
reg [63:0] regs_21;
reg [63:0] regs_22;
reg [63:0] regs_23;
reg [63:0] regs_24;
reg [63:0] regs_25;
reg [63:0] regs_26;
reg [63:0] regs_27;
reg [63:0] regs_28;
reg [63:0] regs_29;
reg [63:0] regs_30;
reg [63:0] regs_31;
reg [63:0] regs_32;
reg [63:0] regs_33;
reg [63:0] regs_34;
reg [63:0] regs_35;
reg [63:0] regs_36;
reg [63:0] regs_37;
reg [63:0] regs_38;
reg [63:0] regs_39;
reg [63:0] regs_40;
reg [63:0] regs_41;
reg [63:0] regs_42;
reg [63:0] regs_43;
reg [63:0] regs_44;
reg [63:0] regs_45;
reg [63:0] regs_46;
reg [63:0] regs_47;
reg [63:0] regs_48;
reg [63:0] regs_49;
reg [63:0] regs_50;
reg [63:0] regs_51;
reg [63:0] regs_52;
reg [63:0] regs_53;
reg [63:0] regs_54;
reg [63:0] regs_55;
reg [63:0] regs_56;
reg [63:0] regs_57;
reg [63:0] regs_58;
reg [63:0] regs_59;
reg [63:0] regs_60;
reg [63:0] regs_61;
reg [63:0] regs_62;
reg [63:0] regs_63;
wire [63:0][63:0] _GEN =
{{regs_63},
{regs_62},
{regs_61},
{regs_60},
{regs_59},
{regs_58},
{regs_57},
{regs_56},
{regs_55},
{regs_54},
{regs_53},
{regs_52},
{regs_51},
{regs_50},
{regs_49},
{regs_48},
{regs_47},
{regs_46},
{regs_45},
{regs_44},
{regs_43},
{regs_42},
{regs_41},
{regs_40},
{regs_39},
{regs_38},
{regs_37},
{regs_36},
{regs_35},
{regs_34},
{regs_33},
{regs_32},
{regs_31},
{regs_30},
{regs_29},
{regs_28},
{regs_27},
{regs_26},
{regs_25},
{regs_24},
{regs_23},
{regs_22},
{regs_21},
{regs_20},
{regs_19},
{regs_18},
{regs_17},
{regs_16},
{regs_15},
{regs_14},
{regs_13},
{regs_12},
{regs_11},
{regs_10},
{regs_9},
{regs_8},
{regs_7},
{regs_6},
{regs_5},
{regs_4},
{regs_3},
{regs_2},
{regs_1},
{regs_0}};
always @(posedge clock) begin
if (reset) begin
regs_0 <= 64'h0;
regs_1 <= 64'h0;
regs_2 <= 64'h0;
regs_3 <= 64'h0;
regs_4 <= 64'h0;
regs_5 <= 64'h0;
regs_6 <= 64'h0;
regs_7 <= 64'h0;
regs_8 <= 64'h0;
regs_9 <= 64'h0;
regs_10 <= 64'h0;
regs_11 <= 64'h0;
regs_12 <= 64'h0;
regs_13 <= 64'h0;
regs_14 <= 64'h0;
regs_15 <= 64'h0;
regs_16 <= 64'h0;
regs_17 <= 64'h0;
regs_18 <= 64'h0;
regs_19 <= 64'h0;
regs_20 <= 64'h0;
regs_21 <= 64'h0;
regs_22 <= 64'h0;
regs_23 <= 64'h0;
regs_24 <= 64'h0;
regs_25 <= 64'h0;
regs_26 <= 64'h0;
regs_27 <= 64'h0;
regs_28 <= 64'h0;
regs_29 <= 64'h0;
regs_30 <= 64'h0;
regs_31 <= 64'h0;
regs_32 <= 64'h0;
regs_33 <= 64'h0;
regs_34 <= 64'h0;
regs_35 <= 64'h0;
regs_36 <= 64'h0;
regs_37 <= 64'h0;
regs_38 <= 64'h0;
regs_39 <= 64'h0;
regs_40 <= 64'h0;
regs_41 <= 64'h0;
regs_42 <= 64'h0;
regs_43 <= 64'h0;
regs_44 <= 64'h0;
regs_45 <= 64'h0;
regs_46 <= 64'h0;
regs_47 <= 64'h0;
regs_48 <= 64'h0;
regs_49 <= 64'h0;
regs_50 <= 64'h0;
regs_51 <= 64'h0;
regs_52 <= 64'h0;
regs_53 <= 64'h0;
regs_54 <= 64'h0;
regs_55 <= 64'h0;
regs_56 <= 64'h0;
regs_57 <= 64'h0;
regs_58 <= 64'h0;
regs_59 <= 64'h0;
regs_60 <= 64'h0;
regs_61 <= 64'h0;
regs_62 <= 64'h0;
regs_63 <= 64'h0;
end
else begin
automatic logic _GEN_0;
automatic logic _GEN_1 = io_wen_1 & (|io_waddr_1);
_GEN_0 = io_wen_0 & (|io_waddr_0);
if (_GEN_1 & ~(|io_waddr_1))
regs_0 <= io_wdata_1;
else if (_GEN_0 & ~(|io_waddr_0))
regs_0 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h1)
regs_1 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h1)
regs_1 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h2)
regs_2 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h2)
regs_2 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h3)
regs_3 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h3)
regs_3 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h4)
regs_4 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h4)
regs_4 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h5)
regs_5 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h5)
regs_5 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h6)
regs_6 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h6)
regs_6 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h7)
regs_7 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h7)
regs_7 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h8)
regs_8 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h8)
regs_8 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h9)
regs_9 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h9)
regs_9 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'hA)
regs_10 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'hA)
regs_10 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'hB)
regs_11 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'hB)
regs_11 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'hC)
regs_12 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'hC)
regs_12 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'hD)
regs_13 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'hD)
regs_13 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'hE)
regs_14 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'hE)
regs_14 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'hF)
regs_15 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'hF)
regs_15 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h10)
regs_16 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h10)
regs_16 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h11)
regs_17 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h11)
regs_17 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h12)
regs_18 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h12)
regs_18 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h13)
regs_19 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h13)
regs_19 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h14)
regs_20 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h14)
regs_20 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h15)
regs_21 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h15)
regs_21 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h16)
regs_22 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h16)
regs_22 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h17)
regs_23 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h17)
regs_23 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h18)
regs_24 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h18)
regs_24 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h19)
regs_25 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h19)
regs_25 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h1A)
regs_26 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h1A)
regs_26 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h1B)
regs_27 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h1B)
regs_27 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h1C)
regs_28 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h1C)
regs_28 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h1D)
regs_29 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h1D)
regs_29 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h1E)
regs_30 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h1E)
regs_30 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h1F)
regs_31 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h1F)
regs_31 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h20)
regs_32 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h20)
regs_32 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h21)
regs_33 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h21)
regs_33 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h22)
regs_34 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h22)
regs_34 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h23)
regs_35 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h23)
regs_35 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h24)
regs_36 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h24)
regs_36 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h25)
regs_37 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h25)
regs_37 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h26)
regs_38 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h26)
regs_38 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h27)
regs_39 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h27)
regs_39 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h28)
regs_40 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h28)
regs_40 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h29)
regs_41 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h29)
regs_41 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h2A)
regs_42 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h2A)
regs_42 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h2B)
regs_43 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h2B)
regs_43 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h2C)
regs_44 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h2C)
regs_44 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h2D)
regs_45 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h2D)
regs_45 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h2E)
regs_46 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h2E)
regs_46 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h2F)
regs_47 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h2F)
regs_47 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h30)
regs_48 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h30)
regs_48 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h31)
regs_49 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h31)
regs_49 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h32)
regs_50 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h32)
regs_50 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h33)
regs_51 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h33)
regs_51 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h34)
regs_52 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h34)
regs_52 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h35)
regs_53 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h35)
regs_53 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h36)
regs_54 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h36)
regs_54 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h37)
regs_55 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h37)
regs_55 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h38)
regs_56 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h38)
regs_56 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h39)
regs_57 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h39)
regs_57 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h3A)
regs_58 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h3A)
regs_58 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h3B)
regs_59 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h3B)
regs_59 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h3C)
regs_60 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h3C)
regs_60 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h3D)
regs_61 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h3D)
regs_61 <= io_wdata_0;
if (_GEN_1 & io_waddr_1 == 6'h3E)
regs_62 <= io_wdata_1;
else if (_GEN_0 & io_waddr_0 == 6'h3E)
regs_62 <= io_wdata_0;
if (_GEN_1 & (&io_waddr_1))
regs_63 <= io_wdata_1;
else if (_GEN_0 & (&io_waddr_0))
regs_63 <= io_wdata_0;
end
end // always @(posedge)
assign io_rdata_0 = io_raddr_0 == 6'h0 ? 64'h0 : _GEN[io_raddr_0];
assign io_rdata_1 = io_raddr_1 == 6'h0 ? 64'h0 : _GEN[io_raddr_1];
assign io_rdata_2 = io_raddr_2 == 6'h0 ? 64'h0 : _GEN[io_raddr_2];
assign io_rdata_3 = io_raddr_3 == 6'h0 ? 64'h0 : _GEN[io_raddr_3];
endmodule

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// Generated by CIRCT firtool-1.139.0
module RenameTable(
input clock,
reset,
input [4:0] io_rs1_0,
io_rs1_1,
io_rs2_0,
io_rs2_1,
io_rd_0,
io_rd_1,
input [5:0] io_newPhys_0,
io_newPhys_1,
input io_wen_0,
io_wen_1,
output [5:0] io_prs1_0,
io_prs1_1,
io_prs2_0,
io_prs2_1,
io_oldPrd_0,
io_oldPrd_1,
input io_commitWen_0,
io_commitWen_1,
input [4:0] io_commitRd_0,
io_commitRd_1,
input [5:0] io_commitPhys_0,
io_commitPhys_1,
input io_recover,
output [5:0] io_committedPhys_0,
io_committedPhys_1,
io_committedPhys_2,
io_committedPhys_3,
io_committedPhys_4,
io_committedPhys_5,
io_committedPhys_6,
io_committedPhys_7,
io_committedPhys_8,
io_committedPhys_9,
io_committedPhys_10,
io_committedPhys_11,
io_committedPhys_12,
io_committedPhys_13,
io_committedPhys_14,
io_committedPhys_15,
io_committedPhys_16,
io_committedPhys_17,
io_committedPhys_18,
io_committedPhys_19,
io_committedPhys_20,
io_committedPhys_21,
io_committedPhys_22,
io_committedPhys_23,
io_committedPhys_24,
io_committedPhys_25,
io_committedPhys_26,
io_committedPhys_27,
io_committedPhys_28,
io_committedPhys_29,
io_committedPhys_30,
io_committedPhys_31
);
reg [5:0] speculative_0;
reg [5:0] speculative_1;
reg [5:0] speculative_2;
reg [5:0] speculative_3;
reg [5:0] speculative_4;
reg [5:0] speculative_5;
reg [5:0] speculative_6;
reg [5:0] speculative_7;
reg [5:0] speculative_8;
reg [5:0] speculative_9;
reg [5:0] speculative_10;
reg [5:0] speculative_11;
reg [5:0] speculative_12;
reg [5:0] speculative_13;
reg [5:0] speculative_14;
reg [5:0] speculative_15;
reg [5:0] speculative_16;
reg [5:0] speculative_17;
reg [5:0] speculative_18;
reg [5:0] speculative_19;
reg [5:0] speculative_20;
reg [5:0] speculative_21;
reg [5:0] speculative_22;
reg [5:0] speculative_23;
reg [5:0] speculative_24;
reg [5:0] speculative_25;
reg [5:0] speculative_26;
reg [5:0] speculative_27;
reg [5:0] speculative_28;
reg [5:0] speculative_29;
reg [5:0] speculative_30;
reg [5:0] speculative_31;
reg [5:0] committed_0;
reg [5:0] committed_1;
reg [5:0] committed_2;
reg [5:0] committed_3;
reg [5:0] committed_4;
reg [5:0] committed_5;
reg [5:0] committed_6;
reg [5:0] committed_7;
reg [5:0] committed_8;
reg [5:0] committed_9;
reg [5:0] committed_10;
reg [5:0] committed_11;
reg [5:0] committed_12;
reg [5:0] committed_13;
reg [5:0] committed_14;
reg [5:0] committed_15;
reg [5:0] committed_16;
reg [5:0] committed_17;
reg [5:0] committed_18;
reg [5:0] committed_19;
reg [5:0] committed_20;
reg [5:0] committed_21;
reg [5:0] committed_22;
reg [5:0] committed_23;
reg [5:0] committed_24;
reg [5:0] committed_25;
reg [5:0] committed_26;
reg [5:0] committed_27;
reg [5:0] committed_28;
reg [5:0] committed_29;
reg [5:0] committed_30;
reg [5:0] committed_31;
wire [31:0][5:0] _GEN =
{{speculative_31},
{speculative_30},
{speculative_29},
{speculative_28},
{speculative_27},
{speculative_26},
{speculative_25},
{speculative_24},
{speculative_23},
{speculative_22},
{speculative_21},
{speculative_20},
{speculative_19},
{speculative_18},
{speculative_17},
{speculative_16},
{speculative_15},
{speculative_14},
{speculative_13},
{speculative_12},
{speculative_11},
{speculative_10},
{speculative_9},
{speculative_8},
{speculative_7},
{speculative_6},
{speculative_5},
{speculative_4},
{speculative_3},
{speculative_2},
{speculative_1},
{speculative_0}};
wire slot0Writes = io_wen_0 & (|io_rd_0);
always @(posedge clock) begin
if (reset) begin
speculative_0 <= 6'h0;
speculative_1 <= 6'h1;
speculative_2 <= 6'h2;
speculative_3 <= 6'h3;
speculative_4 <= 6'h4;
speculative_5 <= 6'h5;
speculative_6 <= 6'h6;
speculative_7 <= 6'h7;
speculative_8 <= 6'h8;
speculative_9 <= 6'h9;
speculative_10 <= 6'hA;
speculative_11 <= 6'hB;
speculative_12 <= 6'hC;
speculative_13 <= 6'hD;
speculative_14 <= 6'hE;
speculative_15 <= 6'hF;
speculative_16 <= 6'h10;
speculative_17 <= 6'h11;
speculative_18 <= 6'h12;
speculative_19 <= 6'h13;
speculative_20 <= 6'h14;
speculative_21 <= 6'h15;
speculative_22 <= 6'h16;
speculative_23 <= 6'h17;
speculative_24 <= 6'h18;
speculative_25 <= 6'h19;
speculative_26 <= 6'h1A;
speculative_27 <= 6'h1B;
speculative_28 <= 6'h1C;
speculative_29 <= 6'h1D;
speculative_30 <= 6'h1E;
speculative_31 <= 6'h1F;
committed_0 <= 6'h0;
committed_1 <= 6'h1;
committed_2 <= 6'h2;
committed_3 <= 6'h3;
committed_4 <= 6'h4;
committed_5 <= 6'h5;
committed_6 <= 6'h6;
committed_7 <= 6'h7;
committed_8 <= 6'h8;
committed_9 <= 6'h9;
committed_10 <= 6'hA;
committed_11 <= 6'hB;
committed_12 <= 6'hC;
committed_13 <= 6'hD;
committed_14 <= 6'hE;
committed_15 <= 6'hF;
committed_16 <= 6'h10;
committed_17 <= 6'h11;
committed_18 <= 6'h12;
committed_19 <= 6'h13;
committed_20 <= 6'h14;
committed_21 <= 6'h15;
committed_22 <= 6'h16;
committed_23 <= 6'h17;
committed_24 <= 6'h18;
committed_25 <= 6'h19;
committed_26 <= 6'h1A;
committed_27 <= 6'h1B;
committed_28 <= 6'h1C;
committed_29 <= 6'h1D;
committed_30 <= 6'h1E;
committed_31 <= 6'h1F;
end
else if (io_recover) begin
speculative_0 <= committed_0;
speculative_1 <= committed_1;
speculative_2 <= committed_2;
speculative_3 <= committed_3;
speculative_4 <= committed_4;
speculative_5 <= committed_5;
speculative_6 <= committed_6;
speculative_7 <= committed_7;
speculative_8 <= committed_8;
speculative_9 <= committed_9;
speculative_10 <= committed_10;
speculative_11 <= committed_11;
speculative_12 <= committed_12;
speculative_13 <= committed_13;
speculative_14 <= committed_14;
speculative_15 <= committed_15;
speculative_16 <= committed_16;
speculative_17 <= committed_17;
speculative_18 <= committed_18;
speculative_19 <= committed_19;
speculative_20 <= committed_20;
speculative_21 <= committed_21;
speculative_22 <= committed_22;
speculative_23 <= committed_23;
speculative_24 <= committed_24;
speculative_25 <= committed_25;
speculative_26 <= committed_26;
speculative_27 <= committed_27;
speculative_28 <= committed_28;
speculative_29 <= committed_29;
speculative_30 <= committed_30;
speculative_31 <= committed_31;
end
else begin
automatic logic _GEN_0;
automatic logic _GEN_1;
automatic logic _GEN_2 = io_wen_1 & (|io_rd_1);
automatic logic _GEN_3 = io_commitWen_1 & (|io_commitRd_1);
_GEN_0 = io_wen_0 & (|io_rd_0);
_GEN_1 = io_commitWen_0 & (|io_commitRd_0);
if (_GEN_2 & ~(|io_rd_1))
speculative_0 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h0)
speculative_0 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1)
speculative_1 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1)
speculative_1 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h2)
speculative_2 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h2)
speculative_2 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h3)
speculative_3 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h3)
speculative_3 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h4)
speculative_4 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h4)
speculative_4 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h5)
speculative_5 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h5)
speculative_5 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h6)
speculative_6 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h6)
speculative_6 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h7)
speculative_7 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h7)
speculative_7 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h8)
speculative_8 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h8)
speculative_8 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h9)
speculative_9 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h9)
speculative_9 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hA)
speculative_10 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hA)
speculative_10 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hB)
speculative_11 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hB)
speculative_11 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hC)
speculative_12 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hC)
speculative_12 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hD)
speculative_13 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hD)
speculative_13 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hE)
speculative_14 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hE)
speculative_14 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hF)
speculative_15 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hF)
speculative_15 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h10)
speculative_16 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h10)
speculative_16 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h11)
speculative_17 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h11)
speculative_17 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h12)
speculative_18 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h12)
speculative_18 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h13)
speculative_19 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h13)
speculative_19 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h14)
speculative_20 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h14)
speculative_20 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h15)
speculative_21 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h15)
speculative_21 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h16)
speculative_22 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h16)
speculative_22 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h17)
speculative_23 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h17)
speculative_23 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h18)
speculative_24 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h18)
speculative_24 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h19)
speculative_25 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h19)
speculative_25 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1A)
speculative_26 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1A)
speculative_26 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1B)
speculative_27 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1B)
speculative_27 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1C)
speculative_28 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1C)
speculative_28 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1D)
speculative_29 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1D)
speculative_29 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1E)
speculative_30 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1E)
speculative_30 <= io_newPhys_0;
if (_GEN_2 & (&io_rd_1))
speculative_31 <= io_newPhys_1;
else if (_GEN_0 & (&io_rd_0))
speculative_31 <= io_newPhys_0;
if (_GEN_3 & ~(|io_commitRd_1))
committed_0 <= io_commitPhys_1;
else if (_GEN_1 & ~(|io_commitRd_0))
committed_0 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1)
committed_1 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1)
committed_1 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h2)
committed_2 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h2)
committed_2 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h3)
committed_3 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h3)
committed_3 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h4)
committed_4 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h4)
committed_4 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h5)
committed_5 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h5)
committed_5 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h6)
committed_6 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h6)
committed_6 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h7)
committed_7 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h7)
committed_7 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h8)
committed_8 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h8)
committed_8 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h9)
committed_9 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h9)
committed_9 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hA)
committed_10 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hA)
committed_10 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hB)
committed_11 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hB)
committed_11 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hC)
committed_12 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hC)
committed_12 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hD)
committed_13 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hD)
committed_13 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hE)
committed_14 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hE)
committed_14 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hF)
committed_15 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hF)
committed_15 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h10)
committed_16 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h10)
committed_16 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h11)
committed_17 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h11)
committed_17 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h12)
committed_18 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h12)
committed_18 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h13)
committed_19 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h13)
committed_19 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h14)
committed_20 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h14)
committed_20 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h15)
committed_21 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h15)
committed_21 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h16)
committed_22 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h16)
committed_22 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h17)
committed_23 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h17)
committed_23 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h18)
committed_24 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h18)
committed_24 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h19)
committed_25 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h19)
committed_25 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1A)
committed_26 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1A)
committed_26 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1B)
committed_27 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1B)
committed_27 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1C)
committed_28 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1C)
committed_28 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1D)
committed_29 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1D)
committed_29 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1E)
committed_30 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1E)
committed_30 <= io_commitPhys_0;
if (_GEN_3 & (&io_commitRd_1))
committed_31 <= io_commitPhys_1;
else if (_GEN_1 & (&io_commitRd_0))
committed_31 <= io_commitPhys_0;
end
end // always @(posedge)
assign io_prs1_0 = _GEN[io_rs1_0];
assign io_prs1_1 = slot0Writes & io_rd_0 == io_rs1_1 ? io_newPhys_0 : _GEN[io_rs1_1];
assign io_prs2_0 = _GEN[io_rs2_0];
assign io_prs2_1 = slot0Writes & io_rd_0 == io_rs2_1 ? io_newPhys_0 : _GEN[io_rs2_1];
assign io_oldPrd_0 = _GEN[io_rd_0];
assign io_oldPrd_1 = slot0Writes & io_rd_0 == io_rd_1 ? io_newPhys_0 : _GEN[io_rd_1];
assign io_committedPhys_0 = committed_0;
assign io_committedPhys_1 = committed_1;
assign io_committedPhys_2 = committed_2;
assign io_committedPhys_3 = committed_3;
assign io_committedPhys_4 = committed_4;
assign io_committedPhys_5 = committed_5;
assign io_committedPhys_6 = committed_6;
assign io_committedPhys_7 = committed_7;
assign io_committedPhys_8 = committed_8;
assign io_committedPhys_9 = committed_9;
assign io_committedPhys_10 = committed_10;
assign io_committedPhys_11 = committed_11;
assign io_committedPhys_12 = committed_12;
assign io_committedPhys_13 = committed_13;
assign io_committedPhys_14 = committed_14;
assign io_committedPhys_15 = committed_15;
assign io_committedPhys_16 = committed_16;
assign io_committedPhys_17 = committed_17;
assign io_committedPhys_18 = committed_18;
assign io_committedPhys_19 = committed_19;
assign io_committedPhys_20 = committed_20;
assign io_committedPhys_21 = committed_21;
assign io_committedPhys_22 = committed_22;
assign io_committedPhys_23 = committed_23;
assign io_committedPhys_24 = committed_24;
assign io_committedPhys_25 = committed_25;
assign io_committedPhys_26 = committed_26;
assign io_committedPhys_27 = committed_27;
assign io_committedPhys_28 = committed_28;
assign io_committedPhys_29 = committed_29;
assign io_committedPhys_30 = committed_30;
assign io_committedPhys_31 = committed_31;
endmodule

3006
generated-ooo/ReservationStation.sv Normal file
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961
generated-ooo/StoreQueue.sv Normal file
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@@ -0,0 +1,961 @@
// Generated by CIRCT firtool-1.139.0
module StoreQueue(
input clock,
reset,
io_enqValid,
input [5:0] io_enqRobIdx,
output [3:0] io_enqIdx,
input io_writeAddr,
io_writeData,
input [3:0] io_writeIdx,
input [63:0] io_addr,
io_data,
input [2:0] io_size,
input [63:0] io_loadAddr,
input [5:0] io_loadRobIdx,
output io_forwardValid,
input io_commitValid,
input [5:0] io_commitRobIdx,
output io_drainValid,
output [63:0] io_drain_addr,
io_drain_data,
output [2:0] io_drain_size,
input io_drainReady,
io_flush
);
reg entries_0_valid;
reg [5:0] entries_0_robIdx;
reg entries_0_addrValid;
reg entries_0_dataValid;
reg [63:0] entries_0_addr;
reg [63:0] entries_0_data;
reg [2:0] entries_0_size;
reg entries_0_committed;
reg entries_1_valid;
reg [5:0] entries_1_robIdx;
reg entries_1_addrValid;
reg entries_1_dataValid;
reg [63:0] entries_1_addr;
reg [63:0] entries_1_data;
reg [2:0] entries_1_size;
reg entries_1_committed;
reg entries_2_valid;
reg [5:0] entries_2_robIdx;
reg entries_2_addrValid;
reg entries_2_dataValid;
reg [63:0] entries_2_addr;
reg [63:0] entries_2_data;
reg [2:0] entries_2_size;
reg entries_2_committed;
reg entries_3_valid;
reg [5:0] entries_3_robIdx;
reg entries_3_addrValid;
reg entries_3_dataValid;
reg [63:0] entries_3_addr;
reg [63:0] entries_3_data;
reg [2:0] entries_3_size;
reg entries_3_committed;
reg entries_4_valid;
reg [5:0] entries_4_robIdx;
reg entries_4_addrValid;
reg entries_4_dataValid;
reg [63:0] entries_4_addr;
reg [63:0] entries_4_data;
reg [2:0] entries_4_size;
reg entries_4_committed;
reg entries_5_valid;
reg [5:0] entries_5_robIdx;
reg entries_5_addrValid;
reg entries_5_dataValid;
reg [63:0] entries_5_addr;
reg [63:0] entries_5_data;
reg [2:0] entries_5_size;
reg entries_5_committed;
reg entries_6_valid;
reg [5:0] entries_6_robIdx;
reg entries_6_addrValid;
reg entries_6_dataValid;
reg [63:0] entries_6_addr;
reg [63:0] entries_6_data;
reg [2:0] entries_6_size;
reg entries_6_committed;
reg entries_7_valid;
reg [5:0] entries_7_robIdx;
reg entries_7_addrValid;
reg entries_7_dataValid;
reg [63:0] entries_7_addr;
reg [63:0] entries_7_data;
reg [2:0] entries_7_size;
reg entries_7_committed;
reg entries_8_valid;
reg [5:0] entries_8_robIdx;
reg entries_8_addrValid;
reg entries_8_dataValid;
reg [63:0] entries_8_addr;
reg [63:0] entries_8_data;
reg [2:0] entries_8_size;
reg entries_8_committed;
reg entries_9_valid;
reg [5:0] entries_9_robIdx;
reg entries_9_addrValid;
reg entries_9_dataValid;
reg [63:0] entries_9_addr;
reg [63:0] entries_9_data;
reg [2:0] entries_9_size;
reg entries_9_committed;
reg entries_10_valid;
reg [5:0] entries_10_robIdx;
reg entries_10_addrValid;
reg entries_10_dataValid;
reg [63:0] entries_10_addr;
reg [63:0] entries_10_data;
reg [2:0] entries_10_size;
reg entries_10_committed;
reg entries_11_valid;
reg [5:0] entries_11_robIdx;
reg entries_11_addrValid;
reg entries_11_dataValid;
reg [63:0] entries_11_addr;
reg [63:0] entries_11_data;
reg [2:0] entries_11_size;
reg entries_11_committed;
reg entries_12_valid;
reg [5:0] entries_12_robIdx;
reg entries_12_addrValid;
reg entries_12_dataValid;
reg [63:0] entries_12_addr;
reg [63:0] entries_12_data;
reg [2:0] entries_12_size;
reg entries_12_committed;
reg entries_13_valid;
reg [5:0] entries_13_robIdx;
reg entries_13_addrValid;
reg entries_13_dataValid;
reg [63:0] entries_13_addr;
reg [63:0] entries_13_data;
reg [2:0] entries_13_size;
reg entries_13_committed;
reg entries_14_valid;
reg [5:0] entries_14_robIdx;
reg entries_14_addrValid;
reg entries_14_dataValid;
reg [63:0] entries_14_addr;
reg [63:0] entries_14_data;
reg [2:0] entries_14_size;
reg entries_14_committed;
reg entries_15_valid;
reg [5:0] entries_15_robIdx;
reg entries_15_addrValid;
reg entries_15_dataValid;
reg [63:0] entries_15_addr;
reg [63:0] entries_15_data;
reg [2:0] entries_15_size;
reg entries_15_committed;
wire [14:0] enqOH =
entries_0_valid
? (entries_1_valid
? (entries_2_valid
? (entries_3_valid
? (entries_4_valid
? (entries_5_valid
? (entries_6_valid
? (entries_7_valid
? (entries_8_valid
? (entries_9_valid
? (entries_10_valid
? (entries_11_valid
? (entries_12_valid
? (entries_13_valid
? (entries_14_valid
? {~entries_15_valid,
14'h0}
: 15'h2000)
: 15'h1000)
: 15'h800)
: 15'h400)
: 15'h200)
: 15'h100)
: 15'h80)
: 15'h40)
: 15'h20)
: 15'h10)
: 15'h8)
: 15'h4)
: 15'h2)
: 15'h1)
: 15'h0;
wire [6:0] _enqIdx_T_1 = enqOH[14:8] | enqOH[6:0];
wire [2:0] _enqIdx_T_3 = _enqIdx_T_1[6:4] | _enqIdx_T_1[2:0];
wire [3:0] enqIdx =
{|(enqOH[14:7]),
|(_enqIdx_T_1[6:3]),
|(_enqIdx_T_3[2:1]),
_enqIdx_T_3[2] | _enqIdx_T_3[0]};
wire drainVec_0 =
entries_0_valid & entries_0_committed & entries_0_addrValid & entries_0_dataValid;
wire drainVec_1 =
entries_1_valid & entries_1_committed & entries_1_addrValid & entries_1_dataValid;
wire drainVec_2 =
entries_2_valid & entries_2_committed & entries_2_addrValid & entries_2_dataValid;
wire drainVec_3 =
entries_3_valid & entries_3_committed & entries_3_addrValid & entries_3_dataValid;
wire drainVec_4 =
entries_4_valid & entries_4_committed & entries_4_addrValid & entries_4_dataValid;
wire drainVec_5 =
entries_5_valid & entries_5_committed & entries_5_addrValid & entries_5_dataValid;
wire drainVec_6 =
entries_6_valid & entries_6_committed & entries_6_addrValid & entries_6_dataValid;
wire drainVec_7 =
entries_7_valid & entries_7_committed & entries_7_addrValid & entries_7_dataValid;
wire drainVec_8 =
entries_8_valid & entries_8_committed & entries_8_addrValid & entries_8_dataValid;
wire drainVec_9 =
entries_9_valid & entries_9_committed & entries_9_addrValid & entries_9_dataValid;
wire drainVec_10 =
entries_10_valid & entries_10_committed & entries_10_addrValid & entries_10_dataValid;
wire drainVec_11 =
entries_11_valid & entries_11_committed & entries_11_addrValid & entries_11_dataValid;
wire drainVec_12 =
entries_12_valid & entries_12_committed & entries_12_addrValid & entries_12_dataValid;
wire drainVec_13 =
entries_13_valid & entries_13_committed & entries_13_addrValid & entries_13_dataValid;
wire drainVec_14 =
entries_14_valid & entries_14_committed & entries_14_addrValid & entries_14_dataValid;
wire drainVec_15 =
entries_15_valid & entries_15_committed & entries_15_addrValid & entries_15_dataValid;
wire [15:0] _io_drainValid_T =
{drainVec_15,
drainVec_14,
drainVec_13,
drainVec_12,
drainVec_11,
drainVec_10,
drainVec_9,
drainVec_8,
drainVec_7,
drainVec_6,
drainVec_5,
drainVec_4,
drainVec_3,
drainVec_2,
drainVec_1,
drainVec_0};
wire [14:0] drainOH =
drainVec_0
? 15'h0
: drainVec_1
? 15'h1
: drainVec_2
? 15'h2
: drainVec_3
? 15'h4
: drainVec_4
? 15'h8
: drainVec_5
? 15'h10
: drainVec_6
? 15'h20
: drainVec_7
? 15'h40
: drainVec_8
? 15'h80
: drainVec_9
? 15'h100
: drainVec_10
? 15'h200
: drainVec_11
? 15'h400
: drainVec_12
? 15'h800
: drainVec_13
? 15'h1000
: drainVec_14
? 15'h2000
: {drainVec_15, 14'h0};
wire [6:0] _drainIdx_T_1 = drainOH[14:8] | drainOH[6:0];
wire [2:0] _drainIdx_T_3 = _drainIdx_T_1[6:4] | _drainIdx_T_1[2:0];
wire [3:0] drainIdx =
{|(drainOH[14:7]),
|(_drainIdx_T_1[6:3]),
|(_drainIdx_T_3[2:1]),
_drainIdx_T_3[2] | _drainIdx_T_3[0]};
wire [15:0][63:0] _GEN =
{{entries_15_addr},
{entries_14_addr},
{entries_13_addr},
{entries_12_addr},
{entries_11_addr},
{entries_10_addr},
{entries_9_addr},
{entries_8_addr},
{entries_7_addr},
{entries_6_addr},
{entries_5_addr},
{entries_4_addr},
{entries_3_addr},
{entries_2_addr},
{entries_1_addr},
{entries_0_addr}};
wire [15:0][63:0] _GEN_0 =
{{entries_15_data},
{entries_14_data},
{entries_13_data},
{entries_12_data},
{entries_11_data},
{entries_10_data},
{entries_9_data},
{entries_8_data},
{entries_7_data},
{entries_6_data},
{entries_5_data},
{entries_4_data},
{entries_3_data},
{entries_2_data},
{entries_1_data},
{entries_0_data}};
wire [15:0][2:0] _GEN_1 =
{{entries_15_size},
{entries_14_size},
{entries_13_size},
{entries_12_size},
{entries_11_size},
{entries_10_size},
{entries_9_size},
{entries_8_size},
{entries_7_size},
{entries_6_size},
{entries_5_size},
{entries_4_size},
{entries_3_size},
{entries_2_size},
{entries_1_size},
{entries_0_size}};
always @(posedge clock) begin
if (reset) begin
entries_0_valid <= 1'h0;
entries_0_robIdx <= 6'h0;
entries_0_addrValid <= 1'h0;
entries_0_dataValid <= 1'h0;
entries_0_addr <= 64'h0;
entries_0_data <= 64'h0;
entries_0_size <= 3'h0;
entries_0_committed <= 1'h0;
entries_1_valid <= 1'h0;
entries_1_robIdx <= 6'h0;
entries_1_addrValid <= 1'h0;
entries_1_dataValid <= 1'h0;
entries_1_addr <= 64'h0;
entries_1_data <= 64'h0;
entries_1_size <= 3'h0;
entries_1_committed <= 1'h0;
entries_2_valid <= 1'h0;
entries_2_robIdx <= 6'h0;
entries_2_addrValid <= 1'h0;
entries_2_dataValid <= 1'h0;
entries_2_addr <= 64'h0;
entries_2_data <= 64'h0;
entries_2_size <= 3'h0;
entries_2_committed <= 1'h0;
entries_3_valid <= 1'h0;
entries_3_robIdx <= 6'h0;
entries_3_addrValid <= 1'h0;
entries_3_dataValid <= 1'h0;
entries_3_addr <= 64'h0;
entries_3_data <= 64'h0;
entries_3_size <= 3'h0;
entries_3_committed <= 1'h0;
entries_4_valid <= 1'h0;
entries_4_robIdx <= 6'h0;
entries_4_addrValid <= 1'h0;
entries_4_dataValid <= 1'h0;
entries_4_addr <= 64'h0;
entries_4_data <= 64'h0;
entries_4_size <= 3'h0;
entries_4_committed <= 1'h0;
entries_5_valid <= 1'h0;
entries_5_robIdx <= 6'h0;
entries_5_addrValid <= 1'h0;
entries_5_dataValid <= 1'h0;
entries_5_addr <= 64'h0;
entries_5_data <= 64'h0;
entries_5_size <= 3'h0;
entries_5_committed <= 1'h0;
entries_6_valid <= 1'h0;
entries_6_robIdx <= 6'h0;
entries_6_addrValid <= 1'h0;
entries_6_dataValid <= 1'h0;
entries_6_addr <= 64'h0;
entries_6_data <= 64'h0;
entries_6_size <= 3'h0;
entries_6_committed <= 1'h0;
entries_7_valid <= 1'h0;
entries_7_robIdx <= 6'h0;
entries_7_addrValid <= 1'h0;
entries_7_dataValid <= 1'h0;
entries_7_addr <= 64'h0;
entries_7_data <= 64'h0;
entries_7_size <= 3'h0;
entries_7_committed <= 1'h0;
entries_8_valid <= 1'h0;
entries_8_robIdx <= 6'h0;
entries_8_addrValid <= 1'h0;
entries_8_dataValid <= 1'h0;
entries_8_addr <= 64'h0;
entries_8_data <= 64'h0;
entries_8_size <= 3'h0;
entries_8_committed <= 1'h0;
entries_9_valid <= 1'h0;
entries_9_robIdx <= 6'h0;
entries_9_addrValid <= 1'h0;
entries_9_dataValid <= 1'h0;
entries_9_addr <= 64'h0;
entries_9_data <= 64'h0;
entries_9_size <= 3'h0;
entries_9_committed <= 1'h0;
entries_10_valid <= 1'h0;
entries_10_robIdx <= 6'h0;
entries_10_addrValid <= 1'h0;
entries_10_dataValid <= 1'h0;
entries_10_addr <= 64'h0;
entries_10_data <= 64'h0;
entries_10_size <= 3'h0;
entries_10_committed <= 1'h0;
entries_11_valid <= 1'h0;
entries_11_robIdx <= 6'h0;
entries_11_addrValid <= 1'h0;
entries_11_dataValid <= 1'h0;
entries_11_addr <= 64'h0;
entries_11_data <= 64'h0;
entries_11_size <= 3'h0;
entries_11_committed <= 1'h0;
entries_12_valid <= 1'h0;
entries_12_robIdx <= 6'h0;
entries_12_addrValid <= 1'h0;
entries_12_dataValid <= 1'h0;
entries_12_addr <= 64'h0;
entries_12_data <= 64'h0;
entries_12_size <= 3'h0;
entries_12_committed <= 1'h0;
entries_13_valid <= 1'h0;
entries_13_robIdx <= 6'h0;
entries_13_addrValid <= 1'h0;
entries_13_dataValid <= 1'h0;
entries_13_addr <= 64'h0;
entries_13_data <= 64'h0;
entries_13_size <= 3'h0;
entries_13_committed <= 1'h0;
entries_14_valid <= 1'h0;
entries_14_robIdx <= 6'h0;
entries_14_addrValid <= 1'h0;
entries_14_dataValid <= 1'h0;
entries_14_addr <= 64'h0;
entries_14_data <= 64'h0;
entries_14_size <= 3'h0;
entries_14_committed <= 1'h0;
entries_15_valid <= 1'h0;
entries_15_robIdx <= 6'h0;
entries_15_addrValid <= 1'h0;
entries_15_dataValid <= 1'h0;
entries_15_addr <= 64'h0;
entries_15_data <= 64'h0;
entries_15_size <= 3'h0;
entries_15_committed <= 1'h0;
end
else begin
automatic logic _GEN_2 =
io_enqValid
& (|{~entries_15_valid,
~entries_14_valid,
~entries_13_valid,
~entries_12_valid,
~entries_11_valid,
~entries_10_valid,
~entries_9_valid,
~entries_8_valid,
~entries_7_valid,
~entries_6_valid,
~entries_5_valid,
~entries_4_valid,
~entries_3_valid,
~entries_2_valid,
~entries_1_valid,
~entries_0_valid});
automatic logic _GEN_3;
automatic logic _GEN_4;
automatic logic _GEN_5;
automatic logic _GEN_6;
automatic logic _GEN_7;
automatic logic _GEN_8;
automatic logic _GEN_9;
automatic logic _GEN_10;
automatic logic _GEN_11;
automatic logic _GEN_12;
automatic logic _GEN_13;
automatic logic _GEN_14;
automatic logic _GEN_15;
automatic logic _GEN_16;
automatic logic _GEN_17;
automatic logic _GEN_18;
automatic logic _GEN_19 = io_writeIdx == 4'h0;
automatic logic _GEN_20;
automatic logic _GEN_21 = io_writeIdx == 4'h1;
automatic logic _GEN_22;
automatic logic _GEN_23 = io_writeIdx == 4'h2;
automatic logic _GEN_24;
automatic logic _GEN_25 = io_writeIdx == 4'h3;
automatic logic _GEN_26;
automatic logic _GEN_27 = io_writeIdx == 4'h4;
automatic logic _GEN_28;
automatic logic _GEN_29 = io_writeIdx == 4'h5;
automatic logic _GEN_30;
automatic logic _GEN_31 = io_writeIdx == 4'h6;
automatic logic _GEN_32;
automatic logic _GEN_33 = io_writeIdx == 4'h7;
automatic logic _GEN_34;
automatic logic _GEN_35 = io_writeIdx == 4'h8;
automatic logic _GEN_36;
automatic logic _GEN_37 = io_writeIdx == 4'h9;
automatic logic _GEN_38;
automatic logic _GEN_39 = io_writeIdx == 4'hA;
automatic logic _GEN_40;
automatic logic _GEN_41 = io_writeIdx == 4'hB;
automatic logic _GEN_42;
automatic logic _GEN_43 = io_writeIdx == 4'hC;
automatic logic _GEN_44;
automatic logic _GEN_45 = io_writeIdx == 4'hD;
automatic logic _GEN_46;
automatic logic _GEN_47 = io_writeIdx == 4'hE;
automatic logic _GEN_48;
automatic logic _GEN_49;
automatic logic _GEN_50;
automatic logic _GEN_51;
automatic logic _GEN_52;
automatic logic _GEN_53;
automatic logic _GEN_54;
automatic logic _GEN_55;
automatic logic _GEN_56;
automatic logic _GEN_57;
automatic logic _GEN_58;
automatic logic _GEN_59;
automatic logic _GEN_60;
automatic logic _GEN_61;
automatic logic _GEN_62;
automatic logic _GEN_63;
automatic logic _GEN_64;
automatic logic _GEN_65;
automatic logic _GEN_66 = (|_io_drainValid_T) & io_drainReady;
_GEN_3 = _GEN_2 & enqIdx == 4'h0;
_GEN_4 = _GEN_2 & enqIdx == 4'h1;
_GEN_5 = _GEN_2 & enqIdx == 4'h2;
_GEN_6 = _GEN_2 & enqIdx == 4'h3;
_GEN_7 = _GEN_2 & enqIdx == 4'h4;
_GEN_8 = _GEN_2 & enqIdx == 4'h5;
_GEN_9 = _GEN_2 & enqIdx == 4'h6;
_GEN_10 = _GEN_2 & enqIdx == 4'h7;
_GEN_11 = _GEN_2 & enqIdx == 4'h8;
_GEN_12 = _GEN_2 & enqIdx == 4'h9;
_GEN_13 = _GEN_2 & enqIdx == 4'hA;
_GEN_14 = _GEN_2 & enqIdx == 4'hB;
_GEN_15 = _GEN_2 & enqIdx == 4'hC;
_GEN_16 = _GEN_2 & enqIdx == 4'hD;
_GEN_17 = _GEN_2 & enqIdx == 4'hE;
_GEN_18 = _GEN_2 & (&enqIdx);
_GEN_20 = io_writeAddr & _GEN_19;
_GEN_22 = io_writeAddr & _GEN_21;
_GEN_24 = io_writeAddr & _GEN_23;
_GEN_26 = io_writeAddr & _GEN_25;
_GEN_28 = io_writeAddr & _GEN_27;
_GEN_30 = io_writeAddr & _GEN_29;
_GEN_32 = io_writeAddr & _GEN_31;
_GEN_34 = io_writeAddr & _GEN_33;
_GEN_36 = io_writeAddr & _GEN_35;
_GEN_38 = io_writeAddr & _GEN_37;
_GEN_40 = io_writeAddr & _GEN_39;
_GEN_42 = io_writeAddr & _GEN_41;
_GEN_44 = io_writeAddr & _GEN_43;
_GEN_46 = io_writeAddr & _GEN_45;
_GEN_48 = io_writeAddr & _GEN_47;
_GEN_49 = io_writeAddr & (&io_writeIdx);
_GEN_50 = io_writeData & _GEN_19;
_GEN_51 = io_writeData & _GEN_21;
_GEN_52 = io_writeData & _GEN_23;
_GEN_53 = io_writeData & _GEN_25;
_GEN_54 = io_writeData & _GEN_27;
_GEN_55 = io_writeData & _GEN_29;
_GEN_56 = io_writeData & _GEN_31;
_GEN_57 = io_writeData & _GEN_33;
_GEN_58 = io_writeData & _GEN_35;
_GEN_59 = io_writeData & _GEN_37;
_GEN_60 = io_writeData & _GEN_39;
_GEN_61 = io_writeData & _GEN_41;
_GEN_62 = io_writeData & _GEN_43;
_GEN_63 = io_writeData & _GEN_45;
_GEN_64 = io_writeData & _GEN_47;
_GEN_65 = io_writeData & (&io_writeIdx);
entries_0_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'h0) & (_GEN_3 | entries_0_valid);
if (io_flush) begin
entries_0_robIdx <= 6'h0;
entries_0_addr <= 64'h0;
entries_0_data <= 64'h0;
entries_0_size <= 3'h0;
entries_1_robIdx <= 6'h0;
entries_1_addr <= 64'h0;
entries_1_data <= 64'h0;
entries_1_size <= 3'h0;
entries_2_robIdx <= 6'h0;
entries_2_addr <= 64'h0;
entries_2_data <= 64'h0;
entries_2_size <= 3'h0;
entries_3_robIdx <= 6'h0;
entries_3_addr <= 64'h0;
entries_3_data <= 64'h0;
entries_3_size <= 3'h0;
entries_4_robIdx <= 6'h0;
entries_4_addr <= 64'h0;
entries_4_data <= 64'h0;
entries_4_size <= 3'h0;
entries_5_robIdx <= 6'h0;
entries_5_addr <= 64'h0;
entries_5_data <= 64'h0;
entries_5_size <= 3'h0;
entries_6_robIdx <= 6'h0;
entries_6_addr <= 64'h0;
entries_6_data <= 64'h0;
entries_6_size <= 3'h0;
entries_7_robIdx <= 6'h0;
entries_7_addr <= 64'h0;
entries_7_data <= 64'h0;
entries_7_size <= 3'h0;
entries_8_robIdx <= 6'h0;
entries_8_addr <= 64'h0;
entries_8_data <= 64'h0;
entries_8_size <= 3'h0;
entries_9_robIdx <= 6'h0;
entries_9_addr <= 64'h0;
entries_9_data <= 64'h0;
entries_9_size <= 3'h0;
entries_10_robIdx <= 6'h0;
entries_10_addr <= 64'h0;
entries_10_data <= 64'h0;
entries_10_size <= 3'h0;
entries_11_robIdx <= 6'h0;
entries_11_addr <= 64'h0;
entries_11_data <= 64'h0;
entries_11_size <= 3'h0;
entries_12_robIdx <= 6'h0;
entries_12_addr <= 64'h0;
entries_12_data <= 64'h0;
entries_12_size <= 3'h0;
entries_13_robIdx <= 6'h0;
entries_13_addr <= 64'h0;
entries_13_data <= 64'h0;
entries_13_size <= 3'h0;
entries_14_robIdx <= 6'h0;
entries_14_addr <= 64'h0;
entries_14_data <= 64'h0;
entries_14_size <= 3'h0;
entries_15_robIdx <= 6'h0;
entries_15_addr <= 64'h0;
entries_15_data <= 64'h0;
entries_15_size <= 3'h0;
end
else begin
if (_GEN_3)
entries_0_robIdx <= io_enqRobIdx;
if (_GEN_20) begin
entries_0_addr <= io_addr;
entries_0_size <= io_size;
end
if (_GEN_50)
entries_0_data <= io_data;
if (_GEN_4)
entries_1_robIdx <= io_enqRobIdx;
if (_GEN_22) begin
entries_1_addr <= io_addr;
entries_1_size <= io_size;
end
if (_GEN_51)
entries_1_data <= io_data;
if (_GEN_5)
entries_2_robIdx <= io_enqRobIdx;
if (_GEN_24) begin
entries_2_addr <= io_addr;
entries_2_size <= io_size;
end
if (_GEN_52)
entries_2_data <= io_data;
if (_GEN_6)
entries_3_robIdx <= io_enqRobIdx;
if (_GEN_26) begin
entries_3_addr <= io_addr;
entries_3_size <= io_size;
end
if (_GEN_53)
entries_3_data <= io_data;
if (_GEN_7)
entries_4_robIdx <= io_enqRobIdx;
if (_GEN_28) begin
entries_4_addr <= io_addr;
entries_4_size <= io_size;
end
if (_GEN_54)
entries_4_data <= io_data;
if (_GEN_8)
entries_5_robIdx <= io_enqRobIdx;
if (_GEN_30) begin
entries_5_addr <= io_addr;
entries_5_size <= io_size;
end
if (_GEN_55)
entries_5_data <= io_data;
if (_GEN_9)
entries_6_robIdx <= io_enqRobIdx;
if (_GEN_32) begin
entries_6_addr <= io_addr;
entries_6_size <= io_size;
end
if (_GEN_56)
entries_6_data <= io_data;
if (_GEN_10)
entries_7_robIdx <= io_enqRobIdx;
if (_GEN_34) begin
entries_7_addr <= io_addr;
entries_7_size <= io_size;
end
if (_GEN_57)
entries_7_data <= io_data;
if (_GEN_11)
entries_8_robIdx <= io_enqRobIdx;
if (_GEN_36) begin
entries_8_addr <= io_addr;
entries_8_size <= io_size;
end
if (_GEN_58)
entries_8_data <= io_data;
if (_GEN_12)
entries_9_robIdx <= io_enqRobIdx;
if (_GEN_38) begin
entries_9_addr <= io_addr;
entries_9_size <= io_size;
end
if (_GEN_59)
entries_9_data <= io_data;
if (_GEN_13)
entries_10_robIdx <= io_enqRobIdx;
if (_GEN_40) begin
entries_10_addr <= io_addr;
entries_10_size <= io_size;
end
if (_GEN_60)
entries_10_data <= io_data;
if (_GEN_14)
entries_11_robIdx <= io_enqRobIdx;
if (_GEN_42) begin
entries_11_addr <= io_addr;
entries_11_size <= io_size;
end
if (_GEN_61)
entries_11_data <= io_data;
if (_GEN_15)
entries_12_robIdx <= io_enqRobIdx;
if (_GEN_44) begin
entries_12_addr <= io_addr;
entries_12_size <= io_size;
end
if (_GEN_62)
entries_12_data <= io_data;
if (_GEN_16)
entries_13_robIdx <= io_enqRobIdx;
if (_GEN_46) begin
entries_13_addr <= io_addr;
entries_13_size <= io_size;
end
if (_GEN_63)
entries_13_data <= io_data;
if (_GEN_17)
entries_14_robIdx <= io_enqRobIdx;
if (_GEN_48) begin
entries_14_addr <= io_addr;
entries_14_size <= io_size;
end
if (_GEN_64)
entries_14_data <= io_data;
if (_GEN_18)
entries_15_robIdx <= io_enqRobIdx;
if (_GEN_49) begin
entries_15_addr <= io_addr;
entries_15_size <= io_size;
end
if (_GEN_65)
entries_15_data <= io_data;
end
entries_0_addrValid <= ~io_flush & (_GEN_20 | ~_GEN_3 & entries_0_addrValid);
entries_0_dataValid <= ~io_flush & (_GEN_50 | ~_GEN_3 & entries_0_dataValid);
entries_0_committed <=
~io_flush
& (io_commitValid & entries_0_valid & entries_0_robIdx == io_commitRobIdx
| ~_GEN_3 & entries_0_committed);
entries_1_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'h1) & (_GEN_4 | entries_1_valid);
entries_1_addrValid <= ~io_flush & (_GEN_22 | ~_GEN_4 & entries_1_addrValid);
entries_1_dataValid <= ~io_flush & (_GEN_51 | ~_GEN_4 & entries_1_dataValid);
entries_1_committed <=
~io_flush
& (io_commitValid & entries_1_valid & entries_1_robIdx == io_commitRobIdx
| ~_GEN_4 & entries_1_committed);
entries_2_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'h2) & (_GEN_5 | entries_2_valid);
entries_2_addrValid <= ~io_flush & (_GEN_24 | ~_GEN_5 & entries_2_addrValid);
entries_2_dataValid <= ~io_flush & (_GEN_52 | ~_GEN_5 & entries_2_dataValid);
entries_2_committed <=
~io_flush
& (io_commitValid & entries_2_valid & entries_2_robIdx == io_commitRobIdx
| ~_GEN_5 & entries_2_committed);
entries_3_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'h3) & (_GEN_6 | entries_3_valid);
entries_3_addrValid <= ~io_flush & (_GEN_26 | ~_GEN_6 & entries_3_addrValid);
entries_3_dataValid <= ~io_flush & (_GEN_53 | ~_GEN_6 & entries_3_dataValid);
entries_3_committed <=
~io_flush
& (io_commitValid & entries_3_valid & entries_3_robIdx == io_commitRobIdx
| ~_GEN_6 & entries_3_committed);
entries_4_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'h4) & (_GEN_7 | entries_4_valid);
entries_4_addrValid <= ~io_flush & (_GEN_28 | ~_GEN_7 & entries_4_addrValid);
entries_4_dataValid <= ~io_flush & (_GEN_54 | ~_GEN_7 & entries_4_dataValid);
entries_4_committed <=
~io_flush
& (io_commitValid & entries_4_valid & entries_4_robIdx == io_commitRobIdx
| ~_GEN_7 & entries_4_committed);
entries_5_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'h5) & (_GEN_8 | entries_5_valid);
entries_5_addrValid <= ~io_flush & (_GEN_30 | ~_GEN_8 & entries_5_addrValid);
entries_5_dataValid <= ~io_flush & (_GEN_55 | ~_GEN_8 & entries_5_dataValid);
entries_5_committed <=
~io_flush
& (io_commitValid & entries_5_valid & entries_5_robIdx == io_commitRobIdx
| ~_GEN_8 & entries_5_committed);
entries_6_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'h6) & (_GEN_9 | entries_6_valid);
entries_6_addrValid <= ~io_flush & (_GEN_32 | ~_GEN_9 & entries_6_addrValid);
entries_6_dataValid <= ~io_flush & (_GEN_56 | ~_GEN_9 & entries_6_dataValid);
entries_6_committed <=
~io_flush
& (io_commitValid & entries_6_valid & entries_6_robIdx == io_commitRobIdx
| ~_GEN_9 & entries_6_committed);
entries_7_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'h7) & (_GEN_10 | entries_7_valid);
entries_7_addrValid <= ~io_flush & (_GEN_34 | ~_GEN_10 & entries_7_addrValid);
entries_7_dataValid <= ~io_flush & (_GEN_57 | ~_GEN_10 & entries_7_dataValid);
entries_7_committed <=
~io_flush
& (io_commitValid & entries_7_valid & entries_7_robIdx == io_commitRobIdx
| ~_GEN_10 & entries_7_committed);
entries_8_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'h8) & (_GEN_11 | entries_8_valid);
entries_8_addrValid <= ~io_flush & (_GEN_36 | ~_GEN_11 & entries_8_addrValid);
entries_8_dataValid <= ~io_flush & (_GEN_58 | ~_GEN_11 & entries_8_dataValid);
entries_8_committed <=
~io_flush
& (io_commitValid & entries_8_valid & entries_8_robIdx == io_commitRobIdx
| ~_GEN_11 & entries_8_committed);
entries_9_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'h9) & (_GEN_12 | entries_9_valid);
entries_9_addrValid <= ~io_flush & (_GEN_38 | ~_GEN_12 & entries_9_addrValid);
entries_9_dataValid <= ~io_flush & (_GEN_59 | ~_GEN_12 & entries_9_dataValid);
entries_9_committed <=
~io_flush
& (io_commitValid & entries_9_valid & entries_9_robIdx == io_commitRobIdx
| ~_GEN_12 & entries_9_committed);
entries_10_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'hA) & (_GEN_13 | entries_10_valid);
entries_10_addrValid <= ~io_flush & (_GEN_40 | ~_GEN_13 & entries_10_addrValid);
entries_10_dataValid <= ~io_flush & (_GEN_60 | ~_GEN_13 & entries_10_dataValid);
entries_10_committed <=
~io_flush
& (io_commitValid & entries_10_valid & entries_10_robIdx == io_commitRobIdx
| ~_GEN_13 & entries_10_committed);
entries_11_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'hB) & (_GEN_14 | entries_11_valid);
entries_11_addrValid <= ~io_flush & (_GEN_42 | ~_GEN_14 & entries_11_addrValid);
entries_11_dataValid <= ~io_flush & (_GEN_61 | ~_GEN_14 & entries_11_dataValid);
entries_11_committed <=
~io_flush
& (io_commitValid & entries_11_valid & entries_11_robIdx == io_commitRobIdx
| ~_GEN_14 & entries_11_committed);
entries_12_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'hC) & (_GEN_15 | entries_12_valid);
entries_12_addrValid <= ~io_flush & (_GEN_44 | ~_GEN_15 & entries_12_addrValid);
entries_12_dataValid <= ~io_flush & (_GEN_62 | ~_GEN_15 & entries_12_dataValid);
entries_12_committed <=
~io_flush
& (io_commitValid & entries_12_valid & entries_12_robIdx == io_commitRobIdx
| ~_GEN_15 & entries_12_committed);
entries_13_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'hD) & (_GEN_16 | entries_13_valid);
entries_13_addrValid <= ~io_flush & (_GEN_46 | ~_GEN_16 & entries_13_addrValid);
entries_13_dataValid <= ~io_flush & (_GEN_63 | ~_GEN_16 & entries_13_dataValid);
entries_13_committed <=
~io_flush
& (io_commitValid & entries_13_valid & entries_13_robIdx == io_commitRobIdx
| ~_GEN_16 & entries_13_committed);
entries_14_valid <=
~(io_flush | _GEN_66 & drainIdx == 4'hE) & (_GEN_17 | entries_14_valid);
entries_14_addrValid <= ~io_flush & (_GEN_48 | ~_GEN_17 & entries_14_addrValid);
entries_14_dataValid <= ~io_flush & (_GEN_64 | ~_GEN_17 & entries_14_dataValid);
entries_14_committed <=
~io_flush
& (io_commitValid & entries_14_valid & entries_14_robIdx == io_commitRobIdx
| ~_GEN_17 & entries_14_committed);
entries_15_valid <=
~(io_flush | _GEN_66 & (&drainIdx)) & (_GEN_18 | entries_15_valid);
entries_15_addrValid <= ~io_flush & (_GEN_49 | ~_GEN_18 & entries_15_addrValid);
entries_15_dataValid <= ~io_flush & (_GEN_65 | ~_GEN_18 & entries_15_dataValid);
entries_15_committed <=
~io_flush
& (io_commitValid & entries_15_valid & entries_15_robIdx == io_commitRobIdx
| ~_GEN_18 & entries_15_committed);
end
end // always @(posedge)
assign io_enqIdx = enqIdx;
assign io_forwardValid =
|{entries_15_valid & entries_15_addrValid & entries_15_dataValid
& entries_15_robIdx < io_loadRobIdx & entries_15_addr[63:3] == io_loadAddr[63:3],
entries_14_valid & entries_14_addrValid & entries_14_dataValid
& entries_14_robIdx < io_loadRobIdx & entries_14_addr[63:3] == io_loadAddr[63:3],
entries_13_valid & entries_13_addrValid & entries_13_dataValid
& entries_13_robIdx < io_loadRobIdx & entries_13_addr[63:3] == io_loadAddr[63:3],
entries_12_valid & entries_12_addrValid & entries_12_dataValid
& entries_12_robIdx < io_loadRobIdx & entries_12_addr[63:3] == io_loadAddr[63:3],
entries_11_valid & entries_11_addrValid & entries_11_dataValid
& entries_11_robIdx < io_loadRobIdx & entries_11_addr[63:3] == io_loadAddr[63:3],
entries_10_valid & entries_10_addrValid & entries_10_dataValid
& entries_10_robIdx < io_loadRobIdx & entries_10_addr[63:3] == io_loadAddr[63:3],
entries_9_valid & entries_9_addrValid & entries_9_dataValid
& entries_9_robIdx < io_loadRobIdx & entries_9_addr[63:3] == io_loadAddr[63:3],
entries_8_valid & entries_8_addrValid & entries_8_dataValid
& entries_8_robIdx < io_loadRobIdx & entries_8_addr[63:3] == io_loadAddr[63:3],
entries_7_valid & entries_7_addrValid & entries_7_dataValid
& entries_7_robIdx < io_loadRobIdx & entries_7_addr[63:3] == io_loadAddr[63:3],
entries_6_valid & entries_6_addrValid & entries_6_dataValid
& entries_6_robIdx < io_loadRobIdx & entries_6_addr[63:3] == io_loadAddr[63:3],
entries_5_valid & entries_5_addrValid & entries_5_dataValid
& entries_5_robIdx < io_loadRobIdx & entries_5_addr[63:3] == io_loadAddr[63:3],
entries_4_valid & entries_4_addrValid & entries_4_dataValid
& entries_4_robIdx < io_loadRobIdx & entries_4_addr[63:3] == io_loadAddr[63:3],
entries_3_valid & entries_3_addrValid & entries_3_dataValid
& entries_3_robIdx < io_loadRobIdx & entries_3_addr[63:3] == io_loadAddr[63:3],
entries_2_valid & entries_2_addrValid & entries_2_dataValid
& entries_2_robIdx < io_loadRobIdx & entries_2_addr[63:3] == io_loadAddr[63:3],
entries_1_valid & entries_1_addrValid & entries_1_dataValid
& entries_1_robIdx < io_loadRobIdx & entries_1_addr[63:3] == io_loadAddr[63:3],
entries_0_valid & entries_0_addrValid & entries_0_dataValid
& entries_0_robIdx < io_loadRobIdx & entries_0_addr[63:3] == io_loadAddr[63:3]};
assign io_drainValid = |_io_drainValid_T;
assign io_drain_addr = _GEN[drainIdx];
assign io_drain_data = _GEN_0[drainIdx];
assign io_drain_size = _GEN_1[drainIdx];
endmodule

15
generated-ooo/WriteBackStage.sv Normal file
View File

@@ -0,0 +1,15 @@
// Generated by CIRCT firtool-1.139.0
module WriteBackStage(
input io_valid,
input [5:0] io_physDest,
input [63:0] io_data,
output io_wen,
output [5:0] io_waddr,
output [63:0] io_wdata
);
assign io_wen = io_valid;
assign io_waddr = io_physDest;
assign io_wdata = io_data;
endmodule

27
generated-ooo/data_1024x256.sv Normal file
View File

@@ -0,0 +1,27 @@
// Generated by CIRCT firtool-1.139.0
// VCS coverage exclude_file
module data_1024x256(
input [9:0] R0_addr,
input R0_en,
R0_clk,
output [255:0] R0_data,
input [9:0] W0_addr,
input W0_en,
W0_clk,
input [255:0] W0_data
);
reg [255:0] Memory[0:1023];
reg _R0_en_d0;
reg [9:0] _R0_addr_d0;
always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr;
end // always @(posedge)
always @(posedge W0_clk) begin
if (W0_en)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 256'bx;
endmodule

27
generated-ooo/data_64x4096.sv Normal file
View File

@@ -0,0 +1,27 @@
// Generated by CIRCT firtool-1.139.0
// VCS coverage exclude_file
module data_64x4096(
input [5:0] R0_addr,
input R0_en,
R0_clk,
output [4095:0] R0_data,
input [5:0] W0_addr,
input W0_en,
W0_clk,
input [4095:0] W0_data
);
reg [4095:0] Memory[0:63];
reg _R0_en_d0;
reg [5:0] _R0_addr_d0;
always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr;
end // always @(posedge)
always @(posedge W0_clk) begin
if (W0_en)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 4096'bx;
endmodule

31
generated-ooo/filelist.f Normal file
View File

@@ -0,0 +1,31 @@
tags_1024x204.sv
data_1024x256.sv
ICache.sv
Frontend.sv
Decoder.sv
IDStage.sv
RenameTable.sv
FreeList.sv
ROB.sv
RenameStage.sv
ReservationStation.sv
IssueQueue.sv
IssueStage.sv
PhysicalRegFile.sv
ALU.sv
BranchUnit.sv
ExecStage.sv
WriteBackStage.sv
CommitStage.sv
LoadQueue.sv
StoreQueue.sv
DTLB.sv
PageTableWalker.sv
MMU.sv
tags_64x416.sv
data_64x4096.sv
DCache.sv
LSU.sv
CSRFile.sv
OoOBackend.sv
Core.sv

27
generated-ooo/tags_1024x204.sv Normal file
View File

@@ -0,0 +1,27 @@
// Generated by CIRCT firtool-1.139.0
// VCS coverage exclude_file
module tags_1024x204(
input [9:0] R0_addr,
input R0_en,
R0_clk,
output [203:0] R0_data,
input [9:0] W0_addr,
input W0_en,
W0_clk,
input [203:0] W0_data
);
reg [203:0] Memory[0:1023];
reg _R0_en_d0;
reg [9:0] _R0_addr_d0;
always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr;
end // always @(posedge)
always @(posedge W0_clk) begin
if (W0_en)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 204'bx;
endmodule

27
generated-ooo/tags_64x416.sv Normal file
View File

@@ -0,0 +1,27 @@
// Generated by CIRCT firtool-1.139.0
// VCS coverage exclude_file
module tags_64x416(
input [5:0] R0_addr,
input R0_en,
R0_clk,
output [415:0] R0_data,
input [5:0] W0_addr,
input W0_en,
W0_clk,
input [415:0] W0_data
);
reg [415:0] Memory[0:63];
reg _R0_en_d0;
reg [5:0] _R0_addr_d0;
always @(posedge R0_clk) begin
_R0_en_d0 <= R0_en;
_R0_addr_d0 <= R0_addr;
end // always @(posedge)
always @(posedge W0_clk) begin
if (W0_en)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 416'bx;
endmodule

38
generated-ooo/verification/OoOBackend_Verification.sv Normal file
View File

@@ -0,0 +1,38 @@
// Generated by CIRCT firtool-1.139.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module OoOBackend_Verification();
`ifndef SYNTHESIS
always @(posedge OoOBackend.clock) begin
automatic logic [63:0] _GEN;
_GEN =
OoOBackend.memSlot
? OoOBackend.issue_io_out_1_decoded_pc
: OoOBackend.issue_io_out_0_decoded_pc;
if ((`PRINTF_COND_) & OoOBackend._storeEnq_T & _GEN < 64'h80000050
& ~OoOBackend.reset)
$fwrite(32'h80000002,
"[mem-issue] pc=0x%x inst=0x%x isLoad=%d isStore=%d prs1=%d src1=0x%x immS=0x%x addr=0x%x ready=%d\n",
_GEN,
OoOBackend.memSlot
? OoOBackend.issue_io_out_1_decoded_inst
: OoOBackend.issue_io_out_0_decoded_inst, OoOBackend._layer_probe_0,
OoOBackend._layer_probe_1,
OoOBackend.memSlot
? OoOBackend.issue_io_out_1_prs1
: OoOBackend.issue_io_out_0_prs1, OoOBackend.memSrc1,
OoOBackend._layer_probe, OoOBackend.memAddr,
OoOBackend.memSlot
? OoOBackend.issue_io_outReady_1
: OoOBackend.issue_io_outReady_0);
end // always @(posedge)
`endif // not def SYNTHESIS
endmodule

32
generated-ooo/verification/RenameStage_Verification.sv Normal file
View File

@@ -0,0 +1,32 @@
// Generated by CIRCT firtool-1.139.0
// Users can define 'PRINTF_COND' to add an extra gate to prints.
`ifndef PRINTF_COND_
`ifdef PRINTF_COND
`define PRINTF_COND_ (`PRINTF_COND)
`else // PRINTF_COND
`define PRINTF_COND_ 1
`endif // PRINTF_COND
`endif // not def PRINTF_COND_
module RenameStage_Verification();
`ifndef SYNTHESIS
always @(posedge RenameStage.clock) begin
if ((`PRINTF_COND_) & RenameStage.io_outValid_0_0
& RenameStage.io_in_0_pc < 64'h80000050 & ~RenameStage.reset)
$fwrite(32'h80000002,
"[rename] pc=0x%x inst=0x%x rs1=%d prs1=%d src1Ready=%d src1FromOlder=%d rd=%d prd=%d\n",
RenameStage.io_in_0_pc, RenameStage.io_in_0_inst, RenameStage.io_in_0_rs1,
RenameStage.table_io_prs1_0, RenameStage.io_out_0_src1Ready_0, 1'h0,
RenameStage.io_in_0_rd, RenameStage.io_out_0_prd_0);
if ((`PRINTF_COND_) & RenameStage.io_outValid_1_0
& RenameStage.io_in_1_pc < 64'h80000050 & ~RenameStage.reset)
$fwrite(32'h80000002,
"[rename] pc=0x%x inst=0x%x rs1=%d prs1=%d src1Ready=%d src1FromOlder=%d rd=%d prd=%d\n",
RenameStage.io_in_1_pc, RenameStage.io_in_1_inst, RenameStage.io_in_1_rs1,
RenameStage.table_io_prs1_1, RenameStage.io_out_1_src1Ready_0,
RenameStage.src1FromOlder, RenameStage.io_in_1_rd,
RenameStage.io_out_1_prd_0);
end // always @(posedge)
`endif // not def SYNTHESIS
endmodule

5
generated-ooo/verification/assert/layers-Core-Verification-Assert.sv Normal file
View File

@@ -0,0 +1,5 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_Core_Verification_Assert
`define layers_Core_Verification_Assert
`include "layers-Core-Verification.sv"
`endif // not def layers_Core_Verification_Assert

5
generated-ooo/verification/assume/layers-Core-Verification-Assume.sv Normal file
View File

@@ -0,0 +1,5 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_Core_Verification_Assume
`define layers_Core_Verification_Assume
`include "layers-Core-Verification.sv"
`endif // not def layers_Core_Verification_Assume

5
generated-ooo/verification/cover/layers-Core-Verification-Cover.sv Normal file
View File

@@ -0,0 +1,5 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_Core_Verification_Cover
`define layers_Core_Verification_Cover
`include "layers-Core-Verification.sv"
`endif // not def layers_Core_Verification_Cover

4
generated-ooo/verification/layers-Core-Verification.sv Normal file
View File

@@ -0,0 +1,4 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_Core_Verification
`define layers_Core_Verification
`endif // not def layers_Core_Verification

6
generated-ooo/verification/layers-OoOBackend-Verification.sv Normal file
View File

@@ -0,0 +1,6 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_OoOBackend_Verification
`define layers_OoOBackend_Verification
`include "layers-RenameStage-Verification.sv"
bind OoOBackend OoOBackend_Verification verification ();
`endif // not def layers_OoOBackend_Verification

5
generated-ooo/verification/layers-RenameStage-Verification.sv Normal file
View File

@@ -0,0 +1,5 @@
// Generated by CIRCT firtool-1.139.0
`ifndef layers_RenameStage_Verification
`define layers_RenameStage_Verification
bind RenameStage RenameStage_Verification verification ();
`endif // not def layers_RenameStage_Verification

47
sim/verilator/Makefile
View File

@@ -1,25 +1,56 @@
VERILATOR = verilator VERILATOR = verilator
VERILATOR_FLAGS = --cc --exe --build -Wall --trace -Wno-fatal JOBS ?= 8
TRACE ?= 0
FAST ?= 1
SPLIT ?= 20000
SPLIT_CFUNCS ?= 20000
VERILATE_JOBS ?= $(JOBS)
BUILD_JOBS ?= $(JOBS)
VERILATOR_FLAGS = --cc --exe --build --verilate-jobs $(VERILATE_JOBS) --build-jobs $(BUILD_JOBS) -Wall -Wno-fatal
VERILATOR_FLAGS += --output-split $(SPLIT) --output-split-cfuncs $(SPLIT_CFUNCS)
ifeq ($(TRACE),1)
VERILATOR_FLAGS += --trace
endif
ifeq ($(FAST),1)
VERILATOR_FLAGS += -CFLAGS "-std=c++14 -O0"
else
VERILATOR_FLAGS += -CFLAGS "-std=c++14 -O2" VERILATOR_FLAGS += -CFLAGS "-std=c++14 -O2"
endif
SBT = env SBT_OPTS="-Dsbt.boot.directory=/tmp/sbt-boot -Dsbt.ivy.home=/tmp/sbt-ivy" COURSIER_CACHE=/tmp/coursier-cache sbt SBT = env SBT_OPTS="-Dsbt.boot.directory=/tmp/sbt-boot -Dsbt.ivy.home=/tmp/sbt-ivy" COURSIER_CACHE=/tmp/coursier-cache sbt
CHISEL_DIR = ../.. CHISEL_DIR = ../..
OOO ?= 0
ifeq ($(OOO),1)
RUN_MAIN = CoreOoO
GENERATED_DIR = $(CHISEL_DIR)/generated-ooo
else
RUN_MAIN = Core
GENERATED_DIR = $(CHISEL_DIR)/generated GENERATED_DIR = $(CHISEL_DIR)/generated
endif
SRC_FILES = testbench.cpp memory.cpp SRC_FILES = testbench.cpp memory.cpp
VERILOG_FILES = $(GENERATED_DIR)/Core.sv VERILOG_FILES = $(GENERATED_DIR)/Core.sv
VERILOG_STAMP = $(GENERATED_DIR)/.Core.sv.stamp
SCALA_SOURCES = $(shell find $(CHISEL_DIR)/src/main/scala -name '*.scala')
TARGET = obj_dir/VCore TARGET = obj_dir/VCore
.PHONY: all verilog compile run clean .PHONY: all verilog compile run clean regenerate
all: compile all: compile
verilog: verilog: $(VERILOG_STAMP)
@echo "Generating Verilog from Chisel..."
cd $(CHISEL_DIR) && $(SBT) "runMain Core"
compile: verilog $(VERILOG_STAMP): $(SCALA_SOURCES) $(CHISEL_DIR)/build.sbt
@echo "Generating Verilog from Chisel..."
cd $(CHISEL_DIR) && $(SBT) "runMain $(RUN_MAIN)"
@touch $@
$(VERILOG_FILES): $(VERILOG_STAMP)
@test -f $@
compile: $(VERILOG_FILES)
@echo "Compiling with Verilator..." @echo "Compiling with Verilator..."
$(VERILATOR) $(VERILATOR_FLAGS) \ $(VERILATOR) $(VERILATOR_FLAGS) \
-I$(GENERATED_DIR) \ -I$(GENERATED_DIR) \
@@ -38,6 +69,10 @@ test-simple: compile
@echo "Running simple test..." @echo "Running simple test..."
./$(TARGET) ../../riscv-tests/isa/rv64ui-p-simple ./$(TARGET) ../../riscv-tests/isa/rv64ui-p-simple
regenerate:
rm -f $(VERILOG_STAMP)
$(MAKE) verilog OOO=$(OOO)
clean: clean:
rm -rf obj_dir rm -rf obj_dir
rm -rf $(GENERATED_DIR) rm -rf $(GENERATED_DIR)

176
sim/verilator/testbench.cpp
View File

@@ -1,10 +1,53 @@
#include <verilated.h> #include <verilated.h>
#include "VCore.h" #include "VCore.h"
#include "VCore___024root.h"
#include "memory.h" #include "memory.h"
#include <cstdio> #include <cstdio>
#include <cstdlib> #include <cstdlib>
#define MAX_CYCLES 100000 #define MAX_CYCLES 300000
static void dump_rob_entry(VCore* core, unsigned idx, const char* label) {
#define ROB_ENTRY_CASE(n) \
case n: \
fprintf(stderr, \
"%s[%u]: valid=%u completed=%u exception=%u mispredict=%u " \
"arch=%u writes=%u op=%u dest=%u old=%u cause=0x%lx bad=0x%lx redirect=0x%lx\n", \
label, idx, \
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__valid_##n, \
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__completed_##n, \
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__exception_##n, \
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__branchMispredict_##n, \
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__entries_##n##_archDest, \
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__entries_##n##_writesDest, \
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__entries_##n##_opClass, \
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__entries_##n##_dest, \
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__entries_##n##_oldDest, \
(uint64_t)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__exceptionCause_##n, \
(uint64_t)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__badAddr_##n, \
(uint64_t)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__redirectPc_##n); \
break
switch (idx & 63U) {
ROB_ENTRY_CASE(0); ROB_ENTRY_CASE(1); ROB_ENTRY_CASE(2); ROB_ENTRY_CASE(3);
ROB_ENTRY_CASE(4); ROB_ENTRY_CASE(5); ROB_ENTRY_CASE(6); ROB_ENTRY_CASE(7);
ROB_ENTRY_CASE(8); ROB_ENTRY_CASE(9); ROB_ENTRY_CASE(10); ROB_ENTRY_CASE(11);
ROB_ENTRY_CASE(12); ROB_ENTRY_CASE(13); ROB_ENTRY_CASE(14); ROB_ENTRY_CASE(15);
ROB_ENTRY_CASE(16); ROB_ENTRY_CASE(17); ROB_ENTRY_CASE(18); ROB_ENTRY_CASE(19);
ROB_ENTRY_CASE(20); ROB_ENTRY_CASE(21); ROB_ENTRY_CASE(22); ROB_ENTRY_CASE(23);
ROB_ENTRY_CASE(24); ROB_ENTRY_CASE(25); ROB_ENTRY_CASE(26); ROB_ENTRY_CASE(27);
ROB_ENTRY_CASE(28); ROB_ENTRY_CASE(29); ROB_ENTRY_CASE(30); ROB_ENTRY_CASE(31);
ROB_ENTRY_CASE(32); ROB_ENTRY_CASE(33); ROB_ENTRY_CASE(34); ROB_ENTRY_CASE(35);
ROB_ENTRY_CASE(36); ROB_ENTRY_CASE(37); ROB_ENTRY_CASE(38); ROB_ENTRY_CASE(39);
ROB_ENTRY_CASE(40); ROB_ENTRY_CASE(41); ROB_ENTRY_CASE(42); ROB_ENTRY_CASE(43);
ROB_ENTRY_CASE(44); ROB_ENTRY_CASE(45); ROB_ENTRY_CASE(46); ROB_ENTRY_CASE(47);
ROB_ENTRY_CASE(48); ROB_ENTRY_CASE(49); ROB_ENTRY_CASE(50); ROB_ENTRY_CASE(51);
ROB_ENTRY_CASE(52); ROB_ENTRY_CASE(53); ROB_ENTRY_CASE(54); ROB_ENTRY_CASE(55);
ROB_ENTRY_CASE(56); ROB_ENTRY_CASE(57); ROB_ENTRY_CASE(58); ROB_ENTRY_CASE(59);
ROB_ENTRY_CASE(60); ROB_ENTRY_CASE(61); ROB_ENTRY_CASE(62); ROB_ENTRY_CASE(63);
}
#undef ROB_ENTRY_CASE
}
int main(int argc, char** argv) { int main(int argc, char** argv) {
if (argc < 2) { if (argc < 2) {
@@ -35,11 +78,20 @@ int main(int argc, char** argv) {
uint64_t cycle = 0; uint64_t cycle = 0;
bool test_done = false; bool test_done = false;
int exit_code = 0; int exit_code = 0;
int bad_access_reports = 0;
bool saw_tohost_req = false;
int flush_reports = 0;
int csr_reports = 0;
int store_reports = 0;
while (cycle < MAX_CYCLES && !test_done) { while (cycle < MAX_CYCLES && !test_done) {
// Handle instruction memory interface // Handle instruction memory interface
if (core->io_imem_req_valid) { if (core->io_imem_req_valid) {
uint64_t pc = core->io_imem_req_bits; uint64_t pc = core->io_imem_req_bits;
if ((pc < MEM_BASE || pc >= MEM_BASE + MEM_SIZE) && bad_access_reports < 32) {
fprintf(stderr, "[%lu] Bad imem fetch pc=0x%lx\n", cycle, pc);
bad_access_reports++;
}
core->io_imem_resp_valid = 1; core->io_imem_resp_valid = 1;
core->io_imem_resp_bits_0 = mem->read32(pc); core->io_imem_resp_bits_0 = mem->read32(pc);
core->io_imem_resp_bits_1 = mem->read32(pc + 4); core->io_imem_resp_bits_1 = mem->read32(pc + 4);
@@ -50,9 +102,20 @@ int main(int argc, char** argv) {
// Handle data memory interface // Handle data memory interface
if (core->io_dmem_req_valid) { if (core->io_dmem_req_valid) {
uint64_t addr = core->io_dmem_req_bits_addr; uint64_t addr = core->io_dmem_req_bits_addr;
if ((addr < MEM_BASE || addr >= MEM_BASE + MEM_SIZE) && addr != TOHOST_ADDR && bad_access_reports < 32) {
fprintf(stderr,
"[%lu] Bad dmem %s addr=0x%lx data=0x%lx size=%u\n",
cycle,
core->io_dmem_req_bits_isStore ? "store" : "load",
addr,
(uint64_t)core->io_dmem_req_bits_data,
(unsigned)core->io_dmem_req_bits_size);
bad_access_reports++;
}
// Check for tohost write // Check for tohost write
if (core->io_dmem_req_bits_isStore && addr == TOHOST_ADDR) { if (core->io_dmem_req_bits_isStore && addr == TOHOST_ADDR) {
saw_tohost_req = true;
uint64_t tohost = core->io_dmem_req_bits_data; uint64_t tohost = core->io_dmem_req_bits_data;
if (tohost == 1) { if (tohost == 1) {
printf("[%lu] TEST PASSED\n", cycle); printf("[%lu] TEST PASSED\n", cycle);
@@ -66,6 +129,15 @@ int main(int argc, char** argv) {
} }
if (core->io_dmem_req_bits_isStore) { if (core->io_dmem_req_bits_isStore) {
if (store_reports < 64) {
fprintf(stderr,
"[%lu] STORE addr=0x%lx data=0x%lx size=%u\n",
cycle,
addr,
(uint64_t)core->io_dmem_req_bits_data,
(unsigned)core->io_dmem_req_bits_size);
store_reports++;
}
switch (core->io_dmem_req_bits_size) { switch (core->io_dmem_req_bits_size) {
case 0: mem->write8(addr, core->io_dmem_req_bits_data & 0xff); break; case 0: mem->write8(addr, core->io_dmem_req_bits_data & 0xff); break;
case 1: mem->write16(addr, core->io_dmem_req_bits_data & 0xffff); break; case 1: mem->write16(addr, core->io_dmem_req_bits_data & 0xffff); break;
@@ -88,10 +160,112 @@ int main(int argc, char** argv) {
core->eval(); core->eval();
cycle++; cycle++;
if ((core->rootp->Core__DOT__backend__DOT__commitCsr0 ||
(core->rootp->Core__DOT__backend__DOT___commit_io_commitReady_1 &&
core->rootp->Core__DOT__backend__DOT___rename_io_commitEntry_1_csrValid)) &&
csr_reports < 64) {
fprintf(stderr,
"[%lu] CSR commit slot0=%u slot1=%u addr=0x%x cmd=%u next=0x%lx mtvec=0x%lx\n",
cycle,
(unsigned)core->rootp->Core__DOT__backend__DOT__commitCsr0,
(unsigned)(core->rootp->Core__DOT__backend__DOT___commit_io_commitReady_1 &&
core->rootp->Core__DOT__backend__DOT___rename_io_commitEntry_1_csrValid),
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__csr__io_cmd_addr,
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__csr__io_cmd_cmd,
(uint64_t)core->rootp->Core__DOT__backend__DOT__csr__DOT__unnamedblk1__DOT__next,
(uint64_t)core->rootp->Core__DOT__backend__DOT__csr__DOT__mtvecReg);
csr_reports++;
}
if (core->rootp->Core__DOT___backend_io_flush && flush_reports < 64) {
fprintf(stderr,
"[%lu] FLUSH exception=%u mtvec=0x%lx mepc=0x%lx mcause=0x%lx frontend_pc=0x%lx\n",
cycle,
(unsigned)core->rootp->Core__DOT__backend__DOT___commit_io_exception,
(uint64_t)core->rootp->Core__DOT__backend__DOT__csr__DOT__mtvecReg,
(uint64_t)core->rootp->Core__DOT__backend__DOT__csr__DOT__mepcReg,
(uint64_t)core->rootp->Core__DOT__backend__DOT__csr__DOT__mcause,
(uint64_t)core->rootp->Core__DOT__frontend__DOT__pc);
flush_reports++;
}
} }
if (!test_done) { if (!test_done) {
printf("[%lu] TEST TIMEOUT\n", cycle); printf("[%lu] TEST TIMEOUT\n", cycle);
fprintf(stderr,
"Timeout state: frontend_pc=0x%lx ic_state=%u ic_lookup=0x%lx ic_miss=0x%lx "
"fetchValid=%u fetchReady=%u feOut=%u issueInReady0=%u robCount=%u "
"rsFree=0x%x freeMask=0x%lx "
"issueReady=%u/%u issue0_pc=0x%lx issue1_pc=0x%lx "
"robHead=%u robTail=%u mtvec=0x%lx mepc=0x%lx mcause=0x%lx "
"flush=%u commitReady=%u/%u commitValid1=%u sawTohost=%u\n",
core->rootp->Core__DOT__frontend__DOT__pc,
(unsigned)core->rootp->Core__DOT__frontend__DOT__icache__DOT__state,
core->rootp->Core__DOT__frontend__DOT__icache__DOT__lookupAddr,
core->rootp->Core__DOT__frontend__DOT__icache__DOT__missAddr,
(unsigned)core->rootp->Core__DOT__fetchValid,
(unsigned)core->rootp->Core__DOT__fetchReady,
(unsigned)core->rootp->Core__DOT___frontend_io_outValid,
(unsigned)core->rootp->Core__DOT__backend__DOT___issue_io_inReady_0,
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__count,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__freeMask,
(uint64_t)core->rootp->Core__DOT__backend__DOT__rename__DOT__freeList__DOT__freeMask,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue_io_outReady_0,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue_io_outReady_1,
core->rootp->Core__DOT__backend__DOT___issue_io_out_0_decoded_pc,
core->rootp->Core__DOT__backend__DOT___issue_io_out_1_decoded_pc,
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__head,
(unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__tail,
core->rootp->Core__DOT__backend__DOT__csr__DOT__mtvecReg,
core->rootp->Core__DOT__backend__DOT__csr__DOT__mepcReg,
core->rootp->Core__DOT__backend__DOT__csr__DOT__mcause,
(unsigned)core->rootp->Core__DOT___backend_io_flush,
(unsigned)core->rootp->Core__DOT__backend__DOT___commit_io_commitReady_0,
(unsigned)core->rootp->Core__DOT__backend__DOT___commit_io_commitReady_1,
(unsigned)core->rootp->Core__DOT__backend__DOT___rename_io_commitValid_1,
saw_tohost_req ? 1u : 0u);
unsigned head = (unsigned)core->rootp->Core__DOT__backend__DOT__rename__DOT__rob__DOT__head;
dump_rob_entry(core, head, "robHead");
dump_rob_entry(core, head + 1U, "robNext");
fprintf(stderr,
"rs0: valid=%u ready=%u pc=0x%lx inst=0x%08x rob=%u prs=%u/%u readySrc=%u/%u prd=%u\n",
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__valid_0,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__readyVec_0,
(uint64_t)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_0_decoded_pc,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_0_decoded_inst,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_0_robIdx,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_0_prs1,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_0_prs2,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_0_src1Ready,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_0_src2Ready,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_0_prd);
fprintf(stderr,
"rs1: valid=%u ready=%u pc=0x%lx inst=0x%08x rob=%u prs=%u/%u readySrc=%u/%u prd=%u issueOH=0x%x/0x%x\n",
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__valid_1,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__readyVec_1,
(uint64_t)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_1_decoded_pc,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_1_decoded_inst,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_1_robIdx,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_1_prs1,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_1_prs2,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_1_src1Ready,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_1_src2Ready,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__slots_1_prd,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__issue0OH,
(unsigned)core->rootp->Core__DOT__backend__DOT__issue__DOT__queue__DOT__intRs__DOT__issue1OH);
fprintf(stderr,
"complete: valid=%u/%u idx0=%u exc=%u/%u mis=%u/%u cause=0x%lx/0x%lx redirect=0x%lx/0x%lx\n",
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeValid_0,
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeValid_1,
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeIdx_0,
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeException_0,
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeException_1,
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeMispredict_0,
(unsigned)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeMispredict_1,
(uint64_t)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeCause_0,
(uint64_t)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeCause_1,
(uint64_t)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeRedirectPc_0,
(uint64_t)core->rootp->Core__DOT__backend__DOT____Vcellinp__rename__io_completeRedirectPc_1);
exit_code = 2; exit_code = 2;
} }

51
src/main/scala/Core.scala
View File

@@ -19,6 +19,47 @@ class Core(p: CoreParams = CoreParams()) extends Module {
val dmem_resp_bits = Input(UInt(p.xlen.W)) val dmem_resp_bits = Input(UInt(p.xlen.W))
}) })
if (p.useOoOBackend) {
val frontend = Module(new Frontend(p))
val id = Module(new IDStage(p))
val backend = Module(new OoOBackend(p))
frontend.io.redirectValid := backend.io.flush
frontend.io.redirectPc := backend.io.redirectPc
frontend.io.imemRespValid := io.imem_resp_valid
frontend.io.imemRespBits(0) := io.imem_resp_bits_0
frontend.io.imemRespBits(1) := io.imem_resp_bits_1
frontend.io.branchUpdate := 0.U.asTypeOf(new BranchUpdate(p))
val fetchValid = RegInit(false.B)
val fetchReg = Reg(new FetchPacket(p))
val fetchReady = !fetchValid || backend.io.decodeReady
frontend.io.outReady := fetchReady
when(backend.io.flush) {
fetchValid := false.B
}.elsewhen(fetchReady) {
fetchValid := frontend.io.outValid
fetchReg := frontend.io.out
}
id.io.inValid := fetchValid
id.io.in := fetchReg
backend.io.decodeValid := id.io.outValid
backend.io.decode := id.io.out
backend.io.dmemRespValid := io.dmem_resp_valid
backend.io.dmemRespData := io.dmem_resp_bits
backend.io.satp := 0.U
io.imem_req_valid := frontend.io.imemReqValid
io.imem_req_bits := frontend.io.imemReqAddr
io.dmem_req_valid := backend.io.dmemReqValid
io.dmem_req_bits_addr := backend.io.dmemReq.addr
io.dmem_req_bits_data := backend.io.dmemReq.data
io.dmem_req_bits_isStore := backend.io.dmemReq.isStore
io.dmem_req_bits_size := backend.io.dmemReq.size
} else {
val sFetch :: sExec :: sLoadWait :: Nil = Enum(3) val sFetch :: sExec :: sLoadWait :: Nil = Enum(3)
val state = RegInit(sFetch) val state = RegInit(sFetch)
val pc = RegInit(Consts.ResetVector) val pc = RegInit(Consts.ResetVector)
@@ -67,6 +108,7 @@ class Core(p: CoreParams = CoreParams()) extends Module {
csr.io.cmd.cmd := dec.funct3 csr.io.cmd.cmd := dec.funct3
csr.io.cmd.rs1 := src1 csr.io.cmd.rs1 := src1
csr.io.cmd.zimm := dec.rs1 csr.io.cmd.zimm := dec.rs1
csr.io.readAddr := instReg(31, 20)
val isEcall = instReg === "h00000073".U val isEcall = instReg === "h00000073".U
val isEbreak = instReg === "h00100073".U val isEbreak = instReg === "h00100073".U
val isMret = instReg === "h30200073".U val isMret = instReg === "h30200073".U
@@ -163,6 +205,7 @@ class Core(p: CoreParams = CoreParams()) extends Module {
} }
} }
}
object Core extends App { object Core extends App {
ChiselStage.emitSystemVerilogFile( ChiselStage.emitSystemVerilogFile(
@@ -171,3 +214,11 @@ object Core extends App {
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info") firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
) )
} }
object CoreOoO extends App {
ChiselStage.emitSystemVerilogFile(
new Core(CoreParams(useOoOBackend = true)),
args = Array("--target-dir", "generated-ooo"),
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
)
}

282
src/main/scala/OoOBackend.scala Normal file
View File

@@ -0,0 +1,282 @@
import chisel3._
import chisel3.util._
import _root_.circt.stage.ChiselStage
class OoOBackend(p: CoreParams = CoreParams()) extends Module {
private val physBits = log2Ceil(p.physRegs)
private val robBits = log2Ceil(p.robEntries)
val io = IO(new Bundle {
val decodeValid = Input(Vec(p.issueWidth, Bool()))
val decode = Input(Vec(p.issueWidth, new DecodedInst(p)))
val decodeReady = Output(Bool())
val commitValid = Output(Vec(p.issueWidth, Bool()))
val commitEntry = Output(Vec(p.issueWidth, new RobEntry(p)))
val flush = Output(Bool())
val redirectPc = Output(UInt(p.xlen.W))
val dmemReqValid = Output(Bool())
val dmemReq = Output(new MemRequest(p))
val dmemRespValid = Input(Bool())
val dmemRespData = Input(UInt(p.xlen.W))
val satp = Input(UInt(p.xlen.W))
})
val rename = Module(new RenameStage(p))
val issue = Module(new IssueStage(p))
val prf = Module(new PhysicalRegFile(p))
val exec = Seq.fill(p.issueWidth)(Module(new ExecStage(p)))
val wb = Seq.fill(p.issueWidth)(Module(new WriteBackStage(p)))
val commit = Module(new CommitStage(p))
val lq = Module(new LoadQueue(p))
val sq = Module(new StoreQueue(p))
val lsu = Module(new LSU(p))
val csr = Module(new CSRFile(p))
val completeValid = Wire(Vec(p.issueWidth, Bool()))
val completeIdx = Wire(Vec(p.issueWidth, UInt(robBits.W)))
val completeException = Wire(Vec(p.issueWidth, Bool()))
val completeCause = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
val completeBadAddr = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
val completeMispredict = Wire(Vec(p.issueWidth, Bool()))
val completeRedirectPc = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
val completeCsrValid = Wire(Vec(p.issueWidth, Bool()))
val completeCsrAddr = Wire(Vec(p.issueWidth, UInt(12.W)))
val completeCsrCmd = Wire(Vec(p.issueWidth, UInt(3.W)))
val completeCsrRs1 = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
val completeCsrZimm = Wire(Vec(p.issueWidth, UInt(5.W)))
val wakeup = Wire(Vec(p.issueWidth, new Wakeup(p)))
val wakeupReg = RegInit(VecInit(Seq.fill(p.issueWidth)(0.U.asTypeOf(new Wakeup(p)))))
val csrRData = Wire(Vec(p.issueWidth, UInt(p.xlen.W)))
rename.io.inValid := VecInit((0 until p.issueWidth).map(i => io.decodeValid(i) && issue.io.inReady(i)))
rename.io.in := io.decode
rename.io.wbValid := VecInit(wb.map(_.io.wen))
rename.io.wbPhys := VecInit(wb.map(_.io.waddr))
rename.io.completeValid := completeValid
rename.io.completeIdx := completeIdx
rename.io.completeException := completeException
rename.io.completeCause := completeCause
rename.io.completeBadAddr := completeBadAddr
rename.io.completeMispredict := completeMispredict
rename.io.completeRedirectPc := completeRedirectPc
rename.io.completeCsrValid := completeCsrValid
rename.io.completeCsrAddr := completeCsrAddr
rename.io.completeCsrCmd := completeCsrCmd
rename.io.completeCsrRs1 := completeCsrRs1
rename.io.completeCsrZimm := completeCsrZimm
rename.io.commitReady := commit.io.commitReady
rename.io.commitMapValid := commit.io.commitMapValid
rename.io.commitArch := commit.io.commitArch
rename.io.commitPhys := commit.io.commitPhys
rename.io.commitFreeOld := commit.io.freeOldPhys
rename.io.commitOldPhys := commit.io.oldPhys
rename.io.flush := commit.io.flush
issue.io.inValid := rename.io.outValid
issue.io.in := rename.io.out
issue.io.wakeup := wakeupReg
val loadPending = RegInit(false.B)
val loadPendingRob = Reg(UInt(robBits.W))
val loadPendingPhys = Reg(UInt(physBits.W))
val loadPendingLq = Reg(UInt(log2Ceil(p.loadQueueEntries).W))
val loadRespValid = lsu.io.respValid && loadPending
val memIssue = Wire(Vec(p.issueWidth, Bool()))
for (i <- 0 until p.issueWidth) {
memIssue(i) := issue.io.outValid(i) && (issue.io.out(i).decoded.isLoad || issue.io.out(i).decoded.isStore)
}
val csrReadReq = Wire(Vec(p.issueWidth, Bool()))
for (i <- 0 until p.issueWidth) {
val decoded = issue.io.out(i).decoded
csrReadReq(i) := issue.io.outValid(i) && decoded.isSystem && decoded.funct3 =/= 0.U
}
val stallSecondCsrRead = csrReadReq(0) && csrReadReq(1)
val memSlot0 = memIssue(0)
val memSlot1 = !memSlot0 && memIssue(1)
val memSlot = Mux(memSlot0, 0.U, 1.U)
val canIssueMem = !loadPending
val issue_io_outReady_0 = Wire(Bool())
val issue_io_outReady_1 = Wire(Bool())
dontTouch(issue_io_outReady_0)
dontTouch(issue_io_outReady_1)
val isMem0 = issue.io.out(0).decoded.isLoad || issue.io.out(0).decoded.isStore
val isMem1 = issue.io.out(1).decoded.isLoad || issue.io.out(1).decoded.isStore
val memReady0 = !isMem0 || (lsu.io.reqReady && canIssueMem)
val memReady1 = !isMem1 || (lsu.io.reqReady && canIssueMem && !memSlot0)
issue_io_outReady_0 := memReady0
issue_io_outReady_1 := memReady1 && !stallSecondCsrRead
issue.io.outReady := VecInit(Seq(issue_io_outReady_0, issue_io_outReady_1))
val issueFire = Wire(Vec(p.issueWidth, Bool()))
for (i <- 0 until p.issueWidth) {
issueFire(i) := issue.io.outValid(i) && issue.io.outReady(i)
}
issue.io.flush := commit.io.flush
io.decodeReady := rename.io.canAccept && issue.io.inReady.asUInt.andR
val memDecoded = issue.io.out(memSlot).decoded
val memSrc1 = Mux(memSlot0, prf.io.rdata(0), prf.io.rdata(2))
val memSrc2 = Mux(memSlot0, prf.io.rdata(1), prf.io.rdata(3))
val memAddr = memSrc1 + Mux(memDecoded.isStore, memDecoded.immS, memDecoded.immI)
val loadEnq = (memSlot0 || memSlot1) && memDecoded.isLoad && issue.io.outReady(memSlot)
val storeEnq = (memSlot0 || memSlot1) && memDecoded.isStore && issue.io.outReady(memSlot)
val lsuLoadReq = loadEnq && !sq.io.forwardValid
lq.io.enqValid := loadEnq
lq.io.enqRobIdx := issue.io.out(memSlot).robIdx
lq.io.addrValid := loadEnq
lq.io.addrIdx := lq.io.enqIdx
lq.io.addr := memAddr
lq.io.size := memDecoded.memWidth
lq.io.complete := loadRespValid
lq.io.completeIdx := loadPendingLq
lq.io.storeAddrValid := storeEnq
lq.io.storeRobIdx := issue.io.out(memSlot).robIdx
lq.io.storeAddr := memAddr
lq.io.storeSize := memDecoded.memWidth
lq.io.flush := commit.io.flush
sq.io.enqValid := storeEnq
sq.io.enqRobIdx := issue.io.out(memSlot).robIdx
sq.io.writeAddr := storeEnq
sq.io.writeData := storeEnq
sq.io.writeIdx := sq.io.enqIdx
sq.io.addr := memAddr
sq.io.data := memSrc2
sq.io.size := memDecoded.memWidth
sq.io.loadAddr := memAddr
sq.io.loadSize := memDecoded.memWidth
sq.io.loadRobIdx := issue.io.out(memSlot).robIdx
val commitStore0 = commit.io.commitReady(0) && rename.io.commitValid(0) &&
rename.io.commitEntry(0).opClass === Consts.OP_STORE
val commitStore1 = commit.io.commitReady(1) && rename.io.commitValid(1) &&
rename.io.commitEntry(1).opClass === Consts.OP_STORE
sq.io.commitValid := commitStore0 || commitStore1
sq.io.commitRobIdx := Mux(commitStore0, rename.io.commitEntry(0).robIdx, rename.io.commitEntry(1).robIdx)
sq.io.drainReady := !lsuLoadReq && lsu.io.reqReady
sq.io.flush := commit.io.flush
lsu.io.reqValid := lsuLoadReq || sq.io.drainValid
lsu.io.req := Mux(sq.io.drainValid, sq.io.drain, 0.U.asTypeOf(new MemRequest(p)))
when(lsuLoadReq) {
lsu.io.req.addr := memAddr
lsu.io.req.data := 0.U
lsu.io.req.isStore := false.B
lsu.io.req.size := memDecoded.memWidth
}
lsu.io.dmemRespValid := io.dmemRespValid
lsu.io.dmemRespData := io.dmemRespData
lsu.io.satp := csr.io.satp
io.dmemReqValid := lsu.io.dmemReqValid
io.dmemReq := lsu.io.dmemReq
val csrReadFire = VecInit((0 until p.issueWidth).map(i => csrReadReq(i) && issue.io.outReady(i)))
csr.io.readAddr := Mux(csrReadFire(0), issue.io.out(0).decoded.inst(31, 20), issue.io.out(1).decoded.inst(31, 20))
csrRData(0) := csr.io.rdata
csrRData(1) := csr.io.rdata
csr.io.trap := commit.io.flush && commit.io.exception
csr.io.trapPc := commit.io.badAddr
csr.io.trapCause := commit.io.exceptionCause
val commitCsr0 = commit.io.commitReady(0) && rename.io.commitValid(0) && rename.io.commitEntry(0).csrValid
val commitCsr1 = commit.io.commitReady(1) && rename.io.commitValid(1) && rename.io.commitEntry(1).csrValid
val commitCsrEntry = Mux(commitCsr0, rename.io.commitEntry(0), rename.io.commitEntry(1))
csr.io.cmd.valid := commitCsr0 || commitCsr1
csr.io.cmd.addr := commitCsrEntry.csrAddr
csr.io.cmd.cmd := commitCsrEntry.csrCmd
csr.io.cmd.rs1 := commitCsrEntry.csrRs1
csr.io.cmd.zimm := commitCsrEntry.csrZimm
when(commit.io.flush) {
loadPending := false.B
}.elsewhen(loadEnq && !sq.io.forwardValid) {
loadPending := true.B
loadPendingRob := issue.io.out(memSlot).robIdx
loadPendingPhys := issue.io.out(memSlot).prd
loadPendingLq := lq.io.enqIdx
}.elsewhen(loadRespValid) {
loadPending := false.B
}
for (i <- 0 until p.issueWidth) {
prf.io.raddr(2 * i) := issue.io.out(i).prs1
prf.io.raddr(2 * i + 1) := issue.io.out(i).prs2
}
for (i <- 0 until p.issueWidth) {
val decoded = issue.io.out(i).decoded
val src1 = prf.io.rdata(2 * i)
val rs2Val = prf.io.rdata(2 * i + 1)
val src2 = Mux(decoded.isOpImm || decoded.isLoad || decoded.isJalr, decoded.immI, rs2Val)
exec(i).io.inValid := issueFire(i)
exec(i).io.in := decoded
exec(i).io.src1 := src1
exec(i).io.src2 := src2
val isLoadRespSlot = i.U === 0.U && loadRespValid
val useExecWb = exec(i).io.outValid && decoded.writesRd && !decoded.isLoad
wb(i).io.valid := useExecWb || isLoadRespSlot
wb(i).io.physDest := Mux(isLoadRespSlot, loadPendingPhys, issue.io.out(i).prd)
wb(i).io.data := Mux(isLoadRespSlot, lsu.io.respData, Mux(decoded.isLui, decoded.immU,
Mux(decoded.isAuipc, decoded.pc + decoded.immU,
Mux(decoded.isJal || decoded.isJalr, decoded.pc + 4.U,
Mux(decoded.isSystem && decoded.funct3 =/= 0.U, csrRData(i), exec(i).io.result)))))
prf.io.wen(i) := wb(i).io.wen
prf.io.waddr(i) := wb(i).io.waddr
prf.io.wdata(i) := wb(i).io.wdata
wakeup(i).valid := wb(i).io.wen
wakeup(i).phys := wb(i).io.waddr
wakeup(i).data := wb(i).io.wdata
val branchTarget = decoded.pc + decoded.immB
val jalTarget = decoded.pc + decoded.immJ
val jalrTarget = (src1 + decoded.immI) & (~1.U(p.xlen.W))
val branchRedirect = Mux(decoded.isJal, jalTarget,
Mux(decoded.isJalr, jalrTarget,
Mux(decoded.isBranch && exec(i).io.branchTaken, branchTarget, decoded.pc + 4.U)))
val isEcall = decoded.inst === "h00000073".U
val isEbreak = decoded.inst === "h00100073".U
val isMret = decoded.inst === "h30200073".U
val completeLoadResp = i.U === 0.U && loadRespValid
completeValid(i) := (issueFire(i) && !decoded.isLoad) || completeLoadResp
completeIdx(i) := Mux(completeLoadResp, loadPendingRob, issue.io.out(i).robIdx)
completeException(i) := (issueFire(i) && (decoded.illegal || isEcall || isEbreak || lq.io.violation)) ||
(completeLoadResp && lsu.io.pageFault)
completeCause(i) := Mux(completeLoadResp && lsu.io.pageFault, 13.U,
Mux(issueFire(i) && isEbreak, 3.U,
Mux(issueFire(i) && isEcall, 11.U,
Mux(issueFire(i) && decoded.illegal, 2.U, 0.U))))
completeBadAddr(i) := decoded.pc
completeMispredict(i) := issueFire(i) &&
(decoded.isJal || decoded.isJalr || isMret || (decoded.isBranch && exec(i).io.branchTaken))
completeRedirectPc(i) := Mux(isEcall || isEbreak, csr.io.mtvec, Mux(isMret, csr.io.mepc, branchRedirect))
completeCsrValid(i) := issueFire(i) && decoded.isSystem && decoded.funct3 =/= 0.U &&
!(decoded.funct3(1) && decoded.rs1 === 0.U)
completeCsrAddr(i) := decoded.inst(31, 20)
completeCsrCmd(i) := decoded.funct3
completeCsrRs1(i) := src1
completeCsrZimm(i) := decoded.rs1
}
wakeupReg := wakeup
commit.io.robValid := rename.io.commitValid
commit.io.robEntry := rename.io.commitEntry
io.commitValid := VecInit((0 until p.issueWidth).map(i => rename.io.commitValid(i) && commit.io.commitReady(i)))
io.commitEntry := rename.io.commitEntry
io.flush := commit.io.flush
io.redirectPc := Mux(commit.io.exception, csr.io.mtvec, commit.io.redirectPc)
}
object OoOBackend extends App {
ChiselStage.emitSystemVerilogFile(
new OoOBackend(),
args = Array("--target-dir", "generated"),
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
)
}

52
src/main/scala/commit/CommitStage.scala
View File

@@ -2,17 +2,51 @@ import chisel3._
import chisel3.util._ import chisel3.util._
class CommitStage(p: CoreParams = CoreParams()) extends Module { class CommitStage(p: CoreParams = CoreParams()) extends Module {
private val physBits = log2Ceil(p.physRegs)
val io = IO(new Bundle { val io = IO(new Bundle {
val robValid = Input(Bool()) val robValid = Input(Vec(p.issueWidth, Bool()))
val robEntry = Input(new RobEntry(p)) val robEntry = Input(Vec(p.issueWidth, new RobEntry(p)))
val commitReady = Output(Bool()) val commitReady = Output(Vec(p.issueWidth, Bool()))
val freeOldPhys = Output(Bool()) val freeOldPhys = Output(Vec(p.issueWidth, Bool()))
val oldPhys = Output(UInt(log2Ceil(p.physRegs).W)) val oldPhys = Output(Vec(p.issueWidth, UInt(physBits.W)))
val commitMapValid = Output(Vec(p.issueWidth, Bool()))
val commitArch = Output(Vec(p.issueWidth, UInt(5.W)))
val commitPhys = Output(Vec(p.issueWidth, UInt(physBits.W)))
val flush = Output(Bool()) val flush = Output(Bool())
val redirectPc = Output(UInt(p.xlen.W))
val exception = Output(Bool())
val exceptionCause = Output(UInt(p.xlen.W))
val badAddr = Output(UInt(p.xlen.W))
}) })
io.commitReady := io.robValid val firstTrap = io.robValid(0) && (io.robEntry(0).exception || io.robEntry(0).branchMispredict)
io.freeOldPhys := io.robValid && io.robEntry.oldDest =/= io.robEntry.dest val secondTrap = io.robValid(1) && (io.robEntry(1).exception || io.robEntry(1).branchMispredict)
io.oldPhys := io.robEntry.oldDest val twoCsrWrites = io.robValid(0) && io.robValid(1) &&
io.flush := io.robValid && (io.robEntry.exception || io.robEntry.branchMispredict) io.robEntry(0).csrValid && io.robEntry(1).csrValid
val firstStore = io.robValid(0) && io.robEntry(0).opClass === Consts.OP_STORE
io.commitReady(0) := io.robValid(0)
io.commitReady(1) := io.robValid(1) && !firstTrap && !secondTrap && !twoCsrWrites && !firstStore
for (i <- 0 until p.issueWidth) {
val doCommit = io.commitReady(i)
io.freeOldPhys(i) := doCommit && io.robEntry(i).writesDest &&
io.robEntry(i).oldDest =/= io.robEntry(i).dest
io.oldPhys(i) := io.robEntry(i).oldDest
io.commitMapValid(i) := doCommit && io.robEntry(i).writesDest &&
io.robEntry(i).archDest =/= 0.U
io.commitArch(i) := io.robEntry(i).archDest
io.commitPhys(i) := io.robEntry(i).dest
}
val secondTrapSelected = !io.robValid(0) && secondTrap
val selectedTrap = firstTrap || secondTrapSelected
io.flush := selectedTrap
io.redirectPc := Mux(firstTrap, io.robEntry(0).redirectPc, io.robEntry(1).redirectPc)
io.exception := Mux(firstTrap, io.robEntry(0).exception,
Mux(secondTrapSelected, io.robEntry(1).exception, false.B))
io.exceptionCause := Mux(firstTrap, io.robEntry(0).exceptionCause,
Mux(secondTrapSelected, io.robEntry(1).exceptionCause, 0.U))
io.badAddr := Mux(firstTrap, io.robEntry(0).badAddr,
Mux(secondTrapSelected, io.robEntry(1).badAddr, 0.U))
} }

63
src/main/scala/common/Bundles.scala
View File

@@ -4,6 +4,7 @@ import chisel3.util._
class FetchPacket(p: CoreParams = CoreParams()) extends Bundle { class FetchPacket(p: CoreParams = CoreParams()) extends Bundle {
val pc = UInt(p.xlen.W) val pc = UInt(p.xlen.W)
val inst = Vec(p.fetchWidth, UInt(32.W)) val inst = Vec(p.fetchWidth, UInt(32.W))
val laneValid = Vec(p.fetchWidth, Bool())
val predictedTaken = Bool() val predictedTaken = Bool()
val predictedTarget = UInt(p.xlen.W) val predictedTarget = UInt(p.xlen.W)
} }
@@ -55,11 +56,19 @@ class RenamePacket(p: CoreParams = CoreParams()) extends Bundle {
val decoded = new DecodedInst(p) val decoded = new DecodedInst(p)
val prs1 = UInt(log2Ceil(p.physRegs).W) val prs1 = UInt(log2Ceil(p.physRegs).W)
val prs2 = UInt(log2Ceil(p.physRegs).W) val prs2 = UInt(log2Ceil(p.physRegs).W)
val src1Ready = Bool()
val src2Ready = Bool()
val prd = UInt(log2Ceil(p.physRegs).W) val prd = UInt(log2Ceil(p.physRegs).W)
val oldPrd = UInt(log2Ceil(p.physRegs).W) val oldPrd = UInt(log2Ceil(p.physRegs).W)
val robIdx = UInt(log2Ceil(p.robEntries).W) val robIdx = UInt(log2Ceil(p.robEntries).W)
} }
class Wakeup(p: CoreParams = CoreParams()) extends Bundle {
val valid = Bool()
val phys = UInt(log2Ceil(p.physRegs).W)
val data = UInt(p.xlen.W)
}
class MemRequest(p: CoreParams = CoreParams()) extends Bundle { class MemRequest(p: CoreParams = CoreParams()) extends Bundle {
val addr = UInt(p.xlen.W) val addr = UInt(p.xlen.W)
val data = UInt(p.xlen.W) val data = UInt(p.xlen.W)
@@ -74,3 +83,57 @@ class CsrCommand(p: CoreParams = CoreParams()) extends Bundle {
val rs1 = UInt(p.xlen.W) val rs1 = UInt(p.xlen.W)
val zimm = UInt(5.W) val zimm = UInt(5.W)
} }
class TlbReq(p: CoreParams = CoreParams()) extends Bundle {
val valid = Bool()
val vaddr = UInt(p.xlen.W)
val isStore = Bool()
val isFetch = Bool()
}
class TlbResp(p: CoreParams = CoreParams()) extends Bundle {
val hit = Bool()
val miss = Bool()
val paddr = UInt(p.xlen.W)
val pageFault = Bool()
val accessFault = Bool()
}
class TlbRefill(p: CoreParams = CoreParams()) extends Bundle {
val valid = Bool()
val vpn = UInt(27.W)
val ppn = UInt(44.W)
val level = UInt(2.W)
val flags = UInt(8.W)
}
class PtwMemReq(p: CoreParams = CoreParams()) extends Bundle {
val valid = Bool()
val addr = UInt(p.xlen.W)
}
class PtwMemResp(p: CoreParams = CoreParams()) extends Bundle {
val valid = Bool()
val data = UInt(p.xlen.W)
}
class LoadQueueEntry(p: CoreParams = CoreParams()) extends Bundle {
val valid = Bool()
val robIdx = UInt(log2Ceil(p.robEntries).W)
val addrValid = Bool()
val addr = UInt(p.xlen.W)
val size = UInt(3.W)
val completed = Bool()
val violation = Bool()
}
class StoreQueueEntry(p: CoreParams = CoreParams()) extends Bundle {
val valid = Bool()
val robIdx = UInt(log2Ceil(p.robEntries).W)
val addrValid = Bool()
val dataValid = Bool()
val addr = UInt(p.xlen.W)
val data = UInt(p.xlen.W)
val size = UInt(3.W)
val committed = Bool()
}

4
src/main/scala/common/Parameters.scala
View File

@@ -19,10 +19,10 @@ case class CoreParams(
dCacheWays: Int = 8, dCacheWays: Int = 8,
cacheLineBytes: Int = 64, cacheLineBytes: Int = 64,
itlbEntries: Int = 32, itlbEntries: Int = 32,
dtlbEntries: Int = 32 dtlbEntries: Int = 32,
useOoOBackend: Boolean = false
) { ) {
require(xlen == 64, "this implementation targets RV64") require(xlen == 64, "this implementation targets RV64")
require(fetchWidth == 2, "frontend is parameterized around dual fetch") require(fetchWidth == 2, "frontend is parameterized around dual fetch")
require(issueWidth == 2, "backend structures are parameterized around dual issue") require(issueWidth == 2, "backend structures are parameterized around dual issue")
} }

34
src/main/scala/csr/CSRFile.scala
View File

@@ -4,6 +4,7 @@ import chisel3.util._
class CSRFile(p: CoreParams = CoreParams()) extends Module { class CSRFile(p: CoreParams = CoreParams()) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val cmd = Input(new CsrCommand(p)) val cmd = Input(new CsrCommand(p))
val readAddr = Input(UInt(12.W))
val rdata = Output(UInt(p.xlen.W)) val rdata = Output(UInt(p.xlen.W))
val trap = Input(Bool()) val trap = Input(Bool())
val trapPc = Input(UInt(p.xlen.W)) val trapPc = Input(UInt(p.xlen.W))
@@ -39,7 +40,7 @@ class CSRFile(p: CoreParams = CoreParams()) extends Module {
io.mepc := mepcReg io.mepc := mepcReg
val r = WireDefault(0.U(p.xlen.W)) val r = WireDefault(0.U(p.xlen.W))
switch(io.cmd.addr) { switch(io.readAddr) {
is("h300".U) { r := mstatus } is("h300".U) { r := mstatus }
is("h301".U) { r := misa } is("h301".U) { r := misa }
is("h302".U) { r := medeleg } is("h302".U) { r := medeleg }
@@ -64,11 +65,36 @@ class CSRFile(p: CoreParams = CoreParams()) extends Module {
} }
io.rdata := r io.rdata := r
val writeOld = WireDefault(0.U(p.xlen.W))
switch(io.cmd.addr) {
is("h300".U) { writeOld := mstatus }
is("h301".U) { writeOld := misa }
is("h302".U) { writeOld := medeleg }
is("h303".U) { writeOld := mideleg }
is("h304".U) { writeOld := mie }
is("h305".U) { writeOld := mtvecReg }
is("h341".U) { writeOld := mepcReg }
is("h342".U) { writeOld := mcause }
is("h343".U) { writeOld := mtval }
is("h344".U) { writeOld := mip }
is("h100".U) { writeOld := sstatus }
is("h105".U) { writeOld := stvec }
is("h140".U) { writeOld := sscratch }
is("h141".U) { writeOld := sepc }
is("h142".U) { writeOld := scause }
is("h143".U) { writeOld := stval }
is("h180".U) { writeOld := satpReg }
is("hf14".U) { writeOld := 0.U }
is("hc00".U) { writeOld := cycle }
is("hc01".U) { writeOld := 0.U }
is("hc02".U) { writeOld := instret }
}
val operand = Mux(io.cmd.cmd(2), io.cmd.zimm, io.cmd.rs1) val operand = Mux(io.cmd.cmd(2), io.cmd.zimm, io.cmd.rs1)
val next = MuxLookup(io.cmd.cmd(1, 0), r)(Seq( val next = MuxLookup(io.cmd.cmd(1, 0), writeOld)(Seq(
1.U -> operand, 1.U -> operand,
2.U -> (r | operand), 2.U -> (writeOld | operand),
3.U -> (r & ~operand) 3.U -> (writeOld & ~operand)
)) ))
when(io.cmd.valid && io.cmd.cmd =/= 0.U) { when(io.cmd.valid && io.cmd.cmd =/= 0.U) {

5
src/main/scala/decode/IDStage.scala
View File

@@ -13,8 +13,7 @@ class IDStage(p: CoreParams = CoreParams()) extends Module {
decoders(i).io.pc := io.in.pc + (4 * i).U decoders(i).io.pc := io.in.pc + (4 * i).U
decoders(i).io.inst := io.in.inst(i) decoders(i).io.inst := io.in.inst(i)
io.out(i) := decoders(i).io.out io.out(i) := decoders(i).io.out
io.out(i).valid := io.inValid io.out(i).valid := io.inValid && io.in.laneValid(i)
io.outValid(i) := io.inValid io.outValid(i) := io.inValid && io.in.laneValid(i)
} }
} }

24
src/main/scala/frontend/Frontend.scala
View File

@@ -1,4 +1,5 @@
import chisel3._ import chisel3._
import chisel3.util._
class Frontend(p: CoreParams = CoreParams()) extends Module { class Frontend(p: CoreParams = CoreParams()) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
@@ -8,6 +9,7 @@ class Frontend(p: CoreParams = CoreParams()) extends Module {
val imemReqAddr = Output(UInt(p.xlen.W)) val imemReqAddr = Output(UInt(p.xlen.W))
val imemRespValid = Input(Bool()) val imemRespValid = Input(Bool())
val imemRespBits = Input(Vec(p.fetchWidth, UInt(32.W))) val imemRespBits = Input(Vec(p.fetchWidth, UInt(32.W)))
val outReady = Input(Bool())
val outValid = Output(Bool()) val outValid = Output(Bool())
val out = Output(new FetchPacket(p)) val out = Output(new FetchPacket(p))
val branchUpdate = Input(new BranchUpdate(p)) val branchUpdate = Input(new BranchUpdate(p))
@@ -20,10 +22,21 @@ class Frontend(p: CoreParams = CoreParams()) extends Module {
predictor.io.pc := pc predictor.io.pc := pc
predictor.io.update := io.branchUpdate predictor.io.update := io.branchUpdate
itlb.io.vaddr := pc itlb.io.req.valid := true.B
itlb.io.req.vaddr := pc
itlb.io.req.isStore := false.B
itlb.io.req.isFetch := true.B
itlb.io.refill.valid := false.B
itlb.io.refill.vpn := 0.U
itlb.io.refill.ppn := 0.U
itlb.io.refill.level := 0.U
itlb.io.refill.flags := 0.U
icache.io.reqValid := true.B icache.io.reqValid := true.B
icache.io.reqAddr := itlb.io.paddr icache.io.reqAddr := Mux(itlb.io.resp.hit, itlb.io.resp.paddr, pc)
icache.io.reqPc := pc
icache.io.flush := io.redirectValid
icache.io.respReady := io.outReady
icache.io.memRespValid := io.imemRespValid icache.io.memRespValid := io.imemRespValid
icache.io.memRespBits := io.imemRespBits icache.io.memRespBits := io.imemRespBits
@@ -34,10 +47,11 @@ class Frontend(p: CoreParams = CoreParams()) extends Module {
io.out.predictedTaken := predictor.io.taken io.out.predictedTaken := predictor.io.taken
io.out.predictedTarget := predictor.io.target io.out.predictedTarget := predictor.io.target
val sequentialNextPc = icache.io.resp.pc + (PopCount(icache.io.resp.laneValid) << 2)
when(io.redirectValid) { when(io.redirectValid) {
pc := io.redirectPc pc := io.redirectPc
}.elsewhen(icache.io.respValid) { }.elsewhen(icache.io.respValid && io.outReady) {
pc := Mux(predictor.io.taken, predictor.io.target, pc + (4 * p.fetchWidth).U) pc := Mux(predictor.io.taken, predictor.io.target, sequentialNextPc)
} }
} }

173
src/main/scala/frontend/ICache.scala
View File

@@ -1,23 +1,180 @@
import chisel3._ import chisel3._
import chisel3.util._
class ICache(p: CoreParams = CoreParams()) extends Module { class ICache(p: CoreParams = CoreParams()) extends Module {
private val lineInsts = p.fetchWidth
private val lineBytes = lineInsts * 4
private val sets = p.iCacheBytes / (p.iCacheWays * lineBytes)
private val setBits = log2Ceil(sets)
private val instBits = log2Ceil(lineInsts)
private val offsetBits = log2Ceil(lineBytes)
val io = IO(new Bundle { val io = IO(new Bundle {
val reqValid = Input(Bool()) val reqValid = Input(Bool())
val reqAddr = Input(UInt(p.xlen.W)) val reqAddr = Input(UInt(p.xlen.W))
val reqPc = Input(UInt(p.xlen.W))
val flush = Input(Bool())
val respReady = Input(Bool())
val memReqValid = Output(Bool()) val memReqValid = Output(Bool())
val memReqAddr = Output(UInt(p.xlen.W)) val memReqAddr = Output(UInt(p.xlen.W))
val memRespValid = Input(Bool()) val memRespValid = Input(Bool())
val memRespBits = Input(Vec(p.fetchWidth, UInt(32.W))) val memRespBits = Input(Vec(p.fetchWidth, UInt(32.W)))
val respValid = Output(Bool()) val respValid = Output(Bool())
val resp = Output(new FetchPacket(p)) val resp = Output(new FetchPacket(p))
val miss = Output(Bool())
}) })
io.memReqValid := io.reqValid def setIndex(addr: UInt): UInt = addr(offsetBits + setBits - 1, offsetBits)
io.memReqAddr := io.reqAddr def instIndex(addr: UInt): UInt = addr(offsetBits - 1, 2)
io.respValid := io.memRespValid def tag(addr: UInt): UInt = addr(p.xlen - 1, offsetBits + setBits)
io.resp.pc := io.reqAddr def alignedFetchAddr(addr: UInt): UInt = Cat(addr(p.xlen - 1, offsetBits), 0.U(offsetBits.W))
io.resp.inst := io.memRespBits
io.resp.predictedTaken := false.B
io.resp.predictedTarget := io.reqAddr + (4 * p.fetchWidth).U
}
val valid = RegInit(VecInit(Seq.fill(sets)(VecInit(Seq.fill(p.iCacheWays)(
VecInit(Seq.fill(lineInsts)(false.B)))))))
val tags = SyncReadMem(sets, Vec(p.iCacheWays, UInt((p.xlen - offsetBits - setBits).W)))
val data = SyncReadMem(sets, Vec(p.iCacheWays, Vec(lineInsts, UInt(32.W))))
val repl = RegInit(VecInit(Seq.fill(sets)(0.U(log2Ceil(p.iCacheWays).W))))
val sIdle :: sLookup :: sResp :: sMiss :: Nil = Enum(4)
val state = RegInit(sIdle)
val lookupAddr = Reg(UInt(p.xlen.W))
val lookupPc = Reg(UInt(p.xlen.W))
val lookupSet = Reg(UInt(setBits.W))
val lookupInst = Reg(UInt(instBits.W))
val lookupValidRow = Reg(Vec(p.iCacheWays, Vec(lineInsts, Bool())))
val missAddr = Reg(UInt(p.xlen.W))
val missPc = Reg(UInt(p.xlen.W))
val missSet = Reg(UInt(setBits.W))
val missInst = Reg(UInt(instBits.W))
val missWay = Reg(UInt(log2Ceil(p.iCacheWays).W))
val missRefillExisting = Reg(Bool())
val missTagRow = Reg(Vec(p.iCacheWays, UInt((p.xlen - offsetBits - setBits).W)))
val missDataRow = Reg(Vec(p.iCacheWays, Vec(lineInsts, UInt(32.W))))
val missValidRow = Reg(Vec(p.iCacheWays, Vec(lineInsts, Bool())))
val missReqSent = RegInit(false.B)
val respReg = Reg(new FetchPacket(p))
val reqSet = setIndex(io.reqAddr)
val reqInst = instIndex(io.reqAddr)
val readFire = state === sIdle && io.reqValid && !io.flush
val readTags = tags.read(reqSet, readFire)
val readData = data.read(reqSet, readFire)
val tagHitVec = VecInit((0 until p.iCacheWays).map(w => lookupValidRow(w).asUInt.orR && readTags(w) === tag(lookupAddr)))
val hitVec = VecInit((0 until p.iCacheWays).map(w => tagHitVec(w) && lookupValidRow(w)(lookupInst)))
val hit = hitVec.asUInt.orR
val hitWay = OHToUInt(hitVec)
val tagHit = tagHitVec.asUInt.orR
val tagHitWay = OHToUInt(tagHitVec)
val lastInst = (lineInsts - 1).U(instBits.W)
val nextInst = lookupInst + 1.U
val lookupCanFetchPair = lookupInst =/= lastInst
val lookupLane1Valid = lookupCanFetchPair && lookupValidRow(hitWay)(nextInst)
val lookupResp = WireDefault(0.U.asTypeOf(new FetchPacket(p)))
lookupResp.pc := lookupPc
lookupResp.inst(0) := readData(hitWay)(lookupInst)
lookupResp.inst(1) := Mux(lookupLane1Valid, readData(hitWay)(nextInst), 0.U)
lookupResp.laneValid(0) := true.B
lookupResp.laneValid(1) := lookupLane1Valid
lookupResp.predictedTaken := false.B
lookupResp.predictedTarget := lookupPc + (4 * p.fetchWidth).U
val missCanFetchPair = missInst =/= lastInst
val missResp = WireDefault(0.U.asTypeOf(new FetchPacket(p)))
missResp.pc := missPc
missResp.inst(0) := io.memRespBits(0)
missResp.inst(1) := Mux(missCanFetchPair, io.memRespBits(1), 0.U)
missResp.laneValid(0) := true.B
missResp.laneValid(1) := missCanFetchPair
missResp.predictedTaken := false.B
missResp.predictedTarget := missPc + (4 * p.fetchWidth).U
io.memReqValid := state === sMiss && !missReqSent
io.memReqAddr := Mux(state === sMiss,
Mux(missCanFetchPair, alignedFetchAddr(missAddr), missAddr),
Mux(reqInst =/= lastInst, alignedFetchAddr(io.reqAddr), io.reqAddr))
io.respValid := (state === sLookup && hit) || state === sResp || (state === sMiss && io.memRespValid)
io.resp := Mux(state === sResp, respReg,
Mux(state === sMiss && io.memRespValid, missResp, lookupResp))
io.miss := state === sLookup && !hit || state === sMiss
when(io.flush) {
state := sIdle
missReqSent := false.B
}.elsewhen(state === sIdle) {
when(io.reqValid) {
lookupAddr := io.reqAddr
lookupPc := io.reqPc
lookupSet := reqSet
lookupInst := reqInst
lookupValidRow := valid(reqSet)
state := sLookup
}
}.elsewhen(state === sLookup) {
when(hit) {
repl(lookupSet) := hitWay
when(io.respReady) {
state := sIdle
}.otherwise {
respReg := lookupResp
state := sResp
}
}.otherwise {
missAddr := lookupAddr
missPc := lookupPc
missSet := lookupSet
missInst := lookupInst
missWay := Mux(tagHit, tagHitWay, repl(lookupSet))
missRefillExisting := tagHit
missTagRow := readTags
missDataRow := readData
missValidRow := lookupValidRow
missReqSent := false.B
state := sMiss
}
}.elsewhen(state === sResp) {
when(io.respReady) {
state := sIdle
}
}.elsewhen(state === sMiss) {
when(!missReqSent) {
missReqSent := true.B
}
when(io.memRespValid) {
val tagWrite = Wire(Vec(p.iCacheWays, UInt((p.xlen - offsetBits - setBits).W)))
val dataWrite = Wire(Vec(p.iCacheWays, Vec(lineInsts, UInt(32.W))))
val validWrite = Wire(Vec(p.iCacheWays, Vec(lineInsts, Bool())))
tagWrite := missTagRow
dataWrite := missDataRow
validWrite := missValidRow
tagWrite(missWay) := tag(missAddr)
when(!missRefillExisting) {
for (i <- 0 until lineInsts) {
validWrite(missWay)(i) := false.B
}
}
dataWrite(missWay)(missInst) := io.memRespBits(0)
validWrite(missWay)(missInst) := true.B
when(missCanFetchPair) {
dataWrite(missWay)(missInst + 1.U) := io.memRespBits(1)
validWrite(missWay)(missInst + 1.U) := true.B
}
valid(missSet) := validWrite
tags.write(missSet, tagWrite)
data.write(missSet, dataWrite)
when(!missRefillExisting) {
repl(missSet) := missWay + 1.U
}
when(io.respReady) {
state := sIdle
}.otherwise {
respReg := missResp
state := sResp
}
}
}
}

46
src/main/scala/frontend/ITLB.scala
View File

@@ -2,15 +2,45 @@ import chisel3._
import chisel3.util._ import chisel3.util._
class ITLB(p: CoreParams = CoreParams()) extends Module { class ITLB(p: CoreParams = CoreParams()) extends Module {
private val vpnBits = 27
private val ppnBits = 44
private val idxBits = log2Ceil(p.itlbEntries)
val io = IO(new Bundle { val io = IO(new Bundle {
val vaddr = Input(UInt(p.xlen.W)) val req = Input(new TlbReq(p))
val paddr = Output(UInt(p.xlen.W)) val resp = Output(new TlbResp(p))
val hit = Output(Bool()) val refill = Input(new TlbRefill(p))
val miss = Output(Bool()) val missVpn = Output(UInt(vpnBits.W))
}) })
io.paddr := io.vaddr val valid = RegInit(VecInit(Seq.fill(p.itlbEntries)(false.B)))
io.hit := true.B val vpn = Reg(Vec(p.itlbEntries, UInt(vpnBits.W)))
io.miss := false.B val ppn = Reg(Vec(p.itlbEntries, UInt(ppnBits.W)))
} val level = Reg(Vec(p.itlbEntries, UInt(2.W)))
val flags = Reg(Vec(p.itlbEntries, UInt(8.W)))
val repl = RegInit(0.U(idxBits.W))
val reqVpn = io.req.vaddr(38, 12)
val pageOff = io.req.vaddr(11, 0)
val hitVec = VecInit((0 until p.itlbEntries).map(i => valid(i) && vpn(i) === reqVpn))
val hit = io.req.valid && hitVec.asUInt.orR
val hitIdx = OHToUInt(hitVec)
val x = flags(hitIdx)(3)
val pageFault = hit && !x
io.resp.hit := hit && !pageFault
io.resp.miss := io.req.valid && !hit
io.resp.paddr := Cat(ppn(hitIdx), pageOff)
io.resp.pageFault := pageFault
io.resp.accessFault := false.B
io.missVpn := reqVpn
when(io.refill.valid) {
valid(repl) := true.B
vpn(repl) := io.refill.vpn
ppn(repl) := io.refill.ppn
level(repl) := io.refill.level
flags(repl) := io.refill.flags
repl := repl + 1.U
}
}

15
src/main/scala/issue/IssueQueue.scala
View File

@@ -2,18 +2,20 @@ import chisel3._
class IssueQueue(p: CoreParams = CoreParams()) extends Module { class IssueQueue(p: CoreParams = CoreParams()) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val enqValid = Input(Bool()) val enqValid = Input(Vec(p.issueWidth, Bool()))
val enq = Input(new RenamePacket(p)) val enq = Input(Vec(p.issueWidth, new RenamePacket(p)))
val enqReady = Output(Bool()) val enqReady = Output(Vec(p.issueWidth, Bool()))
val issueValid = Output(Bool()) val wakeup = Input(Vec(p.issueWidth, new Wakeup(p)))
val issue = Output(new RenamePacket(p)) val issueValid = Output(Vec(p.issueWidth, Bool()))
val issueReady = Input(Bool()) val issue = Output(Vec(p.issueWidth, new RenamePacket(p)))
val issueReady = Input(Vec(p.issueWidth, Bool()))
val flush = Input(Bool()) val flush = Input(Bool())
}) })
val intRs = Module(new ReservationStation(p, p.intRsEntries)) val intRs = Module(new ReservationStation(p, p.intRsEntries))
intRs.io.enqValid := io.enqValid intRs.io.enqValid := io.enqValid
intRs.io.enq := io.enq intRs.io.enq := io.enq
intRs.io.wakeup := io.wakeup
intRs.io.issueReady := io.issueReady intRs.io.issueReady := io.issueReady
intRs.io.flush := io.flush intRs.io.flush := io.flush
@@ -21,4 +23,3 @@ class IssueQueue(p: CoreParams = CoreParams()) extends Module {
io.issueValid := intRs.io.issueValid io.issueValid := intRs.io.issueValid
io.issue := intRs.io.issue io.issue := intRs.io.issue
} }

15
src/main/scala/issue/IssueStage.scala
View File

@@ -2,18 +2,20 @@ import chisel3._
class IssueStage(p: CoreParams = CoreParams()) extends Module { class IssueStage(p: CoreParams = CoreParams()) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val inValid = Input(Bool()) val inValid = Input(Vec(p.issueWidth, Bool()))
val in = Input(new RenamePacket(p)) val in = Input(Vec(p.issueWidth, new RenamePacket(p)))
val inReady = Output(Bool()) val inReady = Output(Vec(p.issueWidth, Bool()))
val outValid = Output(Bool()) val wakeup = Input(Vec(p.issueWidth, new Wakeup(p)))
val out = Output(new RenamePacket(p)) val outValid = Output(Vec(p.issueWidth, Bool()))
val outReady = Input(Bool()) val out = Output(Vec(p.issueWidth, new RenamePacket(p)))
val outReady = Input(Vec(p.issueWidth, Bool()))
val flush = Input(Bool()) val flush = Input(Bool())
}) })
val queue = Module(new IssueQueue(p)) val queue = Module(new IssueQueue(p))
queue.io.enqValid := io.inValid queue.io.enqValid := io.inValid
queue.io.enq := io.in queue.io.enq := io.in
queue.io.wakeup := io.wakeup
queue.io.issueReady := io.outReady queue.io.issueReady := io.outReady
queue.io.flush := io.flush queue.io.flush := io.flush
@@ -21,4 +23,3 @@ class IssueStage(p: CoreParams = CoreParams()) extends Module {
io.outValid := queue.io.issueValid io.outValid := queue.io.issueValid
io.out := queue.io.issue io.out := queue.io.issue
} }

73
src/main/scala/issue/ReservationStation.scala
View File

@@ -3,22 +3,69 @@ import chisel3.util._
class ReservationStation(p: CoreParams = CoreParams(), entries: Int = 16) extends Module { class ReservationStation(p: CoreParams = CoreParams(), entries: Int = 16) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val enqValid = Input(Bool()) val enqValid = Input(Vec(p.issueWidth, Bool()))
val enq = Input(new RenamePacket(p)) val enq = Input(Vec(p.issueWidth, new RenamePacket(p)))
val enqReady = Output(Bool()) val enqReady = Output(Vec(p.issueWidth, Bool()))
val issueValid = Output(Bool()) val wakeup = Input(Vec(p.issueWidth, new Wakeup(p)))
val issue = Output(new RenamePacket(p)) val issueValid = Output(Vec(p.issueWidth, Bool()))
val issueReady = Input(Bool()) val issue = Output(Vec(p.issueWidth, new RenamePacket(p)))
val issueReady = Input(Vec(p.issueWidth, Bool()))
val flush = Input(Bool()) val flush = Input(Bool())
}) })
val q = Module(new Queue(new RenamePacket(p), entries, flow = false, pipe = true)) val valid = RegInit(VecInit(Seq.fill(entries)(false.B)))
q.io.enq.valid := io.enqValid val slots = Reg(Vec(entries, new RenamePacket(p)))
q.io.enq.bits := io.enq
q.io.deq.ready := io.issueReady || io.flush
io.enqReady := q.io.enq.ready val freeMask = VecInit(valid.map(!_.asBool)).asUInt
io.issueValid := q.io.deq.valid && !io.flush val enq0OH = PriorityEncoderOH(freeMask)
io.issue := q.io.deq.bits val enq1OH = PriorityEncoderOH(freeMask & ~enq0OH)
io.enqReady(0) := freeMask.orR
io.enqReady(1) := (freeMask & ~enq0OH).orR
val readyVec = Wire(Vec(entries, Bool()))
for (i <- 0 until entries) {
val src1Wake = io.wakeup.map(w => w.valid && w.phys === slots(i).prs1).reduce(_ || _)
val src2Wake = io.wakeup.map(w => w.valid && w.phys === slots(i).prs2).reduce(_ || _)
val src1ReadyNow = slots(i).src1Ready || src1Wake || slots(i).decoded.rs1 === 0.U
val src2ReadyNow = slots(i).src2Ready || src2Wake || slots(i).decoded.rs2 === 0.U
readyVec(i) := valid(i) && src1ReadyNow && src2ReadyNow
} }
val issue0OH = PriorityEncoderOH(readyVec.asUInt)
val issue1OH = PriorityEncoderOH(readyVec.asUInt & ~issue0OH)
io.issueValid(0) := readyVec.asUInt.orR
io.issueValid(1) := (readyVec.asUInt & ~issue0OH).orR
io.issue(0) := Mux1H(issue0OH, slots)
io.issue(1) := Mux1H(issue1OH, slots)
when(io.flush) {
valid := VecInit(Seq.fill(entries)(false.B))
}.otherwise {
for (i <- 0 until entries) {
when(valid(i)) {
for (w <- 0 until p.issueWidth) {
when(io.wakeup(w).valid && io.wakeup(w).phys === slots(i).prs1) {
slots(i).src1Ready := true.B
}
when(io.wakeup(w).valid && io.wakeup(w).phys === slots(i).prs2) {
slots(i).src2Ready := true.B
}
}
}
when(issue0OH(i) && io.issueReady(0)) {
valid(i) := false.B
}
when(issue1OH(i) && io.issueReady(1)) {
valid(i) := false.B
}
when(enq0OH(i) && io.enqValid(0) && io.enqReady(0)) {
valid(i) := true.B
slots(i) := io.enq(0)
}
when(enq1OH(i) && io.enqValid(1) && io.enqReady(1)) {
valid(i) := true.B
slots(i) := io.enq(1)
}
}
}
}

112
src/main/scala/memory/DCache.scala
View File

@@ -1,20 +1,124 @@
import chisel3._ import chisel3._
import chisel3.util._
class DCache(p: CoreParams = CoreParams()) extends Module { class DCache(p: CoreParams = CoreParams()) extends Module {
private val lineWords = p.cacheLineBytes / (p.xlen / 8)
private val sets = p.dCacheBytes / (p.dCacheWays * p.cacheLineBytes)
private val setBits = log2Ceil(sets)
private val wordBits = log2Ceil(lineWords)
private val byteBits = log2Ceil(p.xlen / 8)
private val offsetBits = log2Ceil(p.cacheLineBytes)
val io = IO(new Bundle { val io = IO(new Bundle {
val reqValid = Input(Bool()) val reqValid = Input(Bool())
val req = Input(new MemRequest(p)) val req = Input(new MemRequest(p))
val reqReady = Output(Bool())
val memReqValid = Output(Bool()) val memReqValid = Output(Bool())
val memReq = Output(new MemRequest(p)) val memReq = Output(new MemRequest(p))
val memRespValid = Input(Bool()) val memRespValid = Input(Bool())
val memRespData = Input(UInt(p.xlen.W)) val memRespData = Input(UInt(p.xlen.W))
val respValid = Output(Bool()) val respValid = Output(Bool())
val respData = Output(UInt(p.xlen.W)) val respData = Output(UInt(p.xlen.W))
val miss = Output(Bool())
}) })
io.memReqValid := io.reqValid def lineAddr(addr: UInt): UInt = Cat(addr(p.xlen - 1, offsetBits), 0.U(offsetBits.W))
io.memReq := io.req def setIndex(addr: UInt): UInt = addr(offsetBits + setBits - 1, offsetBits)
io.respValid := io.memRespValid def wordIndex(addr: UInt): UInt = addr(offsetBits - 1, byteBits)
io.respData := io.memRespData def tag(addr: UInt): UInt = addr(p.xlen - 1, offsetBits + setBits)
def loadSelect(word: UInt, addr: UInt, size: UInt, signed: Bool = true.B): UInt = {
val byteShift = addr(byteBits - 1, 0) << 3
val shifted = word >> byteShift
val b = shifted(7, 0)
val h = shifted(15, 0)
val w = shifted(31, 0)
MuxLookup(size, word)(Seq(
0.U -> Mux(signed, Consts.signExtend(b, 8), b),
1.U -> Mux(signed, Consts.signExtend(h, 16), h),
2.U -> Mux(signed, Consts.signExtend(w, 32), w),
3.U -> word
))
} }
val valid = RegInit(VecInit(Seq.fill(sets)(VecInit(Seq.fill(p.dCacheWays)(false.B)))))
val tags = SyncReadMem(sets, Vec(p.dCacheWays, UInt((p.xlen - offsetBits - setBits).W)))
val data = SyncReadMem(sets, Vec(p.dCacheWays, Vec(lineWords, UInt(p.xlen.W))))
val repl = RegInit(VecInit(Seq.fill(sets)(0.U(log2Ceil(p.dCacheWays).W))))
val sIdle :: sLookup :: sMiss :: Nil = Enum(3)
val state = RegInit(sIdle)
val reqReg = Reg(new MemRequest(p))
val reqSet = Reg(UInt(setBits.W))
val reqWord = Reg(UInt(wordBits.W))
val reqValidRow = Reg(Vec(p.dCacheWays, Bool()))
val missWay = Reg(UInt(log2Ceil(p.dCacheWays).W))
val missTagRow = Reg(Vec(p.dCacheWays, UInt((p.xlen - offsetBits - setBits).W)))
val missDataRow = Reg(Vec(p.dCacheWays, Vec(lineWords, UInt(p.xlen.W))))
val set = setIndex(io.req.addr)
val word = wordIndex(io.req.addr)
val readFire = state === sIdle && io.reqValid && !io.req.isStore
val readTags = tags.read(set, readFire)
val readData = data.read(set, readFire)
val hitVec = VecInit((0 until p.dCacheWays).map(w => reqValidRow(w) && readTags(w) === tag(reqReg.addr)))
val hit = hitVec.asUInt.orR
val hitWay = OHToUInt(hitVec)
val hitWord = readData(hitWay)(reqWord)
val hitResp = loadSelect(hitWord, reqReg.addr, reqReg.size)
val storeBypass = state === sIdle && io.reqValid && io.req.isStore
val memReq = WireDefault(0.U.asTypeOf(new MemRequest(p)))
memReq.addr := lineAddr(reqReg.addr) + (reqWord << byteBits)
memReq.data := reqReg.data
memReq.isStore := reqReg.isStore
memReq.size := 3.U
io.reqReady := state === sIdle
io.memReqValid := state === sMiss || storeBypass
io.memReq := Mux(storeBypass, io.req, memReq)
io.respValid := state === sLookup && hit && !reqReg.isStore ||
state === sMiss && io.memRespValid && !reqReg.isStore
io.respData := Mux(state === sMiss, loadSelect(io.memRespData, reqReg.addr, reqReg.size), hitResp)
io.miss := state === sLookup && !hit || state === sMiss
when(storeBypass) {
valid(set) := VecInit(Seq.fill(p.dCacheWays)(false.B))
}
when(state === sIdle) {
when(io.reqValid && !io.req.isStore) {
reqReg := io.req
reqSet := set
reqWord := word
reqValidRow := valid(set)
state := sLookup
}
}.elsewhen(state === sLookup) {
when(hit) {
repl(reqSet) := hitWay
state := sIdle
}.otherwise {
val way = repl(reqSet)
missWay := way
missTagRow := readTags
missDataRow := readData
state := sMiss
}
}.elsewhen(state === sMiss) {
when(io.memRespValid) {
val tagWrite = Wire(Vec(p.dCacheWays, UInt((p.xlen - offsetBits - setBits).W)))
val dataWrite = Wire(Vec(p.dCacheWays, Vec(lineWords, UInt(p.xlen.W))))
tagWrite := missTagRow
dataWrite := missDataRow
tagWrite(missWay) := tag(reqReg.addr)
dataWrite(missWay)(reqWord) := io.memRespData
valid(reqSet)(missWay) := true.B
tags.write(reqSet, tagWrite)
data.write(reqSet, dataWrite)
repl(reqSet) := missWay + 1.U
state := sIdle
}
}
}

48
src/main/scala/memory/DTLB.scala
View File

@@ -1,15 +1,47 @@
import chisel3._ import chisel3._
import chisel3.util._
class DTLB(p: CoreParams = CoreParams()) extends Module { class DTLB(p: CoreParams = CoreParams()) extends Module {
private val vpnBits = 27
private val ppnBits = 44
private val idxBits = log2Ceil(p.dtlbEntries)
val io = IO(new Bundle { val io = IO(new Bundle {
val vaddr = Input(UInt(p.xlen.W)) val req = Input(new TlbReq(p))
val paddr = Output(UInt(p.xlen.W)) val resp = Output(new TlbResp(p))
val hit = Output(Bool()) val refill = Input(new TlbRefill(p))
val miss = Output(Bool()) val missVpn = Output(UInt(vpnBits.W))
}) })
io.paddr := io.vaddr val valid = RegInit(VecInit(Seq.fill(p.dtlbEntries)(false.B)))
io.hit := true.B val vpn = Reg(Vec(p.dtlbEntries, UInt(vpnBits.W)))
io.miss := false.B val ppn = Reg(Vec(p.dtlbEntries, UInt(ppnBits.W)))
} val level = Reg(Vec(p.dtlbEntries, UInt(2.W)))
val flags = Reg(Vec(p.dtlbEntries, UInt(8.W)))
val repl = RegInit(0.U(idxBits.W))
val reqVpn = io.req.vaddr(38, 12)
val pageOff = io.req.vaddr(11, 0)
val hitVec = VecInit((0 until p.dtlbEntries).map(i => valid(i) && vpn(i) === reqVpn))
val hit = io.req.valid && hitVec.asUInt.orR
val hitIdx = OHToUInt(hitVec)
val r = flags(hitIdx)(1)
val w = flags(hitIdx)(2)
val pageFault = hit && Mux(io.req.isStore, !w, !r)
io.resp.hit := hit && !pageFault
io.resp.miss := io.req.valid && !hit
io.resp.paddr := Cat(ppn(hitIdx), pageOff)
io.resp.pageFault := pageFault
io.resp.accessFault := false.B
io.missVpn := reqVpn
when(io.refill.valid) {
valid(repl) := true.B
vpn(repl) := io.refill.vpn
ppn(repl) := io.refill.ppn
level(repl) := io.refill.level
flags(repl) := io.refill.flags
repl := repl + 1.U
}
}

58
src/main/scala/memory/LSU.scala
View File

@@ -1,30 +1,68 @@
import chisel3._ import chisel3._
import chisel3.util._
class LSU(p: CoreParams = CoreParams()) extends Module { class LSU(p: CoreParams = CoreParams()) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val reqValid = Input(Bool()) val reqValid = Input(Bool())
val req = Input(new MemRequest(p)) val req = Input(new MemRequest(p))
val reqReady = Output(Bool())
val satp = Input(UInt(p.xlen.W))
val dmemReqValid = Output(Bool()) val dmemReqValid = Output(Bool())
val dmemReq = Output(new MemRequest(p)) val dmemReq = Output(new MemRequest(p))
val dmemRespValid = Input(Bool()) val dmemRespValid = Input(Bool())
val dmemRespData = Input(UInt(p.xlen.W)) val dmemRespData = Input(UInt(p.xlen.W))
val respValid = Output(Bool()) val respValid = Output(Bool())
val respData = Output(UInt(p.xlen.W)) val respData = Output(UInt(p.xlen.W))
val pageFault = Output(Bool())
}) })
val dtlb = Module(new DTLB(p)) val dtlb = Module(new DTLB(p))
val mmu = Module(new MMU(p))
val dcache = Module(new DCache(p)) val dcache = Module(new DCache(p))
val bare = io.satp(63, 60) === 0.U
dtlb.io.vaddr := io.req.addr dtlb.io.req.valid := io.reqValid && !bare
dcache.io.reqValid := io.reqValid dtlb.io.req.vaddr := io.req.addr
dcache.io.req := io.req dtlb.io.req.isStore := io.req.isStore
dcache.io.req.addr := dtlb.io.paddr dtlb.io.req.isFetch := false.B
dcache.io.memRespValid := io.dmemRespValid
dcache.io.memRespData := io.dmemRespData
io.dmemReqValid := dcache.io.memReqValid mmu.io.satp := io.satp
io.dmemReq := dcache.io.memReq mmu.io.req.valid := io.reqValid && !bare && dtlb.io.resp.miss
io.respValid := dcache.io.respValid mmu.io.req.vaddr := io.req.addr
io.respData := dcache.io.respData mmu.io.req.isStore := io.req.isStore
mmu.io.req.isFetch := false.B
dtlb.io.refill := mmu.io.refill
val ptwOutstanding = RegInit(false.B)
when(mmu.io.ptwMemReq.valid) {
ptwOutstanding := true.B
}.elsewhen(io.dmemRespValid && ptwOutstanding) {
ptwOutstanding := false.B
} }
mmu.io.ptwMemResp.valid := io.dmemRespValid && ptwOutstanding
mmu.io.ptwMemResp.data := io.dmemRespData
val translatedAddr = Mux(bare, io.req.addr, dtlb.io.resp.paddr)
val translationReady = bare || dtlb.io.resp.hit
val translationFault = dtlb.io.resp.pageFault || mmu.io.resp.pageFault
io.reqReady := dcache.io.reqReady && !ptwOutstanding
dcache.io.reqValid := io.reqValid && translationReady && !translationFault
dcache.io.req := io.req
dcache.io.req.addr := translatedAddr
dcache.io.memRespValid := io.dmemRespValid && !ptwOutstanding
dcache.io.memRespData := io.dmemRespData
val ptwReqAsMem = WireDefault(0.U.asTypeOf(new MemRequest(p)))
ptwReqAsMem.addr := mmu.io.ptwMemReq.addr
ptwReqAsMem.data := 0.U
ptwReqAsMem.isStore := false.B
ptwReqAsMem.size := 3.U
io.dmemReqValid := mmu.io.ptwMemReq.valid || dcache.io.memReqValid
io.dmemReq := Mux(mmu.io.ptwMemReq.valid, ptwReqAsMem, dcache.io.memReq)
io.respValid := dcache.io.respValid || translationFault
io.respData := dcache.io.respData
io.pageFault := translationFault
}

70
src/main/scala/memory/LoadQueue.scala
View File

@@ -2,22 +2,78 @@ import chisel3._
import chisel3.util._ import chisel3.util._
class LoadQueue(p: CoreParams = CoreParams()) extends Module { class LoadQueue(p: CoreParams = CoreParams()) extends Module {
private val idxBits = log2Ceil(p.loadQueueEntries)
private val robBits = log2Ceil(p.robEntries)
val io = IO(new Bundle { val io = IO(new Bundle {
val enqValid = Input(Bool()) val enqValid = Input(Bool())
val enqAddr = Input(UInt(p.xlen.W)) val enqRobIdx = Input(UInt(robBits.W))
val enqReady = Output(Bool()) val enqReady = Output(Bool())
val enqIdx = Output(UInt(idxBits.W))
val addrValid = Input(Bool())
val addrIdx = Input(UInt(idxBits.W))
val addr = Input(UInt(p.xlen.W))
val size = Input(UInt(3.W))
val complete = Input(Bool()) val complete = Input(Bool())
val completeIdx = Input(UInt(idxBits.W))
val storeAddrValid = Input(Bool())
val storeRobIdx = Input(UInt(robBits.W))
val storeAddr = Input(UInt(p.xlen.W))
val storeSize = Input(UInt(3.W))
val violation = Output(Bool())
val flush = Input(Bool()) val flush = Input(Bool())
}) })
val count = RegInit(0.U(log2Ceil(p.loadQueueEntries + 1).W)) val entries = RegInit(VecInit(Seq.fill(p.loadQueueEntries)(0.U.asTypeOf(new LoadQueueEntry(p)))))
io.enqReady := count =/= p.loadQueueEntries.U val freeMask = VecInit(entries.map(e => !e.valid)).asUInt
val enqOH = PriorityEncoderOH(freeMask)
val enqIdx = OHToUInt(enqOH)
def overlap(a: UInt, as: UInt, b: UInt, bs: UInt): Bool = {
val am = MuxLookup(as, 7.U)(Seq(0.U -> 0.U, 1.U -> 1.U, 2.U -> 3.U, 3.U -> 7.U))
val bm = MuxLookup(bs, 7.U)(Seq(0.U -> 0.U, 1.U -> 1.U, 2.U -> 3.U, 3.U -> 7.U))
val a0 = a(p.xlen - 1, 3)
val b0 = b(p.xlen - 1, 3)
a0 === b0 && ((a(2, 0) | am) >= b(2, 0)) && ((b(2, 0) | bm) >= a(2, 0))
}
io.enqReady := freeMask.orR
io.enqIdx := enqIdx
val violationVec = Wire(Vec(p.loadQueueEntries, Bool()))
for (i <- 0 until p.loadQueueEntries) {
val youngerLoad = entries(i).robIdx > io.storeRobIdx
violationVec(i) := io.storeAddrValid && entries(i).valid && entries(i).completed &&
entries(i).addrValid && youngerLoad && overlap(entries(i).addr, entries(i).size, io.storeAddr, io.storeSize)
}
io.violation := violationVec.asUInt.orR
when(io.flush) { when(io.flush) {
count := 0.U entries.foreach(_ := 0.U.asTypeOf(new LoadQueueEntry(p)))
}.otherwise { }.otherwise {
when(io.enqValid && io.enqReady) { count := count + 1.U } when(io.enqValid && io.enqReady) {
when(io.complete && count =/= 0.U) { count := count - 1.U } entries(enqIdx).valid := true.B
entries(enqIdx).robIdx := io.enqRobIdx
entries(enqIdx).addrValid := false.B
entries(enqIdx).completed := false.B
entries(enqIdx).violation := false.B
}
when(io.addrValid) {
entries(io.addrIdx).addrValid := true.B
entries(io.addrIdx).addr := io.addr
entries(io.addrIdx).size := io.size
}
when(io.complete) {
entries(io.completeIdx).completed := true.B
}
for (i <- 0 until p.loadQueueEntries) {
when(violationVec(i)) {
entries(i).violation := true.B
}
}
} }
} }

123
src/main/scala/memory/MMU.scala
View File

@@ -1,15 +1,124 @@
import chisel3._ import chisel3._
import chisel3.util._
class PageTableWalker(p: CoreParams = CoreParams()) extends Module {
val io = IO(new Bundle {
val reqValid = Input(Bool())
val reqVpn = Input(UInt(27.W))
val isStore = Input(Bool())
val isFetch = Input(Bool())
val satp = Input(UInt(p.xlen.W))
val memReq = Output(new PtwMemReq(p))
val memResp = Input(new PtwMemResp(p))
val respValid = Output(Bool())
val refill = Output(new TlbRefill(p))
val pageFault = Output(Bool())
})
val sIdle :: sL2 :: sL1 :: sL0 :: sDone :: Nil = Enum(5)
val state = RegInit(sIdle)
val vpnReg = Reg(UInt(27.W))
val isStoreReg = Reg(Bool())
val isFetchReg = Reg(Bool())
val rootPpn = io.satp(43, 0)
val pte = io.memResp.data
val pteV = pte(0)
val pteR = pte(1)
val pteW = pte(2)
val pteX = pte(3)
val pteU = pte(4)
val pteG = pte(5)
val pteA = pte(6)
val pteD = pte(7)
val pteFlags = pte(7, 0)
val ptePpn = pte(53, 10)
val pteIsLeaf = pteR || pteX
val invalidPte = !pteV || (!pteR && pteW)
val permFault = Mux(isFetchReg, !pteX, Mux(isStoreReg, !pteW || !pteD, !pteR)) || !pteA
val walkFault = RegInit(false.B)
val nextPpn = Reg(UInt(44.W))
def vpnPart(vpn: UInt, level: Int): UInt =
vpn(9 * level + 8, 9 * level)
val level = Wire(UInt(2.W))
level := Mux(state === sL2, 2.U, Mux(state === sL1, 1.U, 0.U))
val curPpn = Reg(UInt(44.W))
val pteAddr = Cat(curPpn, vpnPart(vpnReg, 0), 0.U(3.W))
val pteAddrL1 = Cat(curPpn, vpnPart(vpnReg, 1), 0.U(3.W))
val pteAddrL2 = Cat(rootPpn, vpnPart(vpnReg, 2), 0.U(3.W))
io.memReq.valid := state === sL2 || state === sL1 || state === sL0
io.memReq.addr := Mux(state === sL2, pteAddrL2, Mux(state === sL1, pteAddrL1, pteAddr))
io.respValid := state === sDone
io.pageFault := walkFault
io.refill.valid := state === sDone && !walkFault
io.refill.vpn := vpnReg
io.refill.level := level
io.refill.flags := pteFlags
io.refill.ppn := nextPpn
when(state === sIdle) {
walkFault := false.B
when(io.reqValid) {
vpnReg := io.reqVpn
isStoreReg := io.isStore
isFetchReg := io.isFetch
state := sL2
}
}.elsewhen((state === sL2 || state === sL1 || state === sL0) && io.memResp.valid) {
when(invalidPte) {
walkFault := true.B
state := sDone
}.elsewhen(pteIsLeaf) {
when(permFault) {
walkFault := true.B
}
val ppn0 = Mux(level === 0.U, ptePpn(8, 0), vpnReg(8, 0))
val ppn1 = Mux(level <= 1.U, ptePpn(17, 9), vpnReg(17, 9))
val ppn2 = ptePpn(43, 18)
nextPpn := Cat(ppn2, ppn1, ppn0)
state := sDone
}.otherwise {
curPpn := ptePpn
when(state === sL2) {
state := sL1
}.elsewhen(state === sL1) {
state := sL0
}.otherwise {
walkFault := true.B
state := sDone
}
}
}.elsewhen(state === sDone) {
state := sIdle
}
}
class MMU(p: CoreParams = CoreParams()) extends Module { class MMU(p: CoreParams = CoreParams()) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val satp = Input(UInt(p.xlen.W)) val satp = Input(UInt(p.xlen.W))
val vaddr = Input(UInt(p.xlen.W)) val req = Input(new TlbReq(p))
val isStore = Input(Bool()) val resp = Output(new TlbResp(p))
val paddr = Output(UInt(p.xlen.W)) val ptwMemReq = Output(new PtwMemReq(p))
val pageFault = Output(Bool()) val ptwMemResp = Input(new PtwMemResp(p))
val refill = Output(new TlbRefill(p))
}) })
io.paddr := io.vaddr val bare = io.satp(63, 60) === 0.U
io.pageFault := false.B val walker = Module(new PageTableWalker(p))
} walker.io.reqValid := io.req.valid && !bare
walker.io.reqVpn := io.req.vaddr(38, 12)
walker.io.isStore := io.req.isStore
walker.io.isFetch := io.req.isFetch
walker.io.satp := io.satp
walker.io.memResp := io.ptwMemResp
io.ptwMemReq := walker.io.memReq
io.refill := walker.io.refill
io.resp.hit := bare
io.resp.miss := io.req.valid && !bare && !walker.io.respValid
io.resp.paddr := io.req.vaddr
io.resp.pageFault := walker.io.respValid && walker.io.pageFault
io.resp.accessFault := false.B
}

5
src/main/scala/memory/MemStage.scala
View File

@@ -4,17 +4,20 @@ class MemStage(p: CoreParams = CoreParams()) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val reqValid = Input(Bool()) val reqValid = Input(Bool())
val req = Input(new MemRequest(p)) val req = Input(new MemRequest(p))
val satp = Input(UInt(p.xlen.W))
val dmemReqValid = Output(Bool()) val dmemReqValid = Output(Bool())
val dmemReq = Output(new MemRequest(p)) val dmemReq = Output(new MemRequest(p))
val dmemRespValid = Input(Bool()) val dmemRespValid = Input(Bool())
val dmemRespData = Input(UInt(p.xlen.W)) val dmemRespData = Input(UInt(p.xlen.W))
val respValid = Output(Bool()) val respValid = Output(Bool())
val respData = Output(UInt(p.xlen.W)) val respData = Output(UInt(p.xlen.W))
val pageFault = Output(Bool())
}) })
val lsu = Module(new LSU(p)) val lsu = Module(new LSU(p))
lsu.io.reqValid := io.reqValid lsu.io.reqValid := io.reqValid
lsu.io.req := io.req lsu.io.req := io.req
lsu.io.satp := io.satp
lsu.io.dmemRespValid := io.dmemRespValid lsu.io.dmemRespValid := io.dmemRespValid
lsu.io.dmemRespData := io.dmemRespData lsu.io.dmemRespData := io.dmemRespData
@@ -22,5 +25,5 @@ class MemStage(p: CoreParams = CoreParams()) extends Module {
io.dmemReq := lsu.io.dmemReq io.dmemReq := lsu.io.dmemReq
io.respValid := lsu.io.respValid io.respValid := lsu.io.respValid
io.respData := lsu.io.respData io.respData := lsu.io.respData
io.pageFault := lsu.io.pageFault
} }

87
src/main/scala/memory/StoreQueue.scala
View File

@@ -2,23 +2,94 @@ import chisel3._
import chisel3.util._ import chisel3.util._
class StoreQueue(p: CoreParams = CoreParams()) extends Module { class StoreQueue(p: CoreParams = CoreParams()) extends Module {
private val idxBits = log2Ceil(p.storeQueueEntries)
private val robBits = log2Ceil(p.robEntries)
val io = IO(new Bundle { val io = IO(new Bundle {
val enqValid = Input(Bool()) val enqValid = Input(Bool())
val enq = Input(new MemRequest(p)) val enqRobIdx = Input(UInt(robBits.W))
val enqReady = Output(Bool()) val enqReady = Output(Bool())
val enqIdx = Output(UInt(idxBits.W))
val writeAddr = Input(Bool())
val writeData = Input(Bool())
val writeIdx = Input(UInt(idxBits.W))
val addr = Input(UInt(p.xlen.W))
val data = Input(UInt(p.xlen.W))
val size = Input(UInt(3.W))
val loadAddr = Input(UInt(p.xlen.W))
val loadSize = Input(UInt(3.W))
val loadRobIdx = Input(UInt(robBits.W))
val forwardValid = Output(Bool())
val forwardData = Output(UInt(p.xlen.W))
val commitValid = Input(Bool())
val commitRobIdx = Input(UInt(robBits.W))
val drainValid = Output(Bool()) val drainValid = Output(Bool())
val drain = Output(new MemRequest(p)) val drain = Output(new MemRequest(p))
val drainReady = Input(Bool()) val drainReady = Input(Bool())
val flush = Input(Bool()) val flush = Input(Bool())
}) })
val q = Module(new Queue(new MemRequest(p), p.storeQueueEntries)) val entries = RegInit(VecInit(Seq.fill(p.storeQueueEntries)(0.U.asTypeOf(new StoreQueueEntry(p)))))
q.io.enq.valid := io.enqValid && !io.flush val freeMask = VecInit(entries.map(e => !e.valid)).asUInt
q.io.enq.bits := io.enq val enqOH = PriorityEncoderOH(freeMask)
q.io.deq.ready := io.drainReady || io.flush val enqIdx = OHToUInt(enqOH)
io.enqReady := q.io.enq.ready def sameWord(a: UInt, b: UInt): Bool = a(p.xlen - 1, 3) === b(p.xlen - 1, 3)
io.drainValid := q.io.deq.valid && !io.flush
io.drain := q.io.deq.bits io.enqReady := freeMask.orR
io.enqIdx := enqIdx
val forwardVec = Wire(Vec(p.storeQueueEntries, Bool()))
for (i <- 0 until p.storeQueueEntries) {
forwardVec(i) := entries(i).valid && entries(i).addrValid && entries(i).dataValid &&
entries(i).robIdx < io.loadRobIdx && sameWord(entries(i).addr, io.loadAddr)
} }
io.forwardValid := forwardVec.asUInt.orR
io.forwardData := Mux1H(forwardVec, entries.map(_.data))
val drainVec = Wire(Vec(p.storeQueueEntries, Bool()))
for (i <- 0 until p.storeQueueEntries) {
drainVec(i) := entries(i).valid && entries(i).committed && entries(i).addrValid && entries(i).dataValid
}
val drainOH = PriorityEncoderOH(drainVec.asUInt)
val drainIdx = OHToUInt(drainOH)
io.drainValid := drainVec.asUInt.orR
io.drain.addr := entries(drainIdx).addr
io.drain.data := entries(drainIdx).data
io.drain.isStore := true.B
io.drain.size := entries(drainIdx).size
when(io.flush) {
entries.foreach(_ := 0.U.asTypeOf(new StoreQueueEntry(p)))
}.otherwise {
when(io.enqValid && io.enqReady) {
entries(enqIdx).valid := true.B
entries(enqIdx).robIdx := io.enqRobIdx
entries(enqIdx).addrValid := false.B
entries(enqIdx).dataValid := false.B
entries(enqIdx).committed := false.B
}
when(io.writeAddr) {
entries(io.writeIdx).addrValid := true.B
entries(io.writeIdx).addr := io.addr
entries(io.writeIdx).size := io.size
}
when(io.writeData) {
entries(io.writeIdx).dataValid := true.B
entries(io.writeIdx).data := io.data
}
when(io.commitValid) {
for (i <- 0 until p.storeQueueEntries) {
when(entries(i).valid && entries(i).robIdx === io.commitRobIdx) {
entries(i).committed := true.B
}
}
}
when(io.drainValid && io.drainReady) {
entries(drainIdx).valid := false.B
}
}
}

57
src/main/scala/rename/FreeList.scala
View File

@@ -4,23 +4,50 @@ import chisel3.util._
class FreeList(p: CoreParams = CoreParams()) extends Module { class FreeList(p: CoreParams = CoreParams()) extends Module {
private val physBits = log2Ceil(p.physRegs) private val physBits = log2Ceil(p.physRegs)
val io = IO(new Bundle { val io = IO(new Bundle {
val alloc = Input(Bool()) val allocReq = Input(Vec(p.issueWidth, Bool()))
val allocPhys = Output(UInt(physBits.W)) val allocPhys = Output(Vec(p.issueWidth, UInt(physBits.W)))
val canAlloc = Output(Bool()) val allocValid = Output(Vec(p.issueWidth, Bool()))
val free = Input(Bool()) val canAllocate = Output(Bool())
val freePhys = Input(UInt(physBits.W)) val freeReq = Input(Vec(p.issueWidth, Bool()))
val freePhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
val recover = Input(Bool())
val committedPhys = Input(Vec(p.archRegs, UInt(physBits.W)))
}) })
val freeBits = RegInit(VecInit((0 until p.physRegs).map(i => (i >= p.archRegs).B))) val freeBits = RegInit(VecInit((0 until p.physRegs).map(i => (i >= p.archRegs).B)))
val chosen = PriorityEncoder(freeBits) val freeMask = freeBits.asUInt
io.canAlloc := freeBits.asUInt.orR val firstOH = PriorityEncoderOH(freeMask)
io.allocPhys := chosen val secondMask = freeMask & ~firstOH
val secondOH = PriorityEncoderOH(secondMask)
val freeCount = PopCount(freeMask)
dontTouch(freeMask)
dontTouch(freeCount)
when(io.alloc && io.canAlloc) { io.canAllocate := freeCount >= p.issueWidth.U
freeBits(chosen) := false.B io.allocPhys(0) := OHToUInt(firstOH)
} io.allocPhys(1) := OHToUInt(secondOH)
when(io.free && io.freePhys >= p.archRegs.U) { io.allocValid(0) := io.allocReq(0) && freeMask.orR
freeBits(io.freePhys) := true.B io.allocValid(1) := io.allocReq(1) && secondMask.orR
}
}
val nextFree = Wire(Vec(p.physRegs, Bool()))
nextFree := freeBits
when(io.allocReq(0) && io.allocValid(0)) {
nextFree(io.allocPhys(0)) := false.B
}
when(io.allocReq(1) && io.allocValid(1)) {
nextFree(io.allocPhys(1)) := false.B
}
for (i <- 0 until p.issueWidth) {
when(io.freeReq(i) && io.freePhys(i) =/= 0.U) {
nextFree(io.freePhys(i)) := true.B
}
}
when(io.recover) {
for (i <- 0 until p.physRegs) {
val isCommitted = io.committedPhys.map(_ === i.U).foldLeft(false.B)(_ || _)
freeBits(i) := !isCommitted
}
}.otherwise {
freeBits := nextFree
}
}

183
src/main/scala/rename/ROB.scala
View File

@@ -3,69 +3,184 @@ import chisel3.util._
class RobEntry(p: CoreParams = CoreParams()) extends Bundle { class RobEntry(p: CoreParams = CoreParams()) extends Bundle {
val valid = Bool() val valid = Bool()
val robIdx = UInt(log2Ceil(p.robEntries).W)
val pc = UInt(p.xlen.W) val pc = UInt(p.xlen.W)
val archDest = UInt(5.W)
val writesDest = Bool()
val opClass = UInt(Consts.OpClassWidth.W) val opClass = UInt(Consts.OpClassWidth.W)
val dest = UInt(log2Ceil(p.physRegs).W) val dest = UInt(log2Ceil(p.physRegs).W)
val oldDest = UInt(log2Ceil(p.physRegs).W) val oldDest = UInt(log2Ceil(p.physRegs).W)
val completed = Bool() val completed = Bool()
val exception = Bool() val exception = Bool()
val exceptionCause = UInt(p.xlen.W)
val badAddr = UInt(p.xlen.W)
val branchMispredict = Bool() val branchMispredict = Bool()
val redirectPc = UInt(p.xlen.W)
val csrValid = Bool()
val csrAddr = UInt(12.W)
val csrCmd = UInt(3.W)
val csrRs1 = UInt(p.xlen.W)
val csrZimm = UInt(5.W)
} }
class ROB(p: CoreParams = CoreParams()) extends Module { class ROB(p: CoreParams = CoreParams()) extends Module {
private val idxBits = log2Ceil(p.robEntries) private val idxBits = log2Ceil(p.robEntries)
val io = IO(new Bundle { val io = IO(new Bundle {
val allocate = Input(Bool()) val allocateValid = Input(Vec(p.issueWidth, Bool()))
val allocatePc = Input(UInt(p.xlen.W)) val allocateEntry = Input(Vec(p.issueWidth, new RobEntry(p)))
val allocateClass = Input(UInt(Consts.OpClassWidth.W)) val allocateIdx = Output(Vec(p.issueWidth, UInt(idxBits.W)))
val allocateDest = Input(UInt(log2Ceil(p.physRegs).W))
val allocateOldDest = Input(UInt(log2Ceil(p.physRegs).W))
val allocateIdx = Output(UInt(idxBits.W))
val canAllocate = Output(Bool()) val canAllocate = Output(Bool())
val complete = Input(Bool()) val completeValid = Input(Vec(p.issueWidth, Bool()))
val completeIdx = Input(UInt(idxBits.W)) val completeIdx = Input(Vec(p.issueWidth, UInt(idxBits.W)))
val commitValid = Output(Bool()) val completeException = Input(Vec(p.issueWidth, Bool()))
val commit = Output(new RobEntry(p)) val completeCause = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
val commitReady = Input(Bool()) val completeBadAddr = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
val completeMispredict = Input(Vec(p.issueWidth, Bool()))
val completeRedirectPc = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
val completeCsrValid = Input(Vec(p.issueWidth, Bool()))
val completeCsrAddr = Input(Vec(p.issueWidth, UInt(12.W)))
val completeCsrCmd = Input(Vec(p.issueWidth, UInt(3.W)))
val completeCsrRs1 = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
val completeCsrZimm = Input(Vec(p.issueWidth, UInt(5.W)))
val commitValid = Output(Vec(p.issueWidth, Bool()))
val commit = Output(Vec(p.issueWidth, new RobEntry(p)))
val commitReady = Input(Vec(p.issueWidth, Bool()))
val flush = Input(Bool()) val flush = Input(Bool())
val empty = Output(Bool())
}) })
val entries = RegInit(VecInit(Seq.fill(p.robEntries)(0.U.asTypeOf(new RobEntry(p))))) val entries = RegInit(VecInit(Seq.fill(p.robEntries)(0.U.asTypeOf(new RobEntry(p)))))
val valid = RegInit(VecInit(Seq.fill(p.robEntries)(false.B)))
val completed = RegInit(VecInit(Seq.fill(p.robEntries)(false.B)))
val exception = RegInit(VecInit(Seq.fill(p.robEntries)(false.B)))
val exceptionCause = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(p.xlen.W))))
val badAddr = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(p.xlen.W))))
val branchMispredict = RegInit(VecInit(Seq.fill(p.robEntries)(false.B)))
val redirectPc = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(p.xlen.W))))
val csrValid = RegInit(VecInit(Seq.fill(p.robEntries)(false.B)))
val csrAddr = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(12.W))))
val csrCmd = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(3.W))))
val csrRs1 = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(p.xlen.W))))
val csrZimm = RegInit(VecInit(Seq.fill(p.robEntries)(0.U(5.W))))
val head = RegInit(0.U(idxBits.W)) val head = RegInit(0.U(idxBits.W))
val tail = RegInit(0.U(idxBits.W)) val tail = RegInit(0.U(idxBits.W))
val count = RegInit(0.U(log2Ceil(p.robEntries + 1).W)) val count = RegInit(0.U(log2Ceil(p.robEntries + 1).W))
val allocCount = PopCount(io.allocateValid)
io.canAllocate := count =/= p.robEntries.U val head0 = head
io.allocateIdx := tail val head1 = head + 1.U
io.commit := entries(head) val tail0 = tail
io.commitValid := count =/= 0.U && entries(head).valid && entries(head).completed val tail1 = tail + 1.U
val headEntry0 = Wire(new RobEntry(p))
val headEntry1 = Wire(new RobEntry(p))
headEntry0 := entries(head0)
headEntry0.valid := valid(head0)
headEntry0.completed := completed(head0)
headEntry0.exception := exception(head0)
headEntry0.exceptionCause := exceptionCause(head0)
headEntry0.badAddr := badAddr(head0)
headEntry0.branchMispredict := branchMispredict(head0)
headEntry0.redirectPc := redirectPc(head0)
headEntry0.csrValid := csrValid(head0)
headEntry0.csrAddr := csrAddr(head0)
headEntry0.csrCmd := csrCmd(head0)
headEntry0.csrRs1 := csrRs1(head0)
headEntry0.csrZimm := csrZimm(head0)
headEntry1 := entries(head1)
headEntry1.valid := valid(head1)
headEntry1.completed := completed(head1)
headEntry1.exception := exception(head1)
headEntry1.exceptionCause := exceptionCause(head1)
headEntry1.badAddr := badAddr(head1)
headEntry1.branchMispredict := branchMispredict(head1)
headEntry1.redirectPc := redirectPc(head1)
headEntry1.csrValid := csrValid(head1)
headEntry1.csrAddr := csrAddr(head1)
headEntry1.csrCmd := csrCmd(head1)
headEntry1.csrRs1 := csrRs1(head1)
headEntry1.csrZimm := csrZimm(head1)
io.empty := count === 0.U
io.canAllocate := (p.robEntries.U - count) >= p.issueWidth.U
io.allocateIdx(0) := tail0
io.allocateIdx(1) := tail1
io.commit(0) := headEntry0
io.commit(1) := headEntry1
io.commitValid(0) := count =/= 0.U && valid(head0) && completed(head0)
io.commitValid(1) := count > 1.U && io.commitValid(0) && !headEntry0.exception &&
!headEntry0.branchMispredict && valid(head1) && completed(head1)
when(io.flush) { when(io.flush) {
entries.foreach(_.valid := false.B) valid := VecInit(Seq.fill(p.robEntries)(false.B))
completed := VecInit(Seq.fill(p.robEntries)(false.B))
exception := VecInit(Seq.fill(p.robEntries)(false.B))
branchMispredict := VecInit(Seq.fill(p.robEntries)(false.B))
csrValid := VecInit(Seq.fill(p.robEntries)(false.B))
head := 0.U head := 0.U
tail := 0.U tail := 0.U
count := 0.U count := 0.U
}.otherwise { }.otherwise {
when(io.allocate && io.canAllocate) { when(io.allocateValid(0) && io.canAllocate) {
entries(tail).valid := true.B entries(tail0) := io.allocateEntry(0)
entries(tail).pc := io.allocatePc entries(tail0).robIdx := tail0
entries(tail).opClass := io.allocateClass valid(tail0) := true.B
entries(tail).dest := io.allocateDest completed(tail0) := false.B
entries(tail).oldDest := io.allocateOldDest exception(tail0) := false.B
entries(tail).completed := false.B exceptionCause(tail0) := 0.U
entries(tail).exception := false.B badAddr(tail0) := 0.U
entries(tail).branchMispredict := false.B branchMispredict(tail0) := false.B
tail := tail + 1.U redirectPc(tail0) := 0.U
count := count + 1.U csrValid(tail0) := false.B
csrAddr(tail0) := 0.U
csrCmd(tail0) := 0.U
csrRs1(tail0) := 0.U
csrZimm(tail0) := 0.U
} }
when(io.complete) { when(io.allocateValid(1) && io.canAllocate) {
entries(io.completeIdx).completed := true.B entries(tail1) := io.allocateEntry(1)
} entries(tail1).robIdx := tail1
when(io.commitValid && io.commitReady) { valid(tail1) := true.B
entries(head).valid := false.B completed(tail1) := false.B
head := head + 1.U exception(tail1) := false.B
count := count - 1.U exceptionCause(tail1) := 0.U
badAddr(tail1) := 0.U
branchMispredict(tail1) := false.B
redirectPc(tail1) := 0.U
csrValid(tail1) := false.B
csrAddr(tail1) := 0.U
csrCmd(tail1) := 0.U
csrRs1(tail1) := 0.U
csrZimm(tail1) := 0.U
} }
for (i <- 0 until p.issueWidth) {
when(io.completeValid(i)) {
completed(io.completeIdx(i)) := true.B
exception(io.completeIdx(i)) := io.completeException(i)
exceptionCause(io.completeIdx(i)) := io.completeCause(i)
badAddr(io.completeIdx(i)) := io.completeBadAddr(i)
branchMispredict(io.completeIdx(i)) := io.completeMispredict(i)
redirectPc(io.completeIdx(i)) := io.completeRedirectPc(i)
csrValid(io.completeIdx(i)) := io.completeCsrValid(i)
csrAddr(io.completeIdx(i)) := io.completeCsrAddr(i)
csrCmd(io.completeIdx(i)) := io.completeCsrCmd(i)
csrRs1(io.completeIdx(i)) := io.completeCsrRs1(i)
csrZimm(io.completeIdx(i)) := io.completeCsrZimm(i)
} }
} }
val commit0 = io.commitValid(0) && io.commitReady(0)
val commit1 = io.commitValid(1) && io.commitReady(1)
when(commit0) { valid(head0) := false.B }
when(commit1) { valid(head1) := false.B }
val committed = PopCount(VecInit(Seq(commit0, commit1)))
val allocated = Mux(io.canAllocate, allocCount, 0.U)
head := head + committed
tail := tail + allocated
count := count + allocated - committed
when(!commit0 && !commit1 && allocated === 0.U) {
head := head
tail := tail
count := count
}
}
}

163
src/main/scala/rename/RenameStage.scala
View File

@@ -2,13 +2,43 @@ import chisel3._
import chisel3.util._ import chisel3.util._
class RenameStage(p: CoreParams = CoreParams()) extends Module { class RenameStage(p: CoreParams = CoreParams()) extends Module {
private val physBits = log2Ceil(p.physRegs)
private val robBits = log2Ceil(p.robEntries)
val io = IO(new Bundle { val io = IO(new Bundle {
val inValid = Input(Bool()) val inValid = Input(Vec(p.issueWidth, Bool()))
val in = Input(new DecodedInst(p)) val in = Input(Vec(p.issueWidth, new DecodedInst(p)))
val outValid = Output(Bool()) val outValid = Output(Vec(p.issueWidth, Bool()))
val out = Output(new RenamePacket(p)) val out = Output(Vec(p.issueWidth, new RenamePacket(p)))
val commitFree = Input(Bool()) val canAccept = Output(Bool())
val commitOldPhys = Input(UInt(log2Ceil(p.physRegs).W))
val wbValid = Input(Vec(p.issueWidth, Bool()))
val wbPhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
val completeValid = Input(Vec(p.issueWidth, Bool()))
val completeIdx = Input(Vec(p.issueWidth, UInt(robBits.W)))
val completeException = Input(Vec(p.issueWidth, Bool()))
val completeCause = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
val completeBadAddr = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
val completeMispredict = Input(Vec(p.issueWidth, Bool()))
val completeRedirectPc = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
val completeCsrValid = Input(Vec(p.issueWidth, Bool()))
val completeCsrAddr = Input(Vec(p.issueWidth, UInt(12.W)))
val completeCsrCmd = Input(Vec(p.issueWidth, UInt(3.W)))
val completeCsrRs1 = Input(Vec(p.issueWidth, UInt(p.xlen.W)))
val completeCsrZimm = Input(Vec(p.issueWidth, UInt(5.W)))
val commitReady = Input(Vec(p.issueWidth, Bool()))
val commitValid = Output(Vec(p.issueWidth, Bool()))
val commitEntry = Output(Vec(p.issueWidth, new RobEntry(p)))
val robEmpty = Output(Bool())
val commitMapValid = Input(Vec(p.issueWidth, Bool()))
val commitArch = Input(Vec(p.issueWidth, UInt(5.W)))
val commitPhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
val commitFreeOld = Input(Vec(p.issueWidth, Bool()))
val commitOldPhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
val flush = Input(Bool()) val flush = Input(Bool())
}) })
@@ -16,34 +46,97 @@ class RenameStage(p: CoreParams = CoreParams()) extends Module {
val freeList = Module(new FreeList(p)) val freeList = Module(new FreeList(p))
val rob = Module(new ROB(p)) val rob = Module(new ROB(p))
table.io.rs1 := io.in.rs1 val needsPhys = Wire(Vec(p.issueWidth, Bool()))
table.io.rs2 := io.in.rs2 for (i <- 0 until p.issueWidth) {
table.io.rd := io.in.rd needsPhys(i) := io.inValid(i) && io.in(i).writesRd
table.io.newPhys := freeList.io.allocPhys
table.io.wen := io.inValid && io.in.writesRd && freeList.io.canAlloc && rob.io.canAllocate
table.io.recover := io.flush
freeList.io.alloc := table.io.wen
freeList.io.free := io.commitFree
freeList.io.freePhys := io.commitOldPhys
rob.io.allocate := io.inValid && rob.io.canAllocate && (!io.in.writesRd || freeList.io.canAlloc)
rob.io.allocatePc := io.in.pc
rob.io.allocateClass := io.in.opClass
rob.io.allocateDest := Mux(io.in.writesRd, freeList.io.allocPhys, table.io.oldPrd)
rob.io.allocateOldDest := table.io.oldPrd
rob.io.complete := false.B
rob.io.completeIdx := 0.U
rob.io.commitReady := false.B
rob.io.flush := io.flush
io.outValid := rob.io.allocate
io.out.valid := io.outValid
io.out.decoded := io.in
io.out.prs1 := table.io.prs1
io.out.prs2 := table.io.prs2
io.out.prd := Mux(io.in.writesRd, freeList.io.allocPhys, table.io.oldPrd)
io.out.oldPrd := table.io.oldPrd
io.out.robIdx := rob.io.allocateIdx
} }
table.io.rs1 := VecInit(io.in.map(_.rs1))
table.io.rs2 := VecInit(io.in.map(_.rs2))
table.io.rd := VecInit(io.in.map(_.rd))
table.io.newPhys := freeList.io.allocPhys
table.io.wen := VecInit((0 until p.issueWidth).map(i => io.outValid(i) && io.in(i).writesRd))
table.io.commitWen := io.commitMapValid
table.io.commitRd := io.commitArch
table.io.commitPhys := io.commitPhys
table.io.recover := io.flush
freeList.io.allocReq := needsPhys
freeList.io.freeReq := io.commitFreeOld
freeList.io.freePhys := io.commitOldPhys
freeList.io.recover := io.flush
freeList.io.committedPhys := table.io.committedPhys
val requested = PopCount(io.inValid)
val canRename = freeList.io.canAllocate && rob.io.canAllocate
io.canAccept := canRename
val readyReg = RegInit(VecInit(Seq.fill(p.physRegs)(true.B)))
when(io.flush) {
readyReg := VecInit(Seq.fill(p.physRegs)(true.B))
}.otherwise {
for (i <- 0 until p.issueWidth) {
when(io.wbValid(i)) {
readyReg(io.wbPhys(i)) := true.B
}
when(io.outValid(i) && io.in(i).writesRd) {
readyReg(freeList.io.allocPhys(i)) := false.B
}
}
}
rob.io.allocateValid := VecInit((0 until p.issueWidth).map(i => io.inValid(i) && canRename))
for (i <- 0 until p.issueWidth) {
val e = WireDefault(0.U.asTypeOf(new RobEntry(p)))
e.valid := io.inValid(i) && canRename
e.pc := io.in(i).pc
e.archDest := io.in(i).rd
e.writesDest := io.in(i).writesRd
e.opClass := io.in(i).opClass
e.dest := Mux(io.in(i).writesRd, freeList.io.allocPhys(i), table.io.oldPrd(i))
e.oldDest := table.io.oldPrd(i)
rob.io.allocateEntry(i) := e
}
rob.io.completeValid := io.completeValid
rob.io.completeIdx := io.completeIdx
rob.io.completeException := io.completeException
rob.io.completeCause := io.completeCause
rob.io.completeBadAddr := io.completeBadAddr
rob.io.completeMispredict := io.completeMispredict
rob.io.completeRedirectPc := io.completeRedirectPc
rob.io.completeCsrValid := io.completeCsrValid
rob.io.completeCsrAddr := io.completeCsrAddr
rob.io.completeCsrCmd := io.completeCsrCmd
rob.io.completeCsrRs1 := io.completeCsrRs1
rob.io.completeCsrZimm := io.completeCsrZimm
rob.io.commitReady := io.commitReady
rob.io.flush := io.flush
io.commitValid := rob.io.commitValid
io.commitEntry := rob.io.commit
io.robEmpty := rob.io.empty
for (i <- 0 until p.issueWidth) {
val src1FromOlder = (0 until i).map(j =>
io.outValid(j) && io.in(j).writesRd && io.in(j).rd =/= 0.U && io.in(j).rd === io.in(i).rs1
).foldLeft(false.B)(_ || _)
val src2FromOlder = (0 until i).map(j =>
io.outValid(j) && io.in(j).writesRd && io.in(j).rd =/= 0.U && io.in(j).rd === io.in(i).rs2
).foldLeft(false.B)(_ || _)
io.outValid(i) := io.inValid(i) && canRename
io.out(i).valid := io.outValid(i)
io.out(i).decoded := io.in(i)
io.out(i).prs1 := table.io.prs1(i)
io.out(i).prs2 := table.io.prs2(i)
io.out(i).src1Ready := io.in(i).rs1 === 0.U || (!src1FromOlder && readyReg(table.io.prs1(i)))
io.out(i).src2Ready := io.in(i).rs2 === 0.U || (!src2FromOlder && readyReg(table.io.prs2(i)))
io.out(i).prd := Mux(io.in(i).writesRd, freeList.io.allocPhys(i), table.io.oldPrd(i))
io.out(i).oldPrd := table.io.oldPrd(i)
io.out(i).robIdx := rob.io.allocateIdx(i)
}
when(requested === 0.U) {
io.canAccept := true.B
}
}

44
src/main/scala/rename/RenameTable.scala
View File

@@ -4,29 +4,45 @@ import chisel3.util._
class RenameTable(p: CoreParams = CoreParams()) extends Module { class RenameTable(p: CoreParams = CoreParams()) extends Module {
private val physBits = log2Ceil(p.physRegs) private val physBits = log2Ceil(p.physRegs)
val io = IO(new Bundle { val io = IO(new Bundle {
val rs1 = Input(UInt(5.W)) val rs1 = Input(Vec(p.issueWidth, UInt(5.W)))
val rs2 = Input(UInt(5.W)) val rs2 = Input(Vec(p.issueWidth, UInt(5.W)))
val rd = Input(UInt(5.W)) val rd = Input(Vec(p.issueWidth, UInt(5.W)))
val newPhys = Input(UInt(physBits.W)) val newPhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
val wen = Input(Bool()) val wen = Input(Vec(p.issueWidth, Bool()))
val prs1 = Output(UInt(physBits.W)) val prs1 = Output(Vec(p.issueWidth, UInt(physBits.W)))
val prs2 = Output(UInt(physBits.W)) val prs2 = Output(Vec(p.issueWidth, UInt(physBits.W)))
val oldPrd = Output(UInt(physBits.W)) val oldPrd = Output(Vec(p.issueWidth, UInt(physBits.W)))
val commitWen = Input(Vec(p.issueWidth, Bool()))
val commitRd = Input(Vec(p.issueWidth, UInt(5.W)))
val commitPhys = Input(Vec(p.issueWidth, UInt(physBits.W)))
val recover = Input(Bool()) val recover = Input(Bool())
val committedPhys = Output(Vec(p.archRegs, UInt(physBits.W)))
}) })
val init = VecInit((0 until p.archRegs).map(_.U(physBits.W))) val init = VecInit((0 until p.archRegs).map(_.U(physBits.W)))
val speculative = RegInit(init) val speculative = RegInit(init)
val committed = RegInit(init) val committed = RegInit(init)
io.committedPhys := committed
io.prs1 := speculative(io.rs1) io.prs1(0) := speculative(io.rs1(0))
io.prs2 := speculative(io.rs2) io.prs2(0) := speculative(io.rs2(0))
io.oldPrd := speculative(io.rd) io.oldPrd(0) := speculative(io.rd(0))
val slot0Writes = io.wen(0) && io.rd(0) =/= 0.U
io.prs1(1) := Mux(slot0Writes && io.rd(0) === io.rs1(1), io.newPhys(0), speculative(io.rs1(1)))
io.prs2(1) := Mux(slot0Writes && io.rd(0) === io.rs2(1), io.newPhys(0), speculative(io.rs2(1)))
io.oldPrd(1) := Mux(slot0Writes && io.rd(0) === io.rd(1), io.newPhys(0), speculative(io.rd(1)))
when(io.recover) { when(io.recover) {
speculative := committed speculative := committed
}.elsewhen(io.wen && io.rd =/= 0.U) { }.otherwise {
speculative(io.rd) := io.newPhys for (i <- 0 until p.issueWidth) {
when(io.wen(i) && io.rd(i) =/= 0.U) {
speculative(io.rd(i)) := io.newPhys(i)
}
when(io.commitWen(i) && io.commitRd(i) =/= 0.U) {
committed(io.commitRd(i)) := io.commitPhys(i)
}
}
} }
} }