28 lines
669 B
Systemverilog
28 lines
669 B
Systemverilog
// Generated by CIRCT firtool-1.139.0
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// VCS coverage exclude_file
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module data_1024x256(
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input [9:0] R0_addr,
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input R0_en,
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R0_clk,
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output [255:0] R0_data,
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input [9:0] W0_addr,
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input W0_en,
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W0_clk,
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input [255:0] W0_data
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);
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reg [255:0] Memory[0:1023];
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reg _R0_en_d0;
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reg [9:0] _R0_addr_d0;
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always @(posedge R0_clk) begin
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_R0_en_d0 <= R0_en;
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_R0_addr_d0 <= R0_addr;
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end // always @(posedge)
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always @(posedge W0_clk) begin
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if (W0_en)
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Memory[W0_addr] <= W0_data;
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end // always @(posedge)
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assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 256'bx;
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endmodule
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