63 lines
2.0 KiB
Systemverilog
63 lines
2.0 KiB
Systemverilog
// Generated by CIRCT firtool-1.139.0
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module Frontend(
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input clock,
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reset,
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io_redirectValid,
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input [63:0] io_redirectPc,
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output io_imemReqValid,
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output [63:0] io_imemReqAddr,
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input io_imemRespValid,
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input [31:0] io_imemRespBits_0,
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io_imemRespBits_1,
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input io_outReady,
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output io_outValid,
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output [63:0] io_out_pc,
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output [31:0] io_out_inst_0,
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io_out_inst_1,
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output io_out_laneValid_0,
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io_out_laneValid_1
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);
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wire _icache_io_respValid;
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wire [63:0] _icache_io_resp_pc;
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wire _icache_io_resp_laneValid_0;
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wire _icache_io_resp_laneValid_1;
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reg [63:0] pc;
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always @(posedge clock) begin
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if (reset)
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pc <= 64'h80000000;
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else if (io_redirectValid)
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pc <= io_redirectPc;
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else if (_icache_io_respValid & io_outReady)
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pc <=
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_icache_io_resp_pc
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+ {60'h0,
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{1'h0, _icache_io_resp_laneValid_0} + {1'h0, _icache_io_resp_laneValid_1},
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2'h0};
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end // always @(posedge)
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ICache icache (
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.clock (clock),
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.reset (reset),
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.io_reqAddr (pc),
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.io_reqPc (pc),
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.io_flush (io_redirectValid),
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.io_respReady (io_outReady),
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.io_memReqValid (io_imemReqValid),
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.io_memReqAddr (io_imemReqAddr),
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.io_memRespValid (io_imemRespValid),
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.io_memRespBits_0 (io_imemRespBits_0),
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.io_memRespBits_1 (io_imemRespBits_1),
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.io_respValid (_icache_io_respValid),
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.io_resp_pc (_icache_io_resp_pc),
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.io_resp_inst_0 (io_out_inst_0),
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.io_resp_inst_1 (io_out_inst_1),
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.io_resp_laneValid_0 (_icache_io_resp_laneValid_0),
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.io_resp_laneValid_1 (_icache_io_resp_laneValid_1)
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);
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assign io_outValid = _icache_io_respValid;
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assign io_out_pc = _icache_io_resp_pc;
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assign io_out_laneValid_0 = _icache_io_resp_laneValid_0;
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assign io_out_laneValid_1 = _icache_io_resp_laneValid_1;
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endmodule
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