261 lines
9.9 KiB
Systemverilog
261 lines
9.9 KiB
Systemverilog
// Generated by CIRCT firtool-1.139.0
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module CSRFile(
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input clock,
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reset,
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io_cmd_valid,
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input [11:0] io_cmd_addr,
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input [2:0] io_cmd_cmd,
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input [63:0] io_cmd_rs1,
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input [4:0] io_cmd_zimm,
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input [11:0] io_readAddr,
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output [63:0] io_rdata,
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input io_trap,
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input [63:0] io_trapPc,
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io_trapCause,
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output [63:0] io_satp,
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io_mtvec,
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io_mepc
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);
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reg [63:0] cycle;
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reg [63:0] mstatus;
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reg [63:0] mtvecReg;
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reg [63:0] mepcReg;
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reg [63:0] mcause;
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reg [63:0] mtval;
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reg [63:0] medeleg;
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reg [63:0] mideleg;
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reg [63:0] mie;
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reg [63:0] mip;
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reg [63:0] sstatus;
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reg [63:0] stvec;
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reg [63:0] sepc;
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reg [63:0] scause;
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reg [63:0] stval;
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reg [63:0] sscratch;
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reg [63:0] satpReg;
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always @(posedge clock) begin
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if (reset) begin
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cycle <= 64'h0;
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mstatus <= 64'h0;
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mtvecReg <= 64'h0;
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mepcReg <= 64'h0;
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mcause <= 64'h0;
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mtval <= 64'h0;
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medeleg <= 64'h0;
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mideleg <= 64'h0;
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mie <= 64'h0;
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mip <= 64'h0;
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sstatus <= 64'h0;
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stvec <= 64'h0;
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sepc <= 64'h0;
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scause <= 64'h0;
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stval <= 64'h0;
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sscratch <= 64'h0;
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satpReg <= 64'h0;
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end
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else begin
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automatic logic _GEN;
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automatic logic _GEN_0;
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automatic logic _GEN_1;
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automatic logic _GEN_2;
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automatic logic _GEN_3;
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automatic logic _GEN_4;
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automatic logic _GEN_5;
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automatic logic _GEN_6 = io_cmd_addr == 12'h343;
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automatic logic _GEN_7 = io_cmd_addr == 12'h344;
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automatic logic _GEN_8 = io_cmd_addr == 12'h100;
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automatic logic _GEN_9 = io_cmd_addr == 12'h105;
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automatic logic _GEN_10 = io_cmd_addr == 12'h140;
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automatic logic _GEN_11 = io_cmd_addr == 12'h141;
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automatic logic _GEN_12 = io_cmd_addr == 12'h142;
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automatic logic _GEN_13 = io_cmd_addr == 12'h143;
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automatic logic _GEN_14 = io_cmd_addr == 12'h180;
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automatic logic [63:0] _GEN_15;
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automatic logic [63:0] writeOld;
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automatic logic [63:0] operand;
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automatic logic [63:0] _next_T_1;
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automatic logic [63:0] _next_T_3;
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automatic logic [3:0][63:0] _GEN_16;
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automatic logic [63:0] next;
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automatic logic _GEN_17;
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_GEN = io_cmd_addr == 12'h300;
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_GEN_0 = io_cmd_addr == 12'h302;
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_GEN_1 = io_cmd_addr == 12'h303;
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_GEN_2 = io_cmd_addr == 12'h304;
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_GEN_3 = io_cmd_addr == 12'h305;
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_GEN_4 = io_cmd_addr == 12'h341;
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_GEN_5 = io_cmd_addr == 12'h342;
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_GEN_15 =
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io_cmd_addr == 12'h301
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? 64'h800000000014112D
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: _GEN_0
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? medeleg
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: _GEN_1
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? mideleg
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: _GEN_2
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? mie
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: _GEN_3
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? mtvecReg
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: _GEN_4
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? mepcReg
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: _GEN_5
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? mcause
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: _GEN_6
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? mtval
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: _GEN_7
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? mip
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: _GEN_8
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? sstatus
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: _GEN_9
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? stvec
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: _GEN_10
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? sscratch
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: _GEN_11
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? sepc
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: _GEN_12
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? scause
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: _GEN_13
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? stval
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: _GEN_14
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? satpReg
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: io_cmd_addr == 12'hF14
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| io_cmd_addr != 12'hC00
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? 64'h0
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: cycle;
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writeOld = _GEN ? mstatus : _GEN_15;
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operand = io_cmd_cmd[2] ? {59'h0, io_cmd_zimm} : io_cmd_rs1;
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_next_T_1 = writeOld | operand;
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_next_T_3 = writeOld & ~operand;
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_GEN_16 = {{_next_T_3}, {_next_T_1}, {operand}, {writeOld}};
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next = _GEN_16[io_cmd_cmd[1:0]];
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_GEN_17 = io_cmd_valid & (|io_cmd_cmd);
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cycle <= cycle + 64'h1;
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if (_GEN_17 & _GEN)
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mstatus <= next;
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | ~_GEN_3) begin
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end
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else
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mtvecReg <= next;
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if (io_trap) begin
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mepcReg <= io_trapPc;
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mcause <= io_trapCause;
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end
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else begin
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | ~_GEN_4) begin
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end
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else
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mepcReg <= next;
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | ~_GEN_5) begin
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end
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else
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mcause <= next;
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end
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5
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| ~_GEN_6) begin
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end
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else
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mtval <= next;
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if (~_GEN_17 | _GEN | ~_GEN_0) begin
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end
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else begin
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automatic logic [3:0][63:0] _GEN_18;
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_GEN_18 = {{_next_T_3}, {_next_T_1}, {operand}, {_GEN_15}};
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medeleg <= _GEN_18[io_cmd_cmd[1:0]];
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end
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if (~_GEN_17 | _GEN | _GEN_0 | ~_GEN_1) begin
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end
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else
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mideleg <= next;
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | ~_GEN_2) begin
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end
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else
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mie <= next;
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
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| ~_GEN_7) begin
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end
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else
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mip <= next;
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
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| _GEN_7 | ~_GEN_8) begin
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end
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else
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sstatus <= next;
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
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| _GEN_7 | _GEN_8 | ~_GEN_9) begin
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end
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else
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stvec <= next;
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
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| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | ~_GEN_11) begin
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end
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else
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sepc <= next;
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
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| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | ~_GEN_12) begin
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end
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else
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scause <= next;
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
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| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | _GEN_12 | ~_GEN_13) begin
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end
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else
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stval <= next;
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
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| _GEN_7 | _GEN_8 | _GEN_9 | ~_GEN_10) begin
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end
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else
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sscratch <= next;
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if (~_GEN_17 | _GEN | _GEN_0 | _GEN_1 | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6
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| _GEN_7 | _GEN_8 | _GEN_9 | _GEN_10 | _GEN_11 | _GEN_12 | _GEN_13
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| ~_GEN_14) begin
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end
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else
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satpReg <= next;
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end
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end // always @(posedge)
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assign io_rdata =
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io_readAddr == 12'h300
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? mstatus
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: io_readAddr == 12'h301
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? 64'h800000000014112D
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: io_readAddr == 12'h302
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? medeleg
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: io_readAddr == 12'h303
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? mideleg
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: io_readAddr == 12'h304
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? mie
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: io_readAddr == 12'h305
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? mtvecReg
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: io_readAddr == 12'h341
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? mepcReg
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: io_readAddr == 12'h342
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? mcause
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: io_readAddr == 12'h343
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? mtval
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: io_readAddr == 12'h344
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? mip
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: io_readAddr == 12'h100
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? sstatus
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: io_readAddr == 12'h105
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? stvec
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: io_readAddr == 12'h140
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? sscratch
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: io_readAddr == 12'h141
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? sepc
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: io_readAddr == 12'h142
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? scause
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: io_readAddr == 12'h143
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? stval
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: io_readAddr == 12'h180
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? satpReg
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: io_readAddr == 12'hF14
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| io_readAddr != 12'hC00
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? 64'h0
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: cycle;
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assign io_satp = satpReg;
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assign io_mtvec = mtvecReg;
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assign io_mepc = mepcReg;
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endmodule
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