84 lines
3.4 KiB
Systemverilog
84 lines
3.4 KiB
Systemverilog
// Generated by CIRCT firtool-1.139.0
|
|
module CommitStage(
|
|
input io_robValid_0,
|
|
io_robValid_1,
|
|
input [4:0] io_robEntry_0_archDest,
|
|
input io_robEntry_0_writesDest,
|
|
input [3:0] io_robEntry_0_opClass,
|
|
input [5:0] io_robEntry_0_dest,
|
|
io_robEntry_0_oldDest,
|
|
input io_robEntry_0_exception,
|
|
input [63:0] io_robEntry_0_exceptionCause,
|
|
io_robEntry_0_badAddr,
|
|
input io_robEntry_0_branchMispredict,
|
|
input [63:0] io_robEntry_0_redirectPc,
|
|
input io_robEntry_0_csrValid,
|
|
input [4:0] io_robEntry_1_archDest,
|
|
input io_robEntry_1_writesDest,
|
|
input [5:0] io_robEntry_1_dest,
|
|
io_robEntry_1_oldDest,
|
|
input io_robEntry_1_exception,
|
|
input [63:0] io_robEntry_1_exceptionCause,
|
|
io_robEntry_1_badAddr,
|
|
input io_robEntry_1_branchMispredict,
|
|
input [63:0] io_robEntry_1_redirectPc,
|
|
input io_robEntry_1_csrValid,
|
|
output io_commitReady_0,
|
|
io_commitReady_1,
|
|
io_freeOldPhys_0,
|
|
io_freeOldPhys_1,
|
|
output [5:0] io_oldPhys_0,
|
|
io_oldPhys_1,
|
|
output io_commitMapValid_0,
|
|
io_commitMapValid_1,
|
|
output [4:0] io_commitArch_0,
|
|
io_commitArch_1,
|
|
output [5:0] io_commitPhys_0,
|
|
io_commitPhys_1,
|
|
output io_flush,
|
|
output [63:0] io_redirectPc,
|
|
output io_exception,
|
|
output [63:0] io_exceptionCause,
|
|
io_badAddr
|
|
);
|
|
|
|
wire firstTrap =
|
|
io_robValid_0 & (io_robEntry_0_exception | io_robEntry_0_branchMispredict);
|
|
wire secondTrap =
|
|
io_robValid_1 & (io_robEntry_1_exception | io_robEntry_1_branchMispredict);
|
|
wire io_commitReady_1_0 =
|
|
io_robValid_1 & ~firstTrap & ~secondTrap
|
|
& ~(io_robValid_0 & io_robValid_1 & io_robEntry_0_csrValid & io_robEntry_1_csrValid)
|
|
& ~(io_robValid_0 & io_robEntry_0_opClass == 4'h4);
|
|
wire _io_commitMapValid_0_T = io_robValid_0 & io_robEntry_0_writesDest;
|
|
wire _io_commitMapValid_1_T = io_commitReady_1_0 & io_robEntry_1_writesDest;
|
|
wire secondTrapSelected = ~io_robValid_0 & secondTrap;
|
|
assign io_commitReady_0 = io_robValid_0;
|
|
assign io_commitReady_1 = io_commitReady_1_0;
|
|
assign io_freeOldPhys_0 =
|
|
_io_commitMapValid_0_T & io_robEntry_0_oldDest != io_robEntry_0_dest;
|
|
assign io_freeOldPhys_1 =
|
|
_io_commitMapValid_1_T & io_robEntry_1_oldDest != io_robEntry_1_dest;
|
|
assign io_oldPhys_0 = io_robEntry_0_oldDest;
|
|
assign io_oldPhys_1 = io_robEntry_1_oldDest;
|
|
assign io_commitMapValid_0 = _io_commitMapValid_0_T & (|io_robEntry_0_archDest);
|
|
assign io_commitMapValid_1 = _io_commitMapValid_1_T & (|io_robEntry_1_archDest);
|
|
assign io_commitArch_0 = io_robEntry_0_archDest;
|
|
assign io_commitArch_1 = io_robEntry_1_archDest;
|
|
assign io_commitPhys_0 = io_robEntry_0_dest;
|
|
assign io_commitPhys_1 = io_robEntry_1_dest;
|
|
assign io_flush = firstTrap | secondTrapSelected;
|
|
assign io_redirectPc = firstTrap ? io_robEntry_0_redirectPc : io_robEntry_1_redirectPc;
|
|
assign io_exception =
|
|
firstTrap ? io_robEntry_0_exception : secondTrapSelected & io_robEntry_1_exception;
|
|
assign io_exceptionCause =
|
|
firstTrap
|
|
? io_robEntry_0_exceptionCause
|
|
: secondTrapSelected ? io_robEntry_1_exceptionCause : 64'h0;
|
|
assign io_badAddr =
|
|
firstTrap
|
|
? io_robEntry_0_badAddr
|
|
: secondTrapSelected ? io_robEntry_1_badAddr : 64'h0;
|
|
endmodule
|
|
|