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Fixed incorrect miss_add on pipeline stall

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felsabbagh3
2020-03-31 20:23:09 -07:00
parent bca5ac5e7f
commit 1b9d9f3625
1 changed files with 1 additions and 1 deletions
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rtl/VX_cache/VX_bank.v
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@@ -524,7 +524,7 @@ module VX_bank
wire invalidate_fill;
// Enqueue to miss reserv if it's a valid miss
assign miss_add = valid_st2 && !is_snp_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full));
assign miss_add = valid_st2 && !is_snp_st2 && miss_st2 && !mrvq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
assign miss_add_pc = pc_st2;
assign miss_add_addr = addr_st2;
assign miss_add_data = writeword_st2;