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20f22c7446
scope minor fix
2020-11-22 11:51:46 -08:00
39f6f2999b
snp_forwarder fix
2020-11-22 06:55:45 -08:00
93fb036c4f
blackbox.sh update
2020-11-21 16:01:31 -08:00
736c822d06
merge
2020-11-21 12:36:05 -08:00
7ae770f4eb
config update
2020-11-21 12:27:42 -08:00
1795980a52
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
91fe3efa28
Update .travis.yml
2020-11-17 10:05:26 -05:00
cad321dd9e
Update .travis.yml
2020-11-17 08:35:04 -05:00
e0fe624b1d
Update .travis.yml
2020-11-17 07:33:05 -05:00
a7da36c007
minor update
2020-11-17 03:19:35 -08:00
c287b53e01
minor update
2020-11-17 02:26:49 -08:00
51cbda6b3f
minor update
2020-11-17 00:38:20 -08:00
34b650be94
fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug
2020-11-17 00:27:24 -08:00
3e1fe66d9e
minor update
2020-11-16 08:25:45 -08:00
61add25d96
minor fix
2020-11-16 08:23:16 -08:00
6e9c062f4c
minor fix
2020-11-16 04:23:30 -08:00
2234735cfb
constant integration updates
2020-11-16 03:55:55 -08:00
77bca2deca
constant integration updates
2020-11-16 02:39:53 -08:00
18ff70bc7f
constant integration updates
2020-11-16 01:23:03 -08:00
a1fcdd467a
reset networks optimization
2020-11-16 01:12:02 -08:00
1bc4b8e7a8
constant integration updates, cache bank incoming_fill optimization
2020-11-15 23:01:24 -08:00
2904f6441d
constant integration updates
2020-11-15 21:30:31 -08:00
60f5c15bc8
constant integration update
2020-11-15 23:27:02 -05:00
4c73382675
constant integration updates
2020-11-15 11:23:06 -08:00
e4d7a3deb4
constant integration updates
2020-11-15 10:28:32 -08:00
4337146fe9
constant integration updates
2020-11-15 09:18:44 -08:00
4d94d33e8d
constant integration updates
2020-11-15 09:12:48 -08:00
e946d976e7
constant integration updates
2020-11-15 08:44:57 -08:00
5d58bf3d11
fixed l3cache hang using memory arbiter in afu
2020-11-15 06:36:32 -08:00
2e0f51af80
fixed instr/cycle perf counter
2020-11-12 11:41:25 -08:00
fceb561cbd
synchronous reset network optimization: only reset register when required
2020-11-11 20:54:54 -08:00
ce95c40aee
fixed redundant cache fills
2020-11-11 12:07:27 -05:00
c39f98a8af
merge
2020-11-10 16:48:36 -05:00
d2bc820909
Merge branch 'master' of https://github.com/vortexgpgpu/vortex-dev
2020-11-10 14:01:58 -05:00
0bacfd2dae
minor update
2020-11-10 13:47:28 -05:00
c1f23cf3ad
fixed redundnat cache fill with dirty block, fixed cache tag_store critical path
2020-11-10 08:32:34 -08:00
725322807e
fixed DRAM response backpressure inside Cache
2020-11-10 05:24:57 -08:00
ed69be4027
pipeline optimization: fixed GPR fanout delay to execute unitsddddssssvcd
2020-11-09 21:41:06 -08:00
7c384eaf7f
fixed snoop forwarding hang
2020-11-09 20:02:33 -08:00
f8d54c6994
fixed cache_core_rsp_merge unit
2020-11-09 02:10:35 -08:00
203a184008
fixed bank_core_req_abr critical path
2020-11-08 18:25:32 -08:00
10505caae1
refactoring all arbiters with buffering for request count > 2, optimized the cache core response module in critical path when running as L2
2020-11-08 01:31:46 -08:00
b14007f930
pipeline optimization: fixed GPR fanout delay to execute units
2020-11-07 02:01:21 -08:00
af2bb3b789
cache fixes and opyimization - fmax moved from 162 mhz to 220 mhz!!!
2020-11-05 03:49:50 -08:00
4c6a74fa87
cache refactoring - phase 3 - added dedicated pipeline stage for tag access
2020-11-04 03:21:30 -08:00
cd8ce20bd6
minor improvement
2020-11-03 17:08:26 -08:00
323d2a3b3e
minor fix
2020-11-03 15:34:35 -08:00
ba81d76e02
cache refactoring - phase 2
2020-11-03 04:51:40 -08:00
4151ee197b
per_bank_miss added to VX_cache.v
2020-11-02 12:07:10 -05:00
40a9fd3aaf
miss output vector added to cache.v and bank.v
2020-11-02 12:02:54 -05:00
e6a8df7be1
miss vec is displayed
2020-11-02 12:01:03 -05:00
5be1d85648
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
3fe31fc337
fixed afu to cpu mempcy hang
2020-10-28 14:19:13 -07:00
9a9f7955f0
basic test timing + scope tracing ccip
2020-10-27 17:04:04 -04:00
4bd5ee2673
fixed rtlsim regression
2020-10-26 12:59:58 -04:00
d319ae3b97
minor rupdate
2020-10-26 05:27:10 -04:00
09b1c0eea7
minor update
2020-10-26 02:02:05 -07:00
48897d9778
minor update
2020-10-25 18:29:25 -07:00
43ae82e788
vlsim fix, verilator fst trace, use ram optimization
2020-10-25 16:40:50 -07:00
81dc8c7279
minor update
2020-10-20 16:47:01 -04:00
e9d1754990
Merge branch 'master' of https://github.com/vortexgpgpu/vortex-dev
2020-10-20 11:49:35 -04:00
e6466b887c
minor update
2020-10-20 08:45:21 -07:00
8290ad8828
minor update
2020-10-20 05:49:45 -07:00
7529f72c5d
fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags
2020-10-20 05:32:55 -07:00
301cc45740
scope fixes
2020-10-14 09:19:26 -07:00
58b8e82908
scope fixes ...
2020-10-13 17:09:22 -04:00
4bfc4ee78f
scope fixes
2020-10-13 08:44:55 -07:00
99e209b7a2
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2020-10-12 20:35:44 -07:00
7334896665
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2020-10-12 20:33:32 -07:00
32da50816f
scope refactoring: adding modules definitions to VCD trace
2020-10-12 23:26:02 -04:00
a83048b3bd
Comments
2020-10-06 14:50:56 -04:00
1f4af4777c
Comments
2020-10-06 14:35:46 -04:00
309dd48fc6
scope bug fixes
2020-10-06 03:59:27 -04:00
d2ab8d3cc6
Added comments to prep for cache presentation
2020-10-05 14:49:47 -04:00
4e1007e5b2
scope refactoring
2020-10-03 18:53:21 -04:00
a10d6fed47
update Makefile
2020-09-24 18:29:09 -07:00
878c89861b
CI script updates
2020-09-20 01:44:14 -04:00
990b1585f1
CI script updates
2020-09-20 01:27:34 -04:00
b3a52f4002
minor update
2020-09-20 00:43:01 -04:00
c9d38c2b80
CI script updates
2020-09-20 00:17:42 -04:00
a8972af51e
Merge branch 'master' of https://github.com/vortexgpgpu/vortex-dev
2020-09-19 22:44:27 -04:00
0919210cfa
update CI scripts
2020-09-19 22:41:25 -04:00
409b9113cf
update CI scripts
2020-09-19 17:26:32 -04:00
e29c1a543d
update CI scripts
2020-09-19 17:00:45 -04:00
a7af253aa4
minor update
2020-09-19 16:25:44 -04:00
4f5fc0a1e9
Added passed print statement to current working opencl benchmarks
2020-09-19 16:10:24 -04:00
91f348c61a
adding prebuilt CI script
2020-09-19 16:08:28 -04:00
f6f95e0c46
mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
2020-09-19 14:45:42 -04:00
0646180059
Modified testbench.cpp to assume passed for runtime and isa tests.
2020-09-19 11:24:53 -04:00
959270def1
runtime tests hello modified to return 0 and vecadd modified to replace printf with vx_print_str.
2020-09-15 18:46:45 -04:00
dca5853191
Added "Passed" print to dev,nlTest,simple tests
2020-09-12 16:09:45 -04:00
80f929eb61
fixed build warnings; sgemm Makefile
2020-09-10 13:39:34 -04:00
38303cdc2f
vlsim: host_buffer optimization
2020-09-09 17:53:31 -04:00
adb6b9c44f
dev merge
2020-09-09 17:09:18 -04:00
fba2fa03c7
fixed new AFU Driver bugs - now functional
2020-09-09 17:05:48 -04:00
9b7187441d
updated from GT repo
2020-09-08 18:35:47 -04:00
bf7b0cf340
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2020-09-08 13:05:47 -04:00
0fab1ddd92
adding support for verilator-driven AFU driver: vlsim
2020-09-08 13:05:26 -04:00
807ce24e94
fixed committed instrs count
2020-09-08 07:54:12 -07:00
36ec603d17
fpga fixes: warp scheduler, fnmadd, fdiv, fsqrt
2020-09-08 07:05:26 -07:00
Blaise Tine