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e40a3feefa
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minor update
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2021-05-01 10:33:24 -07:00 |
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d504adb236
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afu mem controller refactoring
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2021-05-01 08:39:52 -07:00 |
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95f057bc2e
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fpga build refactoring
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2021-04-29 06:17:28 -07:00 |
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64848788a1
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minor update
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2021-04-26 20:34:28 -07:00 |
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8543e3a8bf
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code refactoring
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2021-04-26 02:34:21 -07:00 |
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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d808aa2735
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perf counters generic size
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2021-04-25 21:15:24 -07:00 |
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a60361ac2d
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minor update
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2021-04-25 21:10:54 -07:00 |
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cad21a4b92
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minor update
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2021-04-24 01:17:38 -04:00 |
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4cb98a25a7
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enabling 128-bit dram bus
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2021-04-24 00:31:27 -04:00 |
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aff5903a22
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minor ibuffer critical path optimization.
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2021-04-19 20:53:13 -07:00 |
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625689796f
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minor update
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2021-04-04 23:42:57 -07:00 |
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2ce6dbb495
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minor update
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2021-04-04 17:57:35 -07:00 |
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5cfd6e6f82
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minor updates
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2021-04-04 04:04:41 -07:00 |
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d522611ee2
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minor update
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2021-04-03 05:07:00 -07:00 |
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d6552a8851
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minor update
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2021-04-03 04:24:37 -07:00 |
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f829bd3c18
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minor update
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2021-04-03 04:22:44 -07:00 |
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1e2da696ce
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arrays logging
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2021-04-02 02:20:15 -07:00 |
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a75accf6ed
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minor update
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2021-04-01 23:31:55 -07:00 |
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638614fd6d
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decode optimization
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2021-04-01 19:08:15 -07:00 |
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04a96e89c9
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minor update
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2021-04-01 12:34:18 -07:00 |
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a194521683
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minor update
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2021-03-31 02:37:16 -07:00 |
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d15e33e87f
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fpu dpi update
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2021-03-31 02:36:34 -07:00 |
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b3167d763b
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minor update
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2021-03-30 22:08:26 -07:00 |
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16bef8937b
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adding empty to index_buffer
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2021-03-30 10:15:42 -07:00 |
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b33a994f49
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minor update
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2021-03-29 23:51:05 -07:00 |
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fc70bb3a4a
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databus optimization
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2021-03-29 23:48:04 -07:00 |
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8d4e2e7f70
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minor update
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2021-03-22 23:04:54 -07:00 |
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09dbeacc14
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minor update
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2021-03-22 23:04:35 -07:00 |
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af1bb33557
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minor update
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2021-03-21 16:38:53 -07:00 |
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bd40e7db70
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minor update - mux reordering to reduce critical path on input data
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2021-03-21 11:43:57 -07:00 |
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f7d6b71ac2
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minor update
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2021-03-21 11:40:54 -07:00 |
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09194a8501
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minor update
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2021-03-21 11:39:33 -07:00 |
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e85fa9d842
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fixed FCVT timing critical path
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2021-03-18 13:26:36 -07:00 |
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a79253329c
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relaxing commit back-pressure in writeback stage
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2021-03-15 14:39:55 -07:00 |
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10a994d11a
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csr minor update
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2021-03-08 03:46:07 -08:00 |
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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8a86bddd3e
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fixed simX multicore support, added shared memory
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2021-03-04 20:45:27 -08:00 |
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Blaise Tine
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5e3a949d2d
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floating-point conversion fix
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2021-03-01 06:11:03 -08:00 |
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Blaise Tine
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b023496ecb
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minor update
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2021-03-01 03:00:58 -08:00 |
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Blaise Tine
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ad06408044
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minor update
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2021-03-01 01:51:25 -08:00 |
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Blaise Tine
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0e3872ee94
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floating-point CSR fix
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2021-03-01 01:46:41 -08:00 |
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Blaise Tine
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b441870789
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rename use_imm and use_PC
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2021-03-01 00:38:46 -08:00 |
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Blaise Tine
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e3a11e4a5c
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minor fix
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2021-02-28 14:18:43 -08:00 |
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Blaise Tine
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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Blaise Tine
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e64996946d
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using 44-bit perf counters - aligned with DSP counters width
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2021-02-28 02:05:47 -08:00 |
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Blaise Tine
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8a9a67aa5a
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minor update
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2021-02-27 21:54:55 -08:00 |
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Blaise Tine
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f5a17bd1a9
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decode optimization and refactoring
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2021-02-27 18:21:41 -08:00 |
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Blaise Tine
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ebee332e9d
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minor update
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2021-02-27 02:31:05 -08:00 |
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Blaise Tine
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20d704b4d3
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skid buffer optimization
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2021-02-27 02:29:48 -08:00 |
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