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e3a11e4a5c4a8ec092a89e143b3b1684557ae065
vortex/hw/rtl
History
Blaise Tine e3a11e4a5c minor fix
2021-02-28 14:18:43 -08:00
..
afu
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
cache
using shiftreg-based skid buffers
2021-02-28 02:20:09 -08:00
fp_cores
minor update
2021-02-12 08:52:06 -08:00
interfaces
using 44-bit perf counters - aligned with DSP counters width
2021-02-28 02:05:47 -08:00
libs
using shiftreg-based skid buffers
2021-02-28 02:20:09 -08:00
tex_unit
modelsim fixes && pipeline optimization
2020-07-28 14:20:23 -07:00
.DS_Store
project directories reorganization
2020-04-14 06:35:20 -04:00
.gitignore
fix opae build
2020-04-20 12:51:42 -07:00
Vortex.v
cache bank refactoring - removing unecessary core response fifo & restoring single port data access
2021-02-21 21:47:46 -08:00
VX_alu_unit.v
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_cluster.v
cache bank refactoring - removing unecessary core response fifo & restoring single port data access
2021-02-21 21:47:46 -08:00
VX_commit.v
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_config.vh
using shiftreg-based skid buffers
2021-02-28 02:20:09 -08:00
VX_core.v
cache request interfaces update
2021-02-10 20:55:04 -08:00
VX_csr_arb.v
minor update
2021-02-12 08:52:06 -08:00
VX_csr_data.v
using 44-bit perf counters - aligned with DSP counters width
2021-02-28 02:05:47 -08:00
VX_csr_io_arb.v
using shiftreg-based skid buffers
2021-02-28 02:20:09 -08:00
VX_csr_unit.v
fixed loader script stack setup
2020-12-31 22:37:20 -05:00
VX_databus_arb.v
using shiftreg-based skid buffers
2021-02-28 02:20:09 -08:00
VX_decode.v
minor fix
2021-02-28 14:18:43 -08:00
VX_define.vh
minor update
2021-02-27 21:54:55 -08:00
VX_execute.v
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_fetch.v
cache request interfaces update
2021-02-10 20:55:04 -08:00
VX_fpu_unit.v
fcvt fix
2021-01-25 02:22:00 -08:00
VX_gpr_ram_f.v
minor update
2021-01-01 20:24:18 -08:00
VX_gpr_ram_i.v
fixed register file initialization to zero synthesis inference
2020-12-10 00:27:56 -08:00
VX_gpr_stage.v
fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
2021-01-11 23:55:09 -08:00
VX_gpu_unit.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
VX_ibuffer.v
using shiftreg-based skid buffers
2021-02-28 02:20:09 -08:00
VX_icache_stage.v
cache request interfaces update
2021-02-10 20:55:04 -08:00
VX_instr_demux.v
using shiftreg-based skid buffers
2021-02-28 02:20:09 -08:00
VX_ipdom_stack.v
critical path optimization - fpga fmax @4c = ~212 mhz
2020-12-26 03:28:32 -08:00
VX_issue.v
using 44-bit perf counters - aligned with DSP counters width
2021-02-28 02:05:47 -08:00
VX_lsu_unit.v
minor update
2021-02-27 21:54:55 -08:00
VX_mem_arb.v
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
VX_mem_unit.v
using 44-bit perf counters - aligned with DSP counters width
2021-02-28 02:05:47 -08:00
VX_muldiv.v
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_pipeline.v
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_platform.vh
cache specialization for in-order DRAM reponses
2021-02-13 20:23:29 -08:00
VX_print_instr.vh
minor update
2021-02-27 21:54:55 -08:00
VX_scope.vh
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00
VX_scoreboard.v
lkg build rollout with 16cores optimization on arria10
2021-01-24 16:49:22 -08:00
VX_types.vh
FPU float<->int conversion optimization
2020-12-29 15:37:45 -08:00
VX_warp_sched.v
minor update
2021-02-22 13:30:45 -08:00
VX_writeback.v
moving MUL unit into ALU unit
2021-02-23 13:49:02 -08:00