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d15e33e87f
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fpu dpi update
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2021-03-31 02:36:34 -07:00 |
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b3167d763b
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minor update
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2021-03-30 22:08:26 -07:00 |
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a84a6fe8a9
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minor update
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2021-03-30 13:18:32 -07:00 |
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16bef8937b
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adding empty to index_buffer
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2021-03-30 10:15:42 -07:00 |
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b33a994f49
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minor update
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2021-03-29 23:51:05 -07:00 |
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fc70bb3a4a
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databus optimization
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2021-03-29 23:48:04 -07:00 |
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1f0be84eea
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16 core specific json file
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2021-03-29 23:41:48 -07:00 |
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817bc711c8
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fixed startix10 build configuration
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2021-03-23 08:34:35 -07:00 |
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8d4e2e7f70
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minor update
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2021-03-22 23:04:54 -07:00 |
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09dbeacc14
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minor update
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2021-03-22 23:04:35 -07:00 |
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af1bb33557
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minor update
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2021-03-21 16:38:53 -07:00 |
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bd40e7db70
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minor update - mux reordering to reduce critical path on input data
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2021-03-21 11:43:57 -07:00 |
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f7d6b71ac2
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minor update
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2021-03-21 11:40:54 -07:00 |
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09194a8501
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minor update
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2021-03-21 11:39:33 -07:00 |
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e85fa9d842
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fixed FCVT timing critical path
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2021-03-18 13:26:36 -07:00 |
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a79253329c
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relaxing commit back-pressure in writeback stage
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2021-03-15 14:39:55 -07:00 |
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Blaise Tine
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66ea340d05
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Fix RAM memory deallocation
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2021-03-09 01:52:56 -08:00 |
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10a994d11a
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csr minor update
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2021-03-08 03:46:07 -08:00 |
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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Blaise Tine
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8a86bddd3e
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fixed simX multicore support, added shared memory
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2021-03-04 20:45:27 -08:00 |
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5e3a949d2d
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floating-point conversion fix
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2021-03-01 06:11:03 -08:00 |
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b023496ecb
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minor update
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2021-03-01 03:00:58 -08:00 |
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c8af5a8f45
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minor update
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2021-03-01 02:56:58 -08:00 |
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ad06408044
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minor update
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2021-03-01 01:51:25 -08:00 |
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0e3872ee94
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floating-point CSR fix
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2021-03-01 01:46:41 -08:00 |
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b441870789
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rename use_imm and use_PC
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2021-03-01 00:38:46 -08:00 |
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a9cb0b4ec1
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minor update - asesim fix
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2021-02-28 17:30:21 -08:00 |
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e3a11e4a5c
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minor fix
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2021-02-28 14:18:43 -08:00 |
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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e64996946d
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using 44-bit perf counters - aligned with DSP counters width
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2021-02-28 02:05:47 -08:00 |
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8a9a67aa5a
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minor update
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2021-02-27 21:54:55 -08:00 |
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f5a17bd1a9
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decode optimization and refactoring
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2021-02-27 18:21:41 -08:00 |
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ebee332e9d
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minor update
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2021-02-27 02:31:05 -08:00 |
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20d704b4d3
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skid buffer optimization
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2021-02-27 02:29:48 -08:00 |
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34ce0b8e89
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minor update
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2021-02-23 20:54:03 -08:00 |
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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1792571e1b
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minor update
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2021-02-22 13:30:45 -08:00 |
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Blaise Tine
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1346d64ba9
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minor update
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2021-02-22 04:04:13 -08:00 |
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7560202f8b
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cache bank refactoring - removing unecessary core response fifo & restoring single port data access
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2021-02-21 21:47:46 -08:00 |
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ccb74ef286
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cache data access with decoupled read/write ports
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2021-02-21 15:18:24 -08:00 |
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Blaise Tine
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3e961c4e6e
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minor update
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2021-02-21 15:14:46 -08:00 |
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6739dc7923
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minor update - registering execute units skid buffers
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2021-02-21 15:11:08 -08:00 |
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f27c1fac5f
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minor update
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2021-02-21 03:38:24 -08:00 |
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6d7692da37
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minor fix.
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2021-02-21 03:37:36 -08:00 |
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258eb633a6
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minor update
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2021-02-20 13:16:25 -08:00 |
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05f93fac20
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minor update
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2021-02-20 13:15:15 -08:00 |
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Blaise Tine
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143319d557
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minor optimization
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2021-02-18 16:03:16 -08:00 |
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Blaise Tine
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31b3e380dc
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minor update
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2021-02-15 09:23:40 -08:00 |
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Blaise Tine
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9eed48435c
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instruction decode optimization
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2021-02-14 00:19:54 -08:00 |
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3c37db877a
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cache specialization for in-order DRAM reponses
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2021-02-13 20:23:29 -08:00 |
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