Blaise Tine bd40e7db70 minor update - mux reordering to reduce critical path on input data

2021-03-21 11:43:57 -07:00

..

configs

project directories reorganization

2020-04-14 06:35:20 -04:00

dpi

speeding up simulation using dedicated full dpi-based FPU core

2021-01-06 18:44:06 -08:00

models/memory

RTL code refactoring

2020-04-19 03:38:00 -04:00

modelsim

fixed simX multicore support, added shared memory

2021-03-04 20:45:27 -08:00

rtl

minor update - mux reordering to reduce critical path on input data

2021-03-21 11:43:57 -07:00

scripts

minor update

2021-03-01 03:00:58 -08:00

simulate

Merge branch 'master' of https://github.gatech.edu/casl/Vortex

2021-03-04 20:51:03 -08:00

syn

minor update

2021-03-01 02:56:58 -08:00

unit_tests

Fix RAM memory deallocation

2021-03-09 01:52:56 -08:00

.gitignore

adding dram writeenable support + scheduler bug fixes

2020-05-27 19:00:23 -04:00

Makefile

scope refactoring

2020-10-03 18:53:21 -04:00