wu-arch/vortex
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2,438 Commits 7 Branches 0 Tags
cde8da1f3b1354e2f0a5231d9089ed4e95eb3272
Commit Graph
344 Commits
Author SHA1 Message Date
Blaise Tine aff5903a22 minor ibuffer critical path optimization. 2021-04-19 20:53:13 -07:00
Blaise Tine 625689796f minor update 2021-04-04 23:42:57 -07:00
Blaise Tine d6552a8851 minor update 2021-04-03 04:24:37 -07:00
Blaise Tine 04a96e89c9 minor update 2021-04-01 12:34:18 -07:00
Blaise Tine 062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
Blaise Tine 3f5fd6d394 using shiftreg-based skid buffers 2021-02-28 02:20:09 -08:00
Blaise Tine e64996946d using 44-bit perf counters - aligned with DSP counters width 2021-02-28 02:05:47 -08:00
Blaise Tine 700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
Blaise Tine 1346d64ba9 minor update 2021-02-22 04:04:13 -08:00
Blaise Tine 7560202f8b cache bank refactoring - removing unecessary core response fifo & restoring single port data access 2021-02-21 21:47:46 -08:00
Blaise Tine ccb74ef286 cache data access with decoupled read/write ports 2021-02-21 15:18:24 -08:00
Blaise Tine 05f93fac20 minor update 2021-02-20 13:15:15 -08:00
Blaise Tine 9eed48435c instruction decode optimization 2021-02-14 00:19:54 -08:00
Blaise Tine 3c37db877a cache specialization for in-order DRAM reponses 2021-02-13 20:23:29 -08:00
Blaise Tine ab63ac9e5d cache request interfaces update 2021-02-10 20:55:04 -08:00
Blaise Tine 665b97b810 multi-ported cache support for streaming 2021-02-08 16:13:32 -08:00
Blaise Tine fd1726197b cache merge optimization 2021-02-07 07:33:39 -08:00
Blaise Tine 111cc29482 minor update 2021-02-04 15:28:04 -08:00
Blaise Tine 32b94f61f2 minor update 2021-02-01 11:00:09 -08:00
Blaise Tine 62ff97d6e1 minor update - smem perf update 2021-02-01 10:29:20 -08:00
Blaise Tine dc18bfabb8 minor update - remove mshr data store 2021-01-30 06:40:48 -08:00
Blaise Tine 5419859281 fcvt fix 2021-01-25 02:22:00 -08:00
Blaise Tine 8775f63ec4 lkg build rollout with 16cores optimization on arria10 2021-01-24 16:49:22 -08:00
Blaise Tine 74a687e395 minor updates 2021-01-18 05:43:30 -08:00
Blaise Tine b17f1109c6 minor updates 2021-01-18 04:34:34 -08:00
Blaise Tine a7f6b9fffc minor updates 2021-01-17 18:18:05 -08:00
Blaise Tine 8b42393189 minor updates 2021-01-17 17:33:41 -08:00
Blaise Tine a046bd7a73 cache pipeline optimization 2021-01-17 17:19:52 -08:00
Blaise Tine ed216ab39d minor updates 2021-01-17 13:58:43 -08:00
Blaise Tine a69ba5ad7b cache flush support 2021-01-17 05:50:29 -08:00
Blaise Tine d4e7b28be8 cache refactoring 2021-01-17 00:18:56 -08:00
Blaise Tine 5b80484123 minor updates 2021-01-16 14:16:10 -08:00
Blaise Tine a56ecb696d minor updates 2021-01-16 14:05:47 -08:00
Blaise Tine 4f26228d50 minor updates 2021-01-16 05:33:28 -08:00
Blaise Tine fcbf57b66a specialized shared memory module 2021-01-16 04:41:58 -08:00
Blaise Tine f146178c2d minor updates 2021-01-13 15:52:03 -08:00
Blaise Tine 0e1650e1c2 bank deadlock fix 2021-01-13 15:51:42 -08:00
Blaise Tine 79cc4d98e6 bank deadlock fix 2021-01-13 13:06:07 -08:00
Blaise Tine 464c4f4bd8 minor updates 2021-01-12 20:16:59 -08:00
Blaise Tine b4b5d6f0ab minor updates 2021-01-12 15:19:38 -08:00
Blaise Tine e770824d47 fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance 2021-01-10 20:26:15 -08:00
Blaise Tine 06945533cf fixed l2/l3 caches related bugs 2021-01-09 16:32:55 -08:00
Blaise Tine 146c285aa0 minor update 2021-01-06 19:59:04 -08:00
Blaise Tine 2058718f0f minor updates 2021-01-06 07:18:14 -08:00
Blaise Tine 31ff70fd4e minor updates 2021-01-05 15:03:41 -08:00
Blaise Tine 846a4036d3 minor update 2021-01-05 05:46:20 -08:00
Blaise Tine 39bff921be cache bug fixes 2021-01-05 05:04:49 -08:00
Blaise Tine 762b8e2e3e fixed cache mshr critical path 2021-01-04 12:49:40 -05:00
Blaise Tine 4d55118545 cache pipeline optimization - moved tag access to stage0 2021-01-03 23:10:41 -05:00
Blaise Tine 9cef1aae04 cache fill response address is the mshr's top address, no need to store it 2021-01-03 00:57:24 -05:00