Blaise Tine 0e1650e1c2 bank deadlock fix

2021-01-13 15:51:42 -08:00

..

VX_bank.v

bank deadlock fix

2021-01-13 15:51:42 -08:00

VX_cache_config.vh

scratchpad optimization for stack access using custom bank offset aligned to stack size

2021-01-02 16:00:00 -05:00

VX_cache_core_req_bank_sel.v

minor updates

2021-01-12 15:19:38 -08:00

VX_cache_core_rsp_merge.v

critical path optimization - fpga fmax @4c = ~212 mhz

2020-12-26 03:28:32 -08:00

VX_cache.v

minor updates

2021-01-12 15:19:38 -08:00

VX_data_access.v

fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance

2021-01-10 20:26:15 -08:00

VX_data_store.v

fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance

2021-01-10 20:26:15 -08:00

VX_fifo_queue_xt.v

fixed l2/l3 caches related bugs

2021-01-09 16:32:55 -08:00

VX_miss_resrv.v

fixed l2/l3 caches related bugs

2021-01-09 16:32:55 -08:00

VX_tag_access.v

cache pipeline optimization - moved tag access to stage0

2021-01-03 23:10:41 -05:00

VX_tag_store.v

cache pipeline optimization - moved tag access to stage0

2021-01-03 23:10:41 -05:00