Sungwoong Ha
a9709edae2
first pass
2024-03-01 21:05:52 -08:00
Sungwoong Ha
be7d87c82d
temp
2024-02-22 16:31:42 -08:00
Blaise Tine
be0db6e1a5
minor update
2024-02-04 20:32:05 -08:00
Blaise Tine
8d4b6c804f
minor update
2024-02-04 20:17:12 -08:00
Blaise Tine
6f7a389a1f
arbiters unlock refactoring
2024-02-04 20:16:18 -08:00
Blaise Tine
fe15647f98
minor update
2024-02-04 02:11:53 -08:00
Blaise Tine
b0b7cd2b1e
minor updates
2024-02-03 19:09:53 -08:00
Hansung Kim
eb63767051
Don't hardcode SIMULATION
2024-02-01 23:58:06 -08:00
Hansung Kim
48558982f7
Merge remote-tracking branch 'upstream/master' into vortex2
2024-02-01 23:35:58 -08:00
Hansung Kim
a15f4fd483
[BUGFIX] Set mem_req_mask to 0 for fence
...
Fence instructions have address field set to X's which propagates to
cache_req_ready, causing issue stalls. Fix this by setting req_mask to all-zero
so that they can be handled unaffected by x-propagation.
Setting req_valid to 0 does not fix the problem because the LSU only commits
instructions when they have a matching response coming back.
2024-02-01 22:44:33 -08:00
Blaise Tine
f9cd8be19e
minor update
2024-01-31 13:35:43 -08:00
Blaise Tine
8ab7c590fd
disabling fetch's deadlock check when L1 caches are present
2024-01-31 06:16:54 -08:00
Blaise Tine
e2d1387df8
elastic buffers classification
2024-01-31 00:39:37 -08:00
Blaise Tine
38b92ad592
- using SV_DPI defines to disable DPI in synthesis-based simulations
...
- fixed Intel ASE run script: run_ase.sh
2024-01-28 00:22:21 -08:00
Hansung Kim
4643edf3e9
Properly determine core finish
2024-01-26 14:23:52 -08:00
Hansung Kim
c9d1275f0e
Define SIMULATION under VERILATOR
2024-01-25 23:23:34 -08:00
Hansung Kim
60d4180249
Increase LSUQ and IBUF size
2024-01-16 23:53:14 -08:00
Hansung Kim
62171c0788
Change dmem/smem width to LSU lanes not core lanes
2024-01-04 01:34:24 -08:00
Hansung Kim
fd425f1cdf
Change smem bundles into flattened 1-D arrays
2024-01-04 00:52:56 -08:00
Hansung Kim
e6f6d4ea06
Change dmem bundles into flattened 1-D arrays
2024-01-04 00:37:59 -08:00
Hansung Kim
ab55c04d0c
Add localparam for internal/external smem switch
2024-01-01 19:48:06 -08:00
Hansung Kim
b64f0c2794
Add if-stmt to switch between external/internal smem
2024-01-01 12:46:59 -08:00
Hansung Kim
22f656fec1
Add ports for smem TL and connect to smem bus
2024-01-01 02:22:49 -08:00
Hansung Kim
b6cc0c285e
Remove unused tilelink ports in VX_core_wrapper
2024-01-01 01:09:55 -08:00
Hansung Kim
144521e19c
Expose smem ports at VX_core top
...
smem_unit stays inside the core, and the two separate buses to dcache
and smem are exposed at VX_core.
Currently core_wrapper ties req valid to 1'b0, stalling kernels that
reads from sharedmem.
2023-12-31 23:57:31 -08:00
Blaise Tine
031d24e695
minor updates
2023-12-30 00:52:44 -08:00
Blaise Tine
e217bc2c23
adding tracking for SFU stalls
2023-12-28 12:12:11 -08:00
Blaise Tine
c7a81d1493
adding sockets support to simx and cache subsystem refactoring
...
minor update
minor update
minor updates
2023-12-20 15:16:12 -08:00
Blaise Tine
914b680aed
operands optimization
...
minor updates
minor updates
minor update
operands optimization
minor updates
minor updates
2023-12-20 15:07:23 -08:00
Blaise Tine
e04e026a14
profiling update
...
minor updates
2023-12-18 04:43:44 -08:00
Blaise Tine
c6845a4c8d
profiling timing optimization
...
minor update
minor update
minor update
2023-12-18 04:43:10 -08:00
Blaise Tine
f5f9e3dfdb
profiling timing optimization
2023-12-18 04:43:10 -08:00
Blaise Tine
6c7ac35054
profiling optimizations
...
minor updates
2023-12-18 04:43:00 -08:00
Blaise Tine
e5b41bcd66
wctl unit bug fix
2023-12-05 04:57:52 -08:00
Blaise Tine
1912f52bee
profiling bug fix
2023-12-05 04:56:46 -08:00
root
900a1efaca
BUFFER_EX refactoring
2023-12-05 04:55:50 -08:00
Hansung Kim
5825680303
[BUGFIX] Revert way_idx fix
...
The added code results in width mismatch for NUM_WAYS = 4.
2023-11-28 18:44:47 -08:00
Hansung Kim
c3c9a4b5d8
[BUGFIX] Fix wrong bitwidth of way_idx when NUM_WAYS=1
...
When NUM_WAYS=1, CLOG2(NUM_WAYS)-1 becomes -1, setting the MSB of
way_idx to a wrong value.
2023-11-28 16:05:41 -08:00
Hansung Kim
9a8020a683
Force-include gpu_pkg in VX_cache_define.vh
2023-11-28 13:55:11 -08:00
Blaise Tine
9c2916f3fc
minor update
2023-11-28 12:03:48 -08:00
Blaise Tine
e8d56dc013
minor update
2023-11-27 22:16:36 -08:00
Hansung Kim
5e5c625759
Write 0 instead of x for VX_CSR_MPM_RESERVED
...
Otherwise it makes verification hard with tools that don't process x's
well.
2023-11-27 16:06:16 -08:00
Hansung Kim
f41b50fc07
Define DBG_TRACE_CORE_PIPELINE_VCS for selective debug trace
2023-11-27 16:05:15 -08:00
Blaise Tine
24973ffca0
scoreboard optimization & profiling
2023-11-27 05:53:36 -08:00
Blaise Tine
4b68235389
fixed simx dispatcher bug
2023-11-27 04:50:55 -08:00
Blaise Tine
ebec982434
minor update
2023-11-27 02:04:53 -08:00
Hansung Kim
99207c862c
Revert PutPartial -> PutFull spoofing
2023-11-19 17:48:38 -08:00
Hansung Kim
e2d4894343
Add missing valid bit check for write acks
2023-11-17 20:32:53 -08:00
Hansung Kim
bc71c126ef
Fix STORE HEAP trace print in verilog wrapper
2023-11-17 20:25:01 -08:00
Hansung Kim
faf5fe3838
Assert ready when write response is coming back
...
Since the core's response ready signal depends on response valid, but core does
not accept write ACKs, we need to manually assert ready when there is a valid
response coming in for a write regardless of the core's ready state (which would
be 0).
2023-11-17 19:08:32 -08:00
