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c3c9a4b5d831b0c05ab66142c3ebdada3dd0462d
vortex/hw/rtl
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Hansung Kim c3c9a4b5d8 [BUGFIX] Fix wrong bitwidth of way_idx when NUM_WAYS=1 
When NUM_WAYS=1, CLOG2(NUM_WAYS)-1 becomes -1, setting the MSB of
way_idx to a wrong value.
2023-11-28 16:05:41 -08:00
..
afu
Vortex 2.0 changes:
2023-10-19 20:51:22 -07:00
cache
[BUGFIX] Fix wrong bitwidth of way_idx when NUM_WAYS=1
2023-11-28 16:05:41 -08:00
core
Write 0 instead of x for VX_CSR_MPM_RESERVED
2023-11-27 16:06:16 -08:00
fpu
Change result type for dpi calls from wire -> reg
2023-11-15 19:26:12 -08:00
interfaces
Vortex 2.0 changes:
2023-10-19 20:51:22 -07:00
libs
[CHANGE] Work around uninitialized signal issue with === operator
2023-11-17 17:20:54 -08:00
mem
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
.DS_Store
project directories reorganization
2020-04-14 06:35:20 -04:00
Vortex_axi.sv
Vortex 2.0 changes:
2023-10-19 20:51:22 -07:00
Vortex.sv
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
VX_cluster.sv
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
VX_config.vh
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
VX_core_wrapper.sv
Revert PutPartial -> PutFull spoofing
2023-11-19 17:48:38 -08:00
VX_define.vh
minor update
2023-11-03 08:36:28 -04:00
VX_gpu_pkg.sv
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
VX_platform.vh
Define SIMULATION for VCS in VX_platform.vh
2023-11-15 19:14:58 -08:00
VX_scope.vh
Vortex 2.0 changes:
2023-10-19 20:51:22 -07:00
VX_socket.sv
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00
VX_types.vh
cache bindings and memory perf refactory
2023-11-03 08:18:18 -04:00