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Change dmem/smem width to LSU lanes not core lanes

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This commit is contained in:
Hansung Kim
2024-01-04 01:34:24 -08:00
parent fd425f1cdf
commit 62171c0788
1 changed files with 28 additions and 28 deletions
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56
hw/rtl/VX_core_wrapper.sv
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@@ -39,39 +39,39 @@ module Vortex import VX_gpu_pkg::*; #(
// dmem ------------------------------------------------
input [NUM_THREADS - 1:0] dmem_d_valid,
input [(NUM_THREADS * 3) - 1:0] dmem_d_bits_opcode,
input [(NUM_THREADS * 4) - 1:0] dmem_d_bits_size,
input [(NUM_THREADS * DCACHE_NOSM_TAG_WIDTH) - 1:0] dmem_d_bits_source,
input [(NUM_THREADS * 32) - 1:0] dmem_d_bits_data,
output [NUM_THREADS - 1:0] dmem_d_ready,
input [DCACHE_NUM_REQS - 1:0] dmem_d_valid,
input [(DCACHE_NUM_REQS * 3) - 1:0] dmem_d_bits_opcode,
input [(DCACHE_NUM_REQS * 4) - 1:0] dmem_d_bits_size,
input [(DCACHE_NUM_REQS * DCACHE_NOSM_TAG_WIDTH) - 1:0] dmem_d_bits_source,
input [(DCACHE_NUM_REQS * 32) - 1:0] dmem_d_bits_data,
output [DCACHE_NUM_REQS - 1:0] dmem_d_ready,
input [NUM_THREADS - 1:0] dmem_a_ready,
output [NUM_THREADS - 1:0] dmem_a_valid,
output [(NUM_THREADS * 3) - 1:0] dmem_a_bits_opcode,
output [(NUM_THREADS * 4) - 1:0] dmem_a_bits_size,
output [(NUM_THREADS * DCACHE_NOSM_TAG_WIDTH) - 1:0] dmem_a_bits_source,
output [(NUM_THREADS * 32) - 1:0] dmem_a_bits_address,
output [(NUM_THREADS * 4) - 1:0] dmem_a_bits_mask,
output [(NUM_THREADS * 32) - 1:0] dmem_a_bits_data,
input [DCACHE_NUM_REQS - 1:0] dmem_a_ready,
output [DCACHE_NUM_REQS - 1:0] dmem_a_valid,
output [(DCACHE_NUM_REQS * 3) - 1:0] dmem_a_bits_opcode,
output [(DCACHE_NUM_REQS * 4) - 1:0] dmem_a_bits_size,
output [(DCACHE_NUM_REQS * DCACHE_NOSM_TAG_WIDTH) - 1:0] dmem_a_bits_source,
output [(DCACHE_NUM_REQS * 32) - 1:0] dmem_a_bits_address,
output [(DCACHE_NUM_REQS * 4) - 1:0] dmem_a_bits_mask,
output [(DCACHE_NUM_REQS * 32) - 1:0] dmem_a_bits_data,
// smem ------------------------------------------------
input [NUM_THREADS - 1:0] smem_d_valid,
input [(NUM_THREADS * 3) - 1:0] smem_d_bits_opcode,
input [(NUM_THREADS * 4) - 1:0] smem_d_bits_size,
input [(NUM_THREADS * DCACHE_NOSM_TAG_WIDTH) - 1:0] smem_d_bits_source,
input [(NUM_THREADS * 32) - 1:0] smem_d_bits_data,
output [NUM_THREADS - 1:0] smem_d_ready,
input [DCACHE_NUM_REQS - 1:0] smem_d_valid,
input [(DCACHE_NUM_REQS * 3) - 1:0] smem_d_bits_opcode,
input [(DCACHE_NUM_REQS * 4) - 1:0] smem_d_bits_size,
input [(DCACHE_NUM_REQS * DCACHE_NOSM_TAG_WIDTH) - 1:0] smem_d_bits_source,
input [(DCACHE_NUM_REQS * 32) - 1:0] smem_d_bits_data,
output [DCACHE_NUM_REQS - 1:0] smem_d_ready,
input [NUM_THREADS - 1:0] smem_a_ready,
output [NUM_THREADS - 1:0] smem_a_valid,
output [(NUM_THREADS * 3) - 1:0] smem_a_bits_opcode,
output [(NUM_THREADS * 4) - 1:0] smem_a_bits_size,
output [(NUM_THREADS * DCACHE_NOSM_TAG_WIDTH) - 1:0] smem_a_bits_source,
output [(NUM_THREADS * 32) - 1:0] smem_a_bits_address,
output [(NUM_THREADS * 4) - 1:0] smem_a_bits_mask,
output [(NUM_THREADS * 32) - 1:0] smem_a_bits_data,
input [DCACHE_NUM_REQS - 1:0] smem_a_ready,
output [DCACHE_NUM_REQS - 1:0] smem_a_valid,
output [(DCACHE_NUM_REQS * 3) - 1:0] smem_a_bits_opcode,
output [(DCACHE_NUM_REQS * 4) - 1:0] smem_a_bits_size,
output [(DCACHE_NUM_REQS * DCACHE_NOSM_TAG_WIDTH) - 1:0] smem_a_bits_source,
output [(DCACHE_NUM_REQS * 32) - 1:0] smem_a_bits_address,
output [(DCACHE_NUM_REQS * 4) - 1:0] smem_a_bits_mask,
output [(DCACHE_NUM_REQS * 32) - 1:0] smem_a_bits_data,
// input fpu_fcsr_flags_valid,
// input [4:0] fpu_fcsr_flags_bits,