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2,460 Commits 7 Branches 0 Tags
69cbbdd89b0ea0e4769dd4875bcb4f696e228203
Commit Graph
225 Commits
Author SHA1 Message Date
Blaise Tine 377466ed1c fpu area optimization 2021-09-05 21:01:52 -07:00
Blaise Tine f3ba27b138 GPRs optimization - disabling BRAM's read-during-write bypass block. 2021-08-28 15:34:36 -07:00
Blaise Tine 28eb3cfdb2 minor update 2021-08-26 14:49:57 -07:00
Blaise Tine 74a45e2772 stream arbiter optimization (using indexing instead of onehot mux) 2021-08-26 09:52:13 -07:00
Blaise Tine d91d56d126 block ram refactoring (multi-porting supporting and simulation support) 2021-08-26 08:19:44 -07:00
Blaise Tine e494860f38 using lzc instead of priority_encoder 2021-08-26 07:29:47 -07:00
Blaise Tine 2a27bfbfd5 LKG Build (reset network update -fmax=236 mhz 4c) 2021-08-23 01:59:22 -07:00
Blaise Tine eef3dda81d fixed Verilator error 2021-08-13 19:33:12 -07:00
Blaise Tine 646371f9e9 bram block optimization 2021-08-13 19:31:55 -07:00
Blaise Tine f12be56d7c fixed Verilator warnings 2021-08-13 05:52:43 -04:00
Blaise Tine 7961cf7474 Disabling tracing on library 2021-08-12 01:55:52 -07:00
Blaise Tine 7b8fe11e6a unused variables refactoring 2021-08-05 01:46:26 -07:00
Blaise Tine 79fd92a1b4 minor update 2021-07-30 17:43:15 -07:00
Blaise Tine 160ff94a22 minor update 2021-07-30 16:01:22 -07:00
Blaise Tine 3d19588e57 bus arbiters refactoring 2021-07-30 16:00:09 -07:00
Blaise Tine ea1e0f201e OUTPUT_REG refactoring 2021-07-23 06:58:37 -07:00
Blaise Tine 5c58f7eec6 minor update 2021-07-16 12:57:50 -07:00
Blaise Tine a8f9a2559d minor update 2021-07-15 12:25:51 -07:00
Blaise Tine c5aec572b5 minor update 2021-07-15 11:46:43 -07:00
Blaise Tine 7d01be367c reset network refactoring 2021-07-15 11:34:55 -07:00
Blaise Tine 22cf698e69 minor update 2021-07-13 05:25:44 -07:00
Blaise Tine 10e9ee124b using onehot multiplexer to reduce critical path 2021-07-08 00:26:59 -07:00
Blaise Tine dc34c5c5bd minor update 2021-07-03 04:47:19 -07:00
Blaise Tine 93fee18d59 minor update 2021-07-01 02:59:44 -07:00
Blaise Tine 1ea738ed26 lkg build 2021-06-25 16:28:10 -07:00
Blaise Tine a3a7239b4d critical path optimizations 2021-06-23 01:51:23 -07:00
Blaise Tine b8fd2308e1 arbiter specialization 2021-06-22 21:02:37 -07:00
Blaise Tine 57143f5889 synthesis optimizations 2021-06-17 16:43:43 -07:00
Blaise Tine 47c3234659 minor update 2021-06-13 10:58:48 -07:00
Blaise Tine adf033b0aa non-cacheable memory address critical paths optimizations 2021-06-10 12:47:18 -07:00
Blaise Tine aff5903a22 minor ibuffer critical path optimization. 2021-04-19 20:53:13 -07:00
Blaise Tine 16bef8937b adding empty to index_buffer 2021-03-30 10:15:42 -07:00
Blaise Tine b33a994f49 minor update 2021-03-29 23:51:05 -07:00
Blaise Tine bd40e7db70 minor update - mux reordering to reduce critical path on input data 2021-03-21 11:43:57 -07:00
Blaise Tine 062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
Blaise Tine 3f5fd6d394 using shiftreg-based skid buffers 2021-02-28 02:20:09 -08:00
Blaise Tine ebee332e9d minor update 2021-02-27 02:31:05 -08:00
Blaise Tine 20d704b4d3 skid buffer optimization 2021-02-27 02:29:48 -08:00
Blaise Tine 700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
Blaise Tine 143319d557 minor optimization 2021-02-18 16:03:16 -08:00
Blaise Tine 073964fdf7 minor update 2021-02-12 08:52:06 -08:00
Blaise Tine 72b6713a72 updating fdiv/fsqrt bram hex files, reset_delay updaet 2021-02-04 09:02:18 -08:00
Blaise Tine 5419859281 fcvt fix 2021-01-25 02:22:00 -08:00
Blaise Tine 8775f63ec4 lkg build rollout with 16cores optimization on arria10 2021-01-24 16:49:22 -08:00
Blaise Tine a046bd7a73 cache pipeline optimization 2021-01-17 17:19:52 -08:00
Blaise Tine ed216ab39d minor updates 2021-01-17 13:58:43 -08:00
Blaise Tine d4e7b28be8 cache refactoring 2021-01-17 00:18:56 -08:00
Blaise Tine ad6e0b4e77 sp_ram byteen fix 2021-01-15 16:28:03 -08:00
Blaise Tine fe64c47f60 ccip write fix 2021-01-14 22:49:06 -08:00
Blaise Tine b4b5d6f0ab minor updates 2021-01-12 15:19:38 -08:00