Commit Graph

486 Commits

Author SHA1 Message Date
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6107bf8247 minor fix 2021-05-04 11:05:07 -07:00
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8f451aa74c minor update 2021-05-04 08:01:49 -07:00
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bde6a69ea0 adding support for multi-banks memory bus 2021-05-04 07:32:03 -07:00
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228aee1ec7 lsu_unit pending queue bug fix 2021-05-03 12:25:44 -07:00
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bac53e4ae1 minor update 2021-05-02 11:05:49 -07:00
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04a1c0e9eb IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr 2021-05-01 13:44:08 -07:00
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e40a3feefa minor update 2021-05-01 10:33:24 -07:00
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d504adb236 afu mem controller refactoring 2021-05-01 08:39:52 -07:00
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95f057bc2e fpga build refactoring 2021-04-29 06:17:28 -07:00
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64848788a1 minor update 2021-04-26 20:34:28 -07:00
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8543e3a8bf code refactoring 2021-04-26 02:34:21 -07:00
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8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
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d808aa2735 perf counters generic size 2021-04-25 21:15:24 -07:00
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a60361ac2d minor update 2021-04-25 21:10:54 -07:00
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cad21a4b92 minor update 2021-04-24 01:17:38 -04:00
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4cb98a25a7 enabling 128-bit dram bus 2021-04-24 00:31:27 -04:00
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aff5903a22 minor ibuffer critical path optimization. 2021-04-19 20:53:13 -07:00
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625689796f minor update 2021-04-04 23:42:57 -07:00
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2ce6dbb495 minor update 2021-04-04 17:57:35 -07:00
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5cfd6e6f82 minor updates 2021-04-04 04:04:41 -07:00
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d522611ee2 minor update 2021-04-03 05:07:00 -07:00
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d6552a8851 minor update 2021-04-03 04:24:37 -07:00
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f829bd3c18 minor update 2021-04-03 04:22:44 -07:00
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1e2da696ce arrays logging 2021-04-02 02:20:15 -07:00
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a75accf6ed minor update 2021-04-01 23:31:55 -07:00
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638614fd6d decode optimization 2021-04-01 19:08:15 -07:00
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04a96e89c9 minor update 2021-04-01 12:34:18 -07:00
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a194521683 minor update 2021-03-31 02:37:16 -07:00
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d15e33e87f fpu dpi update 2021-03-31 02:36:34 -07:00
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b3167d763b minor update 2021-03-30 22:08:26 -07:00
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16bef8937b adding empty to index_buffer 2021-03-30 10:15:42 -07:00
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b33a994f49 minor update 2021-03-29 23:51:05 -07:00
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fc70bb3a4a databus optimization 2021-03-29 23:48:04 -07:00
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8d4e2e7f70 minor update 2021-03-22 23:04:54 -07:00
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09dbeacc14 minor update 2021-03-22 23:04:35 -07:00
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af1bb33557 minor update 2021-03-21 16:38:53 -07:00
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bd40e7db70 minor update - mux reordering to reduce critical path on input data 2021-03-21 11:43:57 -07:00
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f7d6b71ac2 minor update 2021-03-21 11:40:54 -07:00
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09194a8501 minor update 2021-03-21 11:39:33 -07:00
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e85fa9d842 fixed FCVT timing critical path 2021-03-18 13:26:36 -07:00
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a79253329c relaxing commit back-pressure in writeback stage 2021-03-15 14:39:55 -07:00
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10a994d11a csr minor update 2021-03-08 03:46:07 -08:00
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062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
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8a86bddd3e fixed simX multicore support, added shared memory 2021-03-04 20:45:27 -08:00
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5e3a949d2d floating-point conversion fix 2021-03-01 06:11:03 -08:00
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b023496ecb minor update 2021-03-01 03:00:58 -08:00
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ad06408044 minor update 2021-03-01 01:51:25 -08:00
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0e3872ee94 floating-point CSR fix 2021-03-01 01:46:41 -08:00
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b441870789 rename use_imm and use_PC 2021-03-01 00:38:46 -08:00
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e3a11e4a5c minor fix 2021-02-28 14:18:43 -08:00